ADS7828
ADS
78
®
28
SBAS181C – NOVEMBER 2001 - REVISED MARCH 2005
12-Bit, 8-Channel Sampling
ANALOG-TO-DIGITAL CONVERTER
with I2C™ Interface
DESCRIPTION
FEATURES
●
●
●
●
●
●
8-CHANNEL MULTIPLEXER
50kHz SAMPLING RATE
NO MISSING CODES
2.7V TO 5V OPERATION
INTERNAL 2.5V REFERENCE
I2C INTERFACE SUPPORTS:
Standard, Fast, and High-Speed Modes
● TSSOP-16 PACKAGE
The ADS7828 is a single-supply, low-power, 12-bit data
acquisition device that features a serial I2C interface and an
8-channel multiplexer. The Analog-to-Digital (A/D) converter
features a sample-and-hold amplifier and internal,
asynchronous clock. The combination of an I2C serial,
2-wire interface and micropower consumption makes the
ADS7828 ideal for applications requiring the A/D converter to
be close to the input source in remote locations and for
applications requiring isolation. The ADS7828 is available in
a TSSOP-16 package.
APPLICATIONS
●
●
●
●
●
VOLTAGE-SUPPLY MONITORING
ISOLATED DATA ACQUISITION
TRANSDUCER INTERFACES
BATTERY-OPERATED SYSTEMS
REMOTE DATA ACQUISITION
CH0
SAR
CH1
CH2
CH3
CH4
8-Channel
MUX
CH5
SDA
CH6
CH7
CDAC
Serial
Interface
COM
SCL
A0
Comparator
S/H Amp
A1
2.5V VREF
REFIN/REFOUT
Buffer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Koninklijke Philps Electronics N.V. All other trademarks are the property of their respective owners.
Copyright © 2001-2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
+VDD to GND ........................................................................ –0.3V to +6V
Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V
Operating Temperature Range ...................................... –40°C to +105°C
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature (TJ max) .................................................... +150°C
TSSOP Package
Power Dissipation .................................................... (TJ max – TA)/θJA
θJA Thermal Impedance ........................................................ 240°C/W
Lead Temperature, Soldering
Vapor Phase (60s) ............................................................ +215°C
Infrared (15s) ..................................................................... +220°C
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
ADS7828E
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
±2
TSSOP-16
PW
–40°C to +85°C
ADS7828E/250
Tape and Reel, 250
"
"
"
"
ADS7828E/2K5
Tape and Reel, 2500
ADS7828EB
±1
TSSOP-16
PW
–40°C to +85°C
ADS7828EB/250
Tape and Reel, 250
"
"
"
"
"
ADS7828EB/2K5
Tape and Reel, 2500
PRODUCT
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com.
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
TSSOP
CH0
1
16
+VDD
CH1
2
15
SDA
CH2
3
14
SCL
CH3
4
13
A1
ADS7828
CH4
5
12
A0
CH5
6
11
COM
CH6
7
10
REFIN / REFOUT
CH7
8
9
GND
PIN
NAME
1
CH0
2
CH1
3
CH2
4
CH3
5
CH4
6
CH5
7
CH6
8
CH7
9
GND
10 REFIN / REFOUT
11
COM
12
A0
13
A1
14
SCL
15
SDA
16
+VDD
DESCRIPTION
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Analog Input Channel 6
Analog Input Channel 7
Analog Ground
Internal +2.5V Reference, External Reference Input
Common to Analog Input Channel
Slave Address Bit 0
Slave Address Bit 1
Serial Clock
Serial Data
Power Supply, 3.3V Nominal
ADS7828
2
www.ti.com
SBAS181C
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.
ADS7828E
PARAMETER
ANALOG INPUT
Full-Scale Input Scan
Absolute Input Range
CONDITIONS
MIN
Positive Input - Negative Input
Positive Input
Negative Input
0
–0.2
–0.2
Capacitance
Leakage Current
VOLTAGE REFERENCE OUTPUT
Range
Internal Reference Drift
Output Impedance
Quiescent Current
VOLTAGE REFERENCE INPUT
Range
Resistance
Current Drain
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels: VIH
VIL
VOL
Input Leakage: IIH
IIL
Data Format
Power Dissipation
Power-Down Mode
w/Wrong Address Selected
Full Power-Down
VREF
+VDD + 0.2
+0.2
0
–0.2
–0.2
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
VIN =
VIN =
VIN =
VIN =
2.5VPP
2.5VPP
2.5VPP
2.5VPP
at
at
at
at
TYP
2.475
Internal Reference ON
Internal Reference OFF
Int. Ref. ON, SCL and SDA pulled HIGH
±2
±0.5
±0.5
±0.75
±0.2
±0.75
±0.2
33
82
±3
±1
±4
±1
kHz
–82
72
71
86
120
–82
72
71
86
120
dB (2)
dB
dB
dB
dB
2.5
15
110
1
850
2.525
2.475
VDD
0.05
2.5
15
110
1
850
Straight
Binary
10010
10010
225
100
60
675
300
180
70
25
6
400
V
ppm/°C
Ω
GΩ
µA
VDD
V
GΩ
µA
+VDD + 0.5
+VDD • 0.3
0.4
10
V
V
V
µA
µA
CMOS
Straight
Binary
2.7
2.525
1
20
+VDD + 0.5 +VDD • 0.7
+VDD • 0.3
–0.3
0.4
10
–10
–10
–40
Bits
LSB (1)
LSB
LSB
LSB
LSB
LSB
µVRMS
dB
kHz
µs
CMOS
TEMPERATURE RANGE
Specified Performance
±1
–1, +2
±2
±1
±3
±1
6
+VDD • 0.7
–0.3
Specified Performance
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
SCL Pulled HIGH, SDA Pulled HIGH
V
V
V
pF
µA
50
8
2
1
20
Min. 3mA Sink Current
VIH = +VDD +0.5
VIL = -0.3
VREF
+VDD + 0.2
+0.2
6
0.05
High Speed Mode: SCL= 3.4MHz
UNITS
25
±1
50
8
2
10kHz
10kHz
10kHz
10kHz
MAX
12
±1.0
±1.0
±1.0
±0.2
±1.0
±0.2
33
82
ADS7828 HARDWARE ADDRESS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage, +VDD
Quiescent Current
MIN
12
Conversion Time
AC ACCURACY
Total Harmonic Distortion
Signal-to-Ratio
Signal-to-(Noise+Distortion) Ratio
Spurious-Free Dynamic Range
Isolation Channel-to-Channel
ADS7828EB
MAX
25
±1
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
Power-Supply Rejection
SAMPLING DYNAMICS
Throughput Frequency
TYP
3.6
320
2.7
225
100
60
675
300
180
70
25
6
400
1000
3000
85
–40
Binary
3.6
320
3000
V
µA
µA
µA
µW
µW
µW
µA
µA
µA
nA
85
°C
1000
NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV.
(2) THD measured out to the 9th-harmonic.
ADS7828
SBAS181C
3
www.ti.com
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +85°C, +VDD = +5.0V, VREF = External +5.0V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.
ADS7828E
PARAMETER
ANALOG INPUT
Full-Scale Input Scan
Absolute Input Range
CONDITIONS
MIN
Positive Input - Negative Input
Positive Input
Negative Input
0
–0.2
–0.2
Capacitance
Leakage Current
ADS7828EB
MAX
MIN
VREF
+VDD + 0.2
+0.2
0
–0.2
–0.2
25
±1
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
Power-Supply Rejection
SAMPLING DYNAMICS
Throughput Frequency
AC ACCURACY
Total Harmonic Distortion
Signal-to-Ratio
Signal-to-(Noise+Distortion) Ratio
Spurious-Free Dynamic Range
Isolation Channel-to-Channel
±1.0
VOLTAGE REFERENCE OUTPUT
Range
Internal Reference Drift
Output Impedance
Quiescent Current
VOLTAGE REFERENCE INPUT
Range
Resistance
Current Drain
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
at
at
at
at
10kHz
10kHz
10kHz
10kHz
2.475
Internal Reference ON
Internal Reference OFF
Int. Ref. ON, SCL and SDA pulled HIGH
±3
±1
±3
±1
±0.75
–82
72
71
86
120
–82
72
71
86
120
dB (2)
dB
dB
dB
dB
2.5
15
110
1
1300
50
8
2
2.525
2.475
VDD
0.05
2.525
V
ppm/°C
Ω
GΩ
µA
VDD
V
GΩ
µA
1
20
+VDD + 0.5 +VDD • 0.7
+VDD + 0.5
V
+VDD • 0.3
0.4
10
+VDD • 0.3
0.4
10
V
V
µA
µA
–10
4.75
2.5
15
110
1
1300
CMOS
–0.3
Specified Performance
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
Bits
LSB (1)
LSB
LSB
LSB
LSB
LSB
µVRMS
dB
±1
–1, +2
±2
±1
±2
±1
6
CMOS
ADS7828 HARDWARE ADDRESS
V
V
V
pF
µA
6
+VDD • 0.7
Min. 3mA Sink Current
VIH = +VDD +0.5
VIL = -0.3
VREF
+VDD + 0.2
+0.2
33
82
1
20
High Speed Mode: SCL = 3.4MHz
UNITS
kHz
kHz
kHz
µs
0.05
VIH
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage, +VDD
Quiescent Current
±0.5
±0.5
±0.75
50
8
2
DIGITAL INPUT/OUTPUT
Logic Family
VIL
VOL
Input Leakage: IIH
IIL
Data Format
±2
33
82
2.5VPP
2.5VPP
2.5VPP
2.5VPP
MAX
12
±1.0
±1.0
±1.0
VIN =
VIN =
VIN =
VIN =
TYP
25
±1
12
Conversion Time
Logic Levels:
TYP
–0.3
–10
Straight
Binary
Straight
Binary
10010
10010
5
750
300
150
5.25
1000
3.75
1.5
0.75
5
4.75
Binary
5
750
300
150
5.25
1000
V
µA
µA
µA
3.75
1.5
0.75
5
mW
mW
mW
Power Dissipation
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
Power-Down Mode
High Speed Mode: SCL = 3.4MHz
400
400
µA
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
150
35
150
35
µA
µA
SCL Pulled HIGH, SDA Pulled HIGH
400
w/Wrong Address Selected
Full Power-Down
TEMPERATURE RANGE
Specified Performance
–40
3000
+85
400
–40
3000
nA
+85
°C
NOTES: (1) LSB means Least Significant Bit. With VREF equal to 5.0V, 1LSB is 1.22mV.
(2) THD measured out to the 9th-harmonic.
ADS7828
4
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SBAS181C
TIMING DIAGRAM
SDA
tBUF
tLOW
tF
tR
tHD; STA
tSP
SCL
tHD; STA
tSU; STA
tHD; DAT
STOP
tHIGH
tSU; STO
tSU; DAT
START
REPEATED
START
TIMING CHARACTERISTICS(1)
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
SCL Clock Frequency
fSCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max
High-Speed Mode, CB = 400pF max
Bus Free Time Between a STOP and
START Condition
tBUF
Standard Mode
Fast Mode
4.7
1.3
µs
µs
Hold Time (Repeated) START
Condition
tHD;STA
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
LOW Period of the SCL Clock
tLOW
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.7
1.3
160
320
µs
µs
ns
ns
HIGH Period of the SCL Clock
tHIGH
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.0
600
60
120
µs
ns
ns
ns
Setup Time for a Repeated START
Condition
tSU;STA
Standard Mode
Fast Mode
High-Speed Mode
4.7
600
160
µs
ns
ns
Data Setup Time
tSU;DAT
Standard Mode
Fast Mode
High-Speed Mode
250
100
10
ns
ns
ns
Data Hold Time
tHD;DAT
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
0
0
0(3)
0(3)
3.45
0.9
70
150
µs
µs
ns
ns
tRCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
20 + 0.1CB
10
20
1000
300
40
80
ns
ns
ns
ns
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
20 + 0.1CB
10
20
1000
300
80
160
ns
ns
ns
ns
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
20 + 0.1CB
10
20
300
300
40
80
ns
ns
ns
ns
Rise Time of SCL Signal
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
tRCL1
Fall Time of SCL Signal
tFCL
MIN
MAX
UNITS
100
400
3.4
1.7
kHz
kHz
MHz
MHz
NOTES: (1) All values referred to VIHMIN and VILMAX levels.
(2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An
input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7828
SBAS181C
5
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TIMING CHARACTERISTICS(1) (Cont.)
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.
PARAMETER
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
SYMBOL
CONDITIONS
MIN
MAX
UNITS
tRDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
20 + 0.1CB
10
20
1000
300
80
160
ns
ns
ns
ns
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
20 + 0.1CB
10
20
300
300
80
160
ns
ns
ns
ns
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
tFDA
tSU; STO
µs
ns
ns
Capacitive Load for SDA and SCL
Line
CB
Pulse Width of Spike Suppressed
tSP
Noise Margin at the HIGH Level for
Each Connected Device (Including
Hysteresis)
VNH
Standard Mode
Fast Mode
High-Speed Mode
0.2VDD
V
Noise Margin at the LOW Level for
Each Connected Device (Including
Hysteresis)
VNL
Standard Mode
Fast Mode
High-Speed Mode
0.1VDD
V
Fast Mode
High-Speed Mode
400
pF
50
10
ns
ns
NOTES: (1) All values referred to VIHMIN and VILMAX levels.
(2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An
input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7828
6
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SBAS181C
TYPICAL CHARACTERISTICS
TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT: fIN = 1kHz, 0dB)
INTEGRAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
0.00
2.00
1.50
Amplitude (dB)
1.00
ILE (LSB)
–40.00
–80.00
0.50
0.00
–0.50
–1.00
–1.50
–120.0
–2.00
0
10
20
25
0
1024
2048
Output Code
Frequency (kHz)
2.00
2.00
1.50
1.50
1.00
1.00
0.50
0.50
ILE (LSB)
DLE (LSB)
4095
INTEGRAL LINEARITY ERROR vs CODE
(2.5V External Reference)
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
0.00
0.00
–0.50
–0.50
–1.00
–1.00
–1.50
–1.50
–2.00
–2.00
0
1024
2048
Output Code
3072
0
4095
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5V External Reference)
1024
2048
Output Code
3072
4095
CHANGE IN OFFSET vs TEMPERATURE
1.5
2.00
1.50
Delta from 25°C (LSB)
1.0
1.00
DLE (LSB)
3072
0.50
0.00
–0.50
–1.00
0.5
0.0
–0.5
–1.0
–1.50
–1.5
–2.00
0
1024
2048
Output Code
3072
–50
4095
0
25
50
75
100
Temperature (°C)
ADS7828
SBAS181C
–25
7
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
INTERNAL REFERENCE vs TEMPERATURE
2.51875
1.0
2.51250
Internal Reference (V)
Delta from 25°C (LSB)
CHANGE IN GAIN vs TEMPERATURE
1.5
0.5
0.0
–0.5
–1.0
2.50625
2.50000
2.49375
2.48750
–1.5
2.48125
–50
–25
0
25
50
75
100
–50
–25
0
Temperature (°C)
50
75
100
SUPPLY CURRENT vs TEMPERATURE
750
400
600
350
Supply Current (µA)
Supply Current (nA)
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
450
300
150
0
300
250
200
150
–150
100
–50
–25
0
25
50
75
100
125
–50
–25
0
Temperature (°C)
25
50
75
100
Temperature (°C)
SUPPLY CURRENT vs I2C BUS RATE
INTERNAL VREF vs TURN-ON TIME
300
100
250
No Cap
(42µs)
12-Bit Settling
80
200
Internal VREF (%)
Supply Current (µA)
25
Temperature (°C)
150
100
1µF Cap
(1240µs)
12-Bit Settling
60
40
20
50
0
0
10
100
1k
10k
0
I2C Bus Rate (KHz)
200
400
600
800
1000
1200
1400
Turn-On Time (µs)
ADS7828
8
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SBAS181C
THEORY OF OPERATION
internal +2.5V reference will provide full dynamic range for a
0V to +VDD analog input.
The ADS7828 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µ
CMOS process.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced.
The ADS7828 core is controlled by an internally generated
free-running clock. When the ADS7828 is not performing
conversions or being addressed, it keeps the A/D converter
core powered off, and the internal clock does not operate.
The noise inherent in the converter will also appear to increase
with lower LSB size. With a 2.5V reference, the internal noise
of the converter typically contributes only 0.32LSB peak-topeak of potential error to the output code. When the external
reference is 50mV, the potential error contribution from the
internal noise will be 50 times larger—16LSBs. The errors due
to the internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.
The simplified diagram of input and output for the ADS7828
is shown in Figure 1.
ANALOG INPUT
When the converter enters the hold mode, the voltage on the
selected CHx pin is captured on the internal capacitor array.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typically
25pF). After the capacitor has been fully charged, there is no
further input current. The amount of charge transfer from the
analog source to the converter is a function of conversion rate.
DIGITAL INTERFACE
The ADS7828 supports the I2C serial bus and data transmission protocol, in all three defined modes: standard, fast, and
high-speed. A device that sends data onto the bus is defined
as a transmitter, and a device receiving data as a receiver.
The device that controls the message is called a “master.”
The devices that are controlled by the master are “slaves.”
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The ADS7828
operates as a slave on the I2C bus. Connections to the bus
are made via the open-drain I/O lines SDA and SCL.
REFERENCE
The ADS7828 can operate with an internal 2.5V reference or
an external reference. If a +5V supply is used, an external
+5V reference is required in order to provide full dynamic
range for a 0V to +VDD analog input. This external reference
can be as low as 50mV. When using a +2.7V supply, the
+2.7V to +3.6V
5Ω
+ 1µF to
10µF
0.1µF
REFIN/
REFOUT
SDA
CH1
SCL
CH4
2kΩ
+ 1µF to
10µF
CH0
CH2 ADS7828
CH3
2kΩ
VDD
Microcontroller
A0
A1
GND
CH5
CH6
CH7
COM
FIGURE 1. Simplified I/O of the ADS7828.
ADS7828
SBAS181C
9
www.ti.com
must be taken into account. A master must signal an end of
data to the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master
to generate the STOP condition.
The following bus protocol has been defined (as shown in
Figure 2):
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH will be interpreted as control
signals.
Figure 2 details how data transfer is accomplished on the I2C
bus. Depending upon the state of the R/W bit, two types of
data transfer are possible:
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after the slave address
and each received byte.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain HIGH.
Start Data Transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
2. Data transfer from a slave transmitter to a master
receiver. The first byte, the slave address, is transmitted
by the master. The slave then returns an acknowledge bit.
Next, a number of data bytes are transmitted by the slave
to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end
of the last received byte, a not-acknowledge is returned.
Stop Data Transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data Valid: The state of the data line represents valid data,
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. There is one
clock pulse per bit of data.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next
serial transfer, the bus will not be released.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is not
limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.
The ADS7828 may operate in the following two modes:
• Slave Receiver Mode: Serial data and clock are received
through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware
after reception of the slave address and direction bit.
Within the I2C bus specifications a standard mode (100kHz
clock rate), a fast mode (400kHz clock rate), and a highspeed mode (3.4MHz clock rate) are defined. The ADS7828
works in all three modes.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
• Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode the direction bit will indicate
that the transfer direction is reversed. Serial data is transmitted on SDA by the ADS7828 while the serial clock is
input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Of course, setup and hold times
SDA
MSB
Slave Address
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
1
SCL
2
6
7
8
9
ACK
START
Condition
1
2
3-8
8
9
ACK
Repeated If More Bytes Are Transferred
STOP Condition
or Repeated
START Condition
FIGURE 2. Basic Operation of the ADS7828.
ADS7828
10
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SBAS181C
ADDRESS BYTE
COMMAND BYTE
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
1
0
0
1
0
A1
A0
R/W
SD
C2
C1
C0
PD1
PD0
X
X
The address byte is the first byte received following the
START condition from the master device. The first five bits
(MSBs) of the slave address are factory pre-set to 10010.
The next two bits of the address byte are the device select
bits, A1 and A0. Input pins (A1-A0) on the ADS7828 determine these two bits of the device address for a particular
ADS7828. A maximum of four devices with the same pre-set
code can therefore be connected on the same bus at one
time.
The ADS7828 operating mode is determined by a command
byte which is illustrated above.
The A1-A0 Address Inputs can be connected to VDD or digital
ground. The device address is set by the state of these pins
upon power-up of the ADS7828.
See Table I for a power-down selection summary.
SD: Single-Ended/Differential Inputs
0: Differential Inputs
1: Single-Ended Inputs
C2 - C0: Channel Selections
PD1 - 0: Power-Down Selection
X: Unused
See Table II for a channel selection control summary.
The last bit of the address byte (R/W) defines the operation
to be performed. When set to a ‘1’ a read operation is
selected; when set to a ‘0’ a write operation is selected.
Following the START condition the ADS7828 monitors the
SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device
select bits, and the R/W bit, the slave device outputs an
acknowledge signal on the SDA line.
PD1
PD0
0
0
Power Down Between A/D Converter Conversions
DESCRIPTION
0
1
Internal Reference OFF and A/D Converter ON
1
0
Internal Reference ON and A/D Converter OFF
1
1
Internal Reference ON and A/D Converter ON
TABLE I. Power-Down Selection
CHANNEL SELECTION CONTROL
SD
C2
C1
C0
CH0
CH1
0
0
0
0
+IN
–IN
0
0
0
1
—
—
0
0
1
0
—
—
0
0
1
1
—
0
1
0
0
–IN
CH2
CH3
CH4
CH5
CH6
CH7
COM
—
—
—
—
—
—
—
+IN
–IN
—
—
—
—
—
—
—
+IN
–IN
—
—
—
—
—
—
—
—
+IN
–IN
—
+IN
—
—
—
—
—
—
—
0
1
0
1
—
—
–IN
+IN
—
—
—
—
—
0
1
1
0
—
—
—
—
–IN
+IN
—
—
—
0
1
1
1
—
—
—
—
—
—
–IN
+IN
—
1
0
0
0
+IN
—
—
—
—
—
—
—
–IN
1
0
0
1
—
—
+IN
—
—
—
—
—
–IN
1
0
1
0
—
—
—
—
+IN
—
—
—
–IN
1
0
1
1
—
—
—
—
—
—
+IN
—
–IN
1
1
0
0
—
+IN
—
—
—
—
—
—
–IN
1
1
0
1
—
—
—
+IN
—
—
—
—
–IN
1
1
1
0
—
—
—
—
—
+IN
—
—
–IN
1
1
1
1
—
—
—
—
—
—
—
+IN
–IN
TABLE II. Channel Selection Control Addressed by Command Byte.
ADS7828
SBAS181C
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INITIATING CONVERSION
MSB
Provided the master has write-addressed it, the ADS7828
turns on the A/D converter’s section and begins conversions
when it receives BIT 4 of the command byte shown in the
Command Byte. If the command byte is correct, the ADS7828
will return an ACK condition.
6
5
4
3
2
1
LSB
BYTE 0
0
0
0
0
D11
D10
D9
D8
BYTE 1
D7
D6
D5
D4
D3
D2
D1
D0
READING IN F/S MODE
Figure 3 describes the interaction between the master and
the slave ADS7828 in Fast or Standard (F/S) mode. At the
end of reading conversion data the ADS7828 can be issued
a repeated START condition by the master to secure bus
operation for subsequent conversions of the A/D converter.
This would be the most efficient way to perform continuous
conversions.
READING DATA
Data can be read from the ADS7828 by read-addressing the
part (LSB of address byte set to 1) and receiving the
transmitted bytes. Converted data can only be read from the
ADS7828 once a conversion has been initiated as described
in the preceding section.
Each 12-bit data word is returned in two bytes, as shown
below, where D11 is the MSB of the data word, and D0 is the
LSB. Byte 0 is sent first, followed by Byte 1.
ADC Power-Down Mode
S
1
0
0
1
0
A1
A0
W
A
ADC Sampling Mode
SD C2
C1
0
0
1
0
A1
A
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
1
X
Command Byte
Write-Addressing Byte
Sr
C0 PD1 PD0 X
A0
R
A
0
0
0
0
D11 D10 D9
D8
A
D7 D6 . . .D1 D0
N
P
See Note (1)
Read-Addressing Byte
From Master to Slave
From Slave to Master
2 x (8 Bits + ack/not-ack)
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
W = '0' (WRITE)
R = '1' (READ)
NOTE: (1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.
FIGURE 3. Typical Read Sequence in F/S Mode.
ADS7828
12
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SBAS181C
READING IN HS MODE
See Figure 4 for a typical read sequence for HS mode.
Included in the read sequence is the shift from F/S to HS
modes. It may be desirable to remain in HS mode after
reading a conversion; to do this, issue a repeated START
instead of a STOP at the end of the read sequence, since a
STOP causes the part to return to F/S mode.
High Speed (HS) mode is fast enough that codes can be
read out one at a time. In HS mode, there is not enough time
for a single conversion to complete between the reception of
a repeated START condition and the read-addressing byte,
so the ADS7828 stretches the clock after the read-addressing byte has been fully received, holding it LOW until the
conversion is complete.
F/S Mode
S
0
0
0
0
1
X
X
X
N
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
Sr
1
0
0
1
0
A1
A0
W
A
ADC Sampling Mode
SD
C2 C1
Write-Addressing Byte
C0 PD1 PD0 X
X
A
Command Byte
HS Mode Enabled
ADC Converting Mode
Sr
1
0
0
1
0
A1
A0
R
A
SCLH(2) is stretched LOW waiting for data conversion
Read-Addressing Byte
HS Mode Enabled
Return to F/S Mode(1)
ADC Power-Down Mode
(depending on power-down selection bits)
0
0
0
0
D11 D10 D9
D8
A
D7
D6 . . .D1 D0
N
P
2 x (8 Bits + ack/not-ack)
From Master to Slave
From Slave to Master
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
W = '0' (WRITE)
R = '1' (READ)
NOTES: (1) To remain in HS mode, use repeated START instead of STOP.
(2) SCLH is SCL in HS mode.
FIGURE 4. Typical Read Sequence in HS Mode.
ADS7828
SBAS181C
13
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READING WITH REFERENCE ON/OFF
Internal VREF vs Turn-On Time Typical Characteristic plot.
If the PD1 bit has been set to logic ‘0’ while using the
ADS7828, then the settling time must be reconsidered
after PD1 is set to logic ‘1’. In other words, whenever the
internal reference is turned on after it has been turned off,
the settling time must be long enough to get 12-bit accuracy conversion.
The internal reference defaults to off when the ADS7828
power is on. To turn the internal reference on or off, see
Table I. If the reference (internal or external) is constantly
turned on and off, a proper amount of settling time must be
added before a normal conversion cycle can be started. The
exact amount of settling time needed varies depending on
the configuration.
3) When the internal reference is off, it is not turned on until
both the first Command Byte with PD1 = ‘1’ is sent and
then a STOP condition or repeated START condition is
issued. (The actual turn-on time occurs once the STOP or
repeated START condition is issued.) Any Command Byte
with PD1 = ‘1’ issued after the internal reference is turned
on serves only to keep the internal reference on. Otherwise, the internal reference would be turned off by any
Command Byte with PD1 = ‘0’.
See Figure 5 for an example of the proper internal reference
turn-on sequence before issuing the typical read sequences
required for the F/S mode when an internal reference is
used.
When using an internal reference, there are three things that
must be done:
1) In order to use the internal reference, the PD1 bit of
Command Byte must always be set to logic ‘1’ for each
sample conversion that is issued by the sequence, as
shown in Figure 3.
The example in Figure 5 can be generalized for a HS mode
conversion cycle by simply swapping the timing of the conversion cycle.
2) In order to achieve 12-bit accuracy conversion when
using the internal reference, the internal reference
settling time must be considered, as shown in the
If using an external reference, PD1 must be set to ‘0’, and the
external reference must be settled. The typical sequence in
Figure 3 or Figure 4 can then be used.
Internal Reference
Turn-On
Settling Time
Internal Reference Turn-On Sequence
S
1
0
0
1
0
A1
A0
W
A
X
X
Write-Addressing Byte
X
X
1
X
X
X
A
P
Wait until the required
settling time is reached
Command Byte
Typical Read
Sequence(1)
in F/S Mode
Settled Internal Reference
ADC Power-Down Mode
S
1
0
0
1
0
A1
A0
W
A
ADC Sampling Mode
SD C2
Write-Addressing Byte
C1
C0
1
PD0
X
X
A
Command Byte
Settled Internal Reference
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
Sr
1
0
0
1
0
A1
A0
R
A
0
0
0
0
Read-Addressing Byte
From Master to Slave
From Slave to Master
D11 D10 D9
D8
A
D7 D6 . . .D1 D0
2 x (8 Bits + ack/not-ack)
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
N
P
see
note
(2)
W = '0' (WRITE)
R = '1' (READ)
NOTES: (1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.
FIGURE 5. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S mode shown).
ADS7828
14
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SBAS181C
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7828 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
“n-bit” SAR converter, there are n “windows” in which large
external transient voltages can easily affect the conversion
result. Such glitches might originate from switching power
supplies, nearby digital logic, and high-power devices.
With this in mind, power to the ADS7828 should be clean and
well-bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VDD and the power supply is high.
The ADS7828 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital results.
While high-frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to
remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor. The ideal layout
will include an analog ground plane dedicated to the converter and associated analog circuitry.
ADS7828
SBAS181C
15
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7828E/250
ACTIVE
TSSOP
PW
16
250
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
ADS7828E/250G4
ACTIVE
TSSOP
PW
16
250
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
ADS7828E/2K5
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
ADS7828E/2K5G4
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
ADS7828EB/250
ACTIVE
TSSOP
PW
16
250
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
B
ADS7828EB/250G4
ACTIVE
TSSOP
PW
16
250
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
B
ADS7828EB/2K5
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
B
ADS7828EB/2K5G4
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 85
ADS
7828E
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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