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ADS8350, ADS7850, ADS7250
SBAS580D – MAY 2013 – REVISED MARCH 2018
ADSxx50 Dual, 750-kSPS, 16-, 14-, and 12-Bit, Simultaneous-Sampling,
Analog-to-Digital Converters
1 Features
3 Description
•
•
•
•
•
The ADS8350, ADS7850, and ADS7250 devices
belong to a family of pin-compatible, dual, highspeed,
simultaneous-sampling,
analog-to-digital
converters (ADCs) that support pseudo-differential
analog inputs. All devices support a simple serial
interface that can operate over a wide power-supply
range, enabling easy communication with a large
variety of host controllers.
1
•
•
•
•
16-, 14-, and 12-Bit Pin-Compatible Family
Simultaneously Samples Two Channels
Pseudo-Differential Analog Inputs
Fast Throughput: 750 kSPS
Excellent DC Performance:
– Linearity:
– ADS8350:
16-Bit NMC DNL, ±2.5 LSB, Max INL
– ADS7850:
14-Bit NMC DNL, ±1.5 LSB, Max INL
– ADS7250:
12-Bit NMC DNL, ±1 LSB, Max INL
Excellent AC Performance:
– ADS8350: 85-dB SNR, –96-dB THD
– ADS7850: 81-dB SNR, –90-dB THD
– ADS7250: 73-dB SNR, –88-dB THD
Simple Serial Interface
Fully-Specified Over Extended Industrial
Temperature Range: –40°C to 125°C
Small Footprint: WQFN-16 (3 mm × 3 mm)
All devices are fully specified over the extended
industrial temperature range (–40°C to 125°C) and
are available in a pin-compatible, WQFN-16 (3 mm ×
3 mm) package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS7250
ADS7850
WQFN (16)
3.00 mm × 3.00 mm
ADS8350
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
2 Applications
•
•
•
•
•
•
•
Motor Control:
Position Measurement Using SinCos Encoders
Optical Networking:
EDFA Gain Control Loop
Protection Relays
Power Quality Measurement
Three-Phase Power Controls
Programmable Logic Controllers
Industrial Automation
OPA322
+
-
AINP
+
+
ADS7250,
ADS7850,
ADS8350
OPA322
+
+V
+V
AINM
VREF
AINM
OPA322
+
-
OPA322
+
+
AINP
+V
-
+
+V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8350, ADS7850, ADS7250
SBAS580D – MAY 2013 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: All Devices....................... 5
Electrical Characteristics: ADS7250 ......................... 6
Electrical Characteristics: ADS7850 ......................... 7
Electrical Characteristics: ADS8350 ......................... 8
Timing Requirements ................................................ 9
Switching Characteristics ........................................ 9
Typical Characteristics: ADS7250 ........................ 10
Typical Characteristics: ADS7850 ........................ 13
Typical Characteristics: ADS8350 ........................ 16
Typical Characteristics: All Devices ...................... 19
Detailed Description ............................................ 20
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
21
24
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2014) to Revision D
Page
•
Changed ESD Ratings title, updated to current format, moved Storage temperature parameter to Absolute
Maximum Ratings table .......................................................................................................................................................... 4
•
Changed Timing Characteristics table: split table into Timing Requirements and Switching Characteristics ....................... 9
•
Deleted tSU_DOCK and tHT_CKDO parameters, replaced with tD_CKDO parameter ........................................................................ 9
•
Changed Timing Diagram figure............................................................................................................................................. 9
Changes from Revision B (April 2014) to Revision C
Page
•
Changed Device Information table to current standards ....................................................................................................... 1
•
Corrected pseudo-differential input and reference connections in the functional block diagram ........................................... 1
•
Changed Handling Ratings table to current standards ......................................................................................................... 4
Changes from Revision A (January 2014) to Revision B
Page
•
Changed format to meet latest data sheet standards; added Layout section, moved existing sections ............................... 1
•
Deleted Ordering Information section .................................................................................................................................... 3
Changes from Original (May 2013) to Revision A
•
2
Page
Released to production........................................................................................................................................................... 1
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Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: ADS8350 ADS7850 ADS7250
ADS8350, ADS7850, ADS7250
www.ti.com
SBAS580D – MAY 2013 – REVISED MARCH 2018
5 Pin Configuration and Functions
AINM-A
AINP-A
AVDD
GND
15
14
13
7
8
GND
REFIN-B
4
DVDD
REFGND-B
3
Thermal
Pad
6
2
AINP-B
REFGND-A
5
1
AINM-B
REFIN-A
16
RTE Package
16-Pin WQFN
Top View
12
SDO-B
11
SDO-A
10
SCLK
9
CS
Pin Functions
PIN
NAME
NO.
I/O
AINM-A
16
Analog input
Negative analog input, ADC_A
AINM-B
5
Analog input
Negative analog input, ADC_B
AINP-A
15
Analog input
Positive analog input, ADC_A
AINP-B
6
Analog input
Positive analog input, ADC_B
AVDD
14
Supply
CS
9
Digital input
DVDD
7
Supply
Digital I/O supply
8, 13
Supply
Device ground
REFGND-A
2
Supply
Reference ground potential, ADC_A
REFGND-B
3
Supply
Reference ground potential, ADC_B
REFIN-A
1
Analog input
Reference voltage input, ADC_A
REFIN-B
4
Analog input
Reference voltage input, ADC_B
SCLK
10
Digital input
Serial communication clock
SDO-A
11
Digital output
Data output for serial communication, ADC_A
SDO-B
12
Digital output
Data output for serial communication, ADC_B
GND
Thermal pad
DESCRIPTION
Supply
ADC supply voltage
Chip-select signal; active low
Exposed thermal pad. TI recommends connecting the thermal pad to the printed
circuit board (PCB) ground.
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SBAS580D – MAY 2013 – REVISED MARCH 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Analog input voltage
MIN
MAX
AVDD to GND
–0.3
7
UNIT
DVDD to GND
–0.3
7
AINP_x to REFGND_x
REFGND_x – 0.3
AVDD + 0.3
AINM_x to REFGND_x
REFGND_x – 0.3
AVDD + 0.3
REFIN_x to REFGND_x
REFGND_x – 0.3
AVDD + 0.3
GND – 0.3
DVDD + 0.3
V
V
V
Digital input voltage
CS, SCLK to GND
Ground voltage difference
| REFGND_x – GND |
0.3
V
Input current
Any pin except supply pins
±10
mA
150
°C
150
°C
Maximum virtual junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
AVDD
Analog power supply
DVDD
Digital power supply
NOM
MAX
UNIT
5
V
3.3
V
6.4 Thermal Information
ADS7250, ADS7850, ADS8350
THERMAL METRIC
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
33.3
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
29.5
°C/W
RθJB
Junction-to-board thermal resistance
7.3
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
0.9
°C/W
4
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SBAS580D – MAY 2013 – REVISED MARCH 2018
6.5 Electrical Characteristics: All Devices
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA =
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–VREF
VREF
V
0
2 × VREF
V
VREF + 0.1
V
ANALOG INPUT
FSR
Full-scale input range,
(AINP_x – AINM_x)
VINP
Absolute input voltage,
(AINP_x to REFGND)
VINM
Absolute input voltage,
(AINM_x to REFGND)
CIN
Input capacitance
IIN
Input leakage current
AVDD ≥ 2 x VREF (1),
AINM_x = VREF
AVDD ≥ 2 x VREF
AINM_x = VREF
(1)
,
VREF – 0.1
In sample mode
VREF
40
In hold mode
pF
4
1.5
nA
SAMPLING DYNAMICS
fDATA
Data rate
750
tA
Aperture delay
tA match
ADC_A to ADC_B
Aperture jitter
fCLK
kSPS
8
ns
40
ps
10
ps
Clock frequency
24
MHz
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage
IREF
Reference input current
2.25
2.5
300
Reference leakage current
CREF
AVDD / 2 (1)
µA
1
External ceramic reference
capacitance
V
10
µA
µF
DIGITAL INPUTS (2)
VIH
Input voltage, high
VIL
Input voltage, low
DIGITAL OUTPUTS
0.7 DVDD
DVDD + 0.3
V
–0.3
0.3 DVDD
V
0.8 DVDD
DVDD
V
0
0.2 DVDD
V
5.5
V
5.5
V
(2)
VOH
Output voltage, high
IOH = 500-µA source
VOL
Output voltage, low
IOH = 500-µA sink
POWER SUPPLY
AVDD
Analog supply voltage,
AVDD to GND
4.5 (1)
DVDD
Digital supply voltage,
DVDD to GND
1.65
IA-DYNA
Analog supply current,
during conversion
AVDD = 5 V, throughput = max
8
9
mA
IA-STAT
Analog supply current,
no conversion
AVDD = 5 V, static
5
7
mA
IDVDD
Digital supply current
DVDD = 3.3 V
PD-DYNA
PD-STAT
(1)
(2)
Power dissipation
5.0
0.25
mA
AVDD = 5 V, throughput = max
40
45
AVDD = 5 V, static
25
35
mW
The AVDD supply voltage defines the permissible voltage swing on the analog input pins. To use the maximum dynamic range of the
analog input pins, VREFIN_x and AVDD must be in the respective permissible range with AVDD ≥ 2 x VREFIN_x.
Specified by design; not production tested.
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Product Folder Links: ADS8350 ADS7850 ADS7250
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SBAS580D – MAY 2013 – REVISED MARCH 2018
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6.6 Electrical Characteristics: ADS7250
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA =
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
12
Bits
DC ACCURACY
INL
Integral nonlinearity
DNL
Differential nonlinearity
VOS
Input offset error
VOS match
ADC_A to ADC_B
–1
±0.5
1
LSB
–0.99
±0.4
1
LSB
–2
±0.75
2
mV
–2
±0.75
2
dVOS/dT
Input offset thermal drift
1
GERR
Gain error
Referenced to voltage at REFIN_x
–0.1%
±0.05%
0.1%
GERR match
ADC_A to ADC_B
–0.1%
±0.05%
0.1%
GERR/dT
Gain error thermal drift
Referenced to voltage at REFIN_x
CMRR
Common-mode rejection ratio Both ADCs, dc to 20 kHz
mV
µV/°C
1
ppm/°C
74
dB
AC ACCURACY
–0.5 dBFS at 20-kHz input
SINAD
Signal-to-noise + distortion
71.5
–0.5 dBFS at 100-kHz input
72.9
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
SNR
THD
SFDR
Signal-to-noise ratio
Total harmonic distortion
Spurious-free dynamic range
6
Full-power bandwidth
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dB
72.5
72
–0.5 dBFS at 100-kHz input
73
73
–0.5 dBFS at 250-kHz input
73
–0.5 dBFS at 20-kHz input
–90
–0.5 dBFS at 100-kHz input
–90
–0.5 dBFS at 250-kHz input
–82
–0.5 dBFS at 20-kHz input
90
–0.5 dBFS at 100-kHz input
90
–0.5 dBFS at 250-kHz input
82
Isolation between ADC_A and
fIN = 15 kHz, fNOISE = 25 kHz
ADC_B
BW(FP)
72.9
–85
At –3 dB
25
At –0.1 dB
5
dB
dB
dB
dB
MHz
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: ADS8350 ADS7850 ADS7250
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SBAS580D – MAY 2013 – REVISED MARCH 2018
6.7 Electrical Characteristics: ADS7850
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA =
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
14
Bits
DC ACCURACY
INL
Integral nonlinearity
DNL
Differential nonlinearity
VOS
Input offset error
VOS match
ADC_A to ADC_B
–1.5
±0.8
1.5
LSB
–0.99
±0.7
1
LSB
–1
±0.25
1
mV
–1
±0.25
1
dVOS/dT
Input offset thermal drift
1
GERR
Gain error
Referenced to voltage at REFIN_x
–0.1%
±0.05%
0.1%
GERR match
ADC_A to ADC_B
–0.1%
±0.05%
0.1%
GERR/dT
Gain error thermal drift
Referenced to voltage at REFIN_x
CMRR
Common-mode rejection ratio Both ADCs, dc to 20 kHz
mV
µV/°C
1
ppm/°C
74
dB
AC ACCURACY
–0.5 dBFS at 20-kHz input
SINAD
Signal-to-noise + distortion
79
–0.5 dBFS at 100-kHz input
81
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
SNR
THD
SFDR
Signal-to-noise ratio
Total harmonic distortion
Spurious-free dynamic range
Full-power bandwidth
dB
79.9
79.5
–0.5 dBFS at 100-kHz input
81.5
81.5
–0.5 dBFS at 250-kHz input
81
–0.5 dBFS at 20-kHz input
–90
–0.5 dBFS at 100-kHz input
–90
–0.5 dBFS at 250-kHz input
–86
–0.5 dBFS at 20-kHz input
90
–0.5 dBFS at 100-kHz input
90
–0.5 dBFS at 250-kHz input
86
Isolation between ADC_A and
fIN = 15 kHz, fNOISE = 25 kHz
ADC_B
BW(FP)
81
At –3 dB
At –0.1 dB
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–90
25
5
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dB
dB
dB
dB
MHz
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SBAS580D – MAY 2013 – REVISED MARCH 2018
www.ti.com
6.8 Electrical Characteristics: ADS8350
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA =
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
16
Bits
DC ACCURACY
INL
Integral nonlinearity
DNL
Differential nonlinearity
VOS
Input offset error
VOS match
ADC_A to ADC_B
–2.5
±1
2.5
LSB
–0.99
±0.7
2
LSB
–1
±0.25
1
mV
–1
±0.25
1
dVOS/dT
Input offset thermal drift
1
GERR
Gain error
Referenced to voltage at REFIN_x
–0.1%
±0.05%
0.1%
GERR match
ADC_A to ADC_B
–0.1%
±0.05%
0.1%
GERR/dT
Gain error thermal drift
Referenced to voltage at REFIN_x
CMRR
Common-mode rejection ratio Both ADCs, dc to 20 kHz
mV
µV/°C
1
ppm/°C
74
dB
AC ACCURACY
–0.5 dBFS at 20-kHz input
SINAD
Signal-to-noise + distortion
83.5
–0.5 dBFS at 100-kHz input
83.7
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
SNR
THD
SFDR
Signal-to-noise ratio
Total harmonic distortion
Spurious-free dynamic range
8
Full-power bandwidth
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dB
83
84
–0.5 dBFS at 100-kHz input
85
84.8
–0.5 dBFS at 250-kHz input
84
–0.5 dBFS at 20-kHz input
–96
–0.5 dBFS at 100-kHz input
–90
–0.5 dBFS at 250-kHz input
–90
–0.5 dBFS at 20-kHz input
96
–0.5 dBFS at 100-kHz input
90
–0.5 dBFS at 250-kHz input
90
Isolation between ADC_A and
fIN = 15 kHz, fNOISE = 25 kHz
ADC_B
BW(FP)
84.7
–90
At –3 dB
25
At –0.1 dB
5
dB
dB
dB
dB
MHz
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SBAS580D – MAY 2013 – REVISED MARCH 2018
6.9 Timing Requirements
MIN
NOM
MAX
UNIT
750
kSPS
24
MHz
fCLK = max
fTHROUGHPUT
Sample taken to data read
fCLK
CLOCK frequency
fTHROUGHPUT = max
tCLK
CLOCK period
fTHROUGHPUT = max
tPH_CK
CLOCK high time
0.4
0.6
tCLK
tPL_CK
CLOCK low time
0.4
0.6
tCLK
tACQ
Acquisition time
tPH_CS
fCLK = max
1.33
41.66
ADS8350, fCLK = max
120
ADS7850, fCLK = max
100
ADS7250, fCLK = max
70
CS high time
tPH_CS_SHRT
µs
ns
ns
20
CS high time after frame abort
ADS8350
120
ADS7850
100
ADS7250
70
ns
ns
tD_CKCS
Delay time from last SCLK falling to CS rising
15
ns
tSU_CSCK
Setup time from CS falling to SCLK falling
15
ns
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MAX
UNIT
590
ns
Delay time from CS falling to data enable
12
ns
tDZ_CSDO
Delay time from CS rising to DOUT going to
3-state
10
ns
tD_CKDO
Delay time from SCLK falling to (next) data
valid on SDO
20
ns
tCONV
Conversion time
tDV_CSDO
TEST CONDITIONS
MIN
TYP
3
Sample
N
Sample
N+1
tTHROUGHPUT
tCONV
tACQ
tPH_CS
CS
tSU_CSCK
SCLK
1
2
tPH_CK
13
14
15
16
17
tDV_CSDO
tSCLK
tPL_CK
22
23
24
25
26
27
28
30
D15
D14
D9
30
31
32
tDZ_CSDO
tD_CKDO
SDO-A
SDO-B
ADS8350
tD_CKCS
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data From Sample N
SDO-A
SDO-B
ADS7850
D13
D12
D7
D6
D5
D4
D3
D2
D1
D0
0
0
D1
D0
0
0
0
0
Data From Sample N
SDO-A
SDO-B
ADS7250
D11
D10
D5
D4
D3
D2
Data From Sample N
Figure 1. Timing Diagram
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6.11 Typical Characteristics: ADS7250
1
1
0.75
0.75
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
0.5
0.25
0
-0.25
-0.5
-0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-1
0
1024
2048
Code
3072
4096
0
1024
1
1
0.75
0.75
0.5
Maximum DNL
0
-0.25
Minimum DNL
-0.5
-0.75
C01
0.5
Maximum INL
0.25
0
-0.25
Minimum INL
-0.5
-1
-40
-7
26
59
Free-Air Temperature (oC)
92
125
-40
-7
C01
Figure 4. DNL vs Device Temperature
26
59
Free-Air Temperature (oC)
92
125
C01
Figure 5. INL vs Device Temperature
0
0
fIN = 2 kHz
-20
fIN = 250 kHz
-20
-40
-40
-60
-60
Signal Power (dB)
Signal Power (dB)
4096
-0.75
-1
-80
-100
-120
-140
-80
-100
-120
-140
-160
-160
-180
-180
-200
-200
0
75
150
225
300
Input Frequency (kHz)
Figure 6. Typical FFT at 2-kHz Input
10
3072
Figure 3. Typical INL
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Figure 2. Typical DNL
0.25
2048
Code
C01
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375
0
75
C00
150
225
Input Frequency (kHz)
300
375
C00
Figure 7. Typical FFT at 250-kHz Input
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Typical Characteristics: ADS7250 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
75
-80
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
74.5
74
73.5
73
72.5
72
71.5
71
-84
-88
-92
-96
-100
0
75
150
225
Input Frequency (kHz)
300
375
0
75
74
74.5
73.5
74
73.5
73
72.5
72
71.5
71
70
375
fIN = 2 kHz
-40
Signal-to-Noise and Distortion Ratio (dB)
Total Harmonic Distortion (dB)
fIN = 2 kHz
-89
-89.5
-90
-90.5
-91
-91.5
-92
-7
26
59
Free-Air Temperature (oC)
92
Figure 12. THD vs Device Temperature
26
59
Free-Air Temperature (oC)
92
125
C00
Figure 11. SNR vs Device Temperature
-88
-40
-7
C00
Figure 10. SINAD vs Input Frequency
-88.5
C00
72
71
300
375
73
70.5
150
225
Input Frequency (kHz)
300
72.5
71.5
75
150
225
Input Frequency (kHz)
Figure 9. THD vs Input Frequency
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distortion Ratio( dB)
Figure 8. SNR vs Input Frequency
0
75
C00
125
74
73.5
73
72.5
72
71.5
71
70.5
fIN = 2 kHz
70
-40
-7
C00
26
59
92
Free-Air Temperature (oC)
125
C00
Figure 13. SINAD vs Device Temperature
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Typical Characteristics: ADS7250 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
600
60
Gain Error (m%)
100
Offset Error (uV)
1000
200
-200
20
-20
-60
-600
-100
-1000
-40
-7
26
59
Free-Air Temperature (oC)
92
-40
125
-7
C01
Figure 14. Offset Error vs Device Temperature
26
59
Free-Air Temperature (oC)
92
125
C01
Figure 15. Gain Error vs Device Temperature
70000
60000
Number of Hits
50000
40000
30000
20000
10000
0
2045
2046
Code
2047
C01
Figure 16. DC Histogram
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6.12 Typical Characteristics: ADS7850
1
1
0.75
0.75
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
0.5
0.25
0
-0.25
-0.5
0.5
0.25
0
-0.25
-0.5
-0.75
-0.75
-1
-1
0
4096
8192
Code
12288
0
16384
4096
C01
2
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
12288
16384
C01
Figure 18. Typical INL
Figure 17. Typical DNL
1
Maximum DNL
0.5
0
8192
Code
Minimum DNL
-0.5
1
Maximum INL
0.5
0
-0.5
Minimum INL
-1
-1.5
-1
-40
-7
26
59
Free-Air Temperature (oC)
92
-2
125
-40
Figure 19. DNL vs Device Temperature
26
59
Free-Air Temperature (oC)
92
125
C01
Figure 20. INL vs Device Temperature
0
0
fIN = 2 kHz
-20
fIN = 250 kHz
-20
-40
-40
-60
Signal Power (dB)
Signal Power (dB)
-7
C01
-80
-100
-120
-140
-60
-80
-100
-120
-140
-160
-160
-180
-180
-200
-200
0
75
150
225
Input Frequency (kHz)
300
Figure 21. Typical FFT at 2-kHz Input
375
0
75
C00
150
225
Input Frequency (kHz)
300
375
C00
Figure 22. Typical FFT at 250-kHz Input
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Typical Characteristics: ADS7850 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
-80
84
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
83.5
83
82.5
82
81.5
81
80.5
-84
-88
-92
-96
-100
80
0
75
150
225
Input Frequency (kHz)
300
0
375
300
375
C00
84
fIN = 2 kHz
85
84
83
82
81
80
79
78
0
75
150
225
300
Input Frequency (kHz)
83
82
81
80
79
78
375
-40
Signal-to-Noise and Distortion Ratio (dB)
fIN = 2 kHz
-89
-90
-91
-92
-93
-94
-7
26
59
Free-Air Temperature (oC)
92
Figure 27. THD vs Device Temperature
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59
Free-Air Temperature (oC)
92
125
C00
Figure 26. SNR vs Device Temperature
-88
-40
-7
C00
Figure 25. SINAD vs Input Frequency
Total Harmonic Distortion (dB)
150
225
Input Frequency (kHz)
Figure 24. THD vs Input Frequency
86
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distortion Ratio (dB)
Figure 23. SNR vs Input Frequency
14
75
C00
125
84
fIN = 2 kHz
83
82
81
80
79
78
-40
-7
C00
26
59
Free-Air Temperature (oC)
92
125
C00
Figure 28. SINAD vs Device Temperature
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Typical Characteristics: ADS7850 (continued)
1000
100
750
75
500
50
Gain Error (m%)
Offset Error (µ)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
250
0
-250
25
0
-25
-500
-50
-750
-75
-100
-1000
-40
-7
26
59
Free-Air Temperature (oC)
92
-40
125
-7
C01
Figure 29. Offset Error vs Device Temperature
26
59
92
Free-Air Temperature (oC)
125
C01
Figure 30. Gain Error vs Device Temperature
60000
Number of Hits
50000
40000
30000
20000
10000
0
8181
8182
8183
Code
8184
8185
C01
Figure 31. DC Histogram
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6.13 Typical Characteristics: ADS8350
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
1
2
Differential Nonlinearity (LSB)
0.8
1.5
Integral Nonlinearity (LSB)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
1
0.5
0
-0.5
-1
-1.5
-0.8
-1
-2
0
16384
32768
49152
ADC Output Code (LSB)
65536
0
16384
Figure 32. Typical DNL
65536
C011
Figure 33. Typical INL
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
49152
2
2
Maximum DNL
1
0.5
0
Minimum DNL
-0.5
Maximum INL
1
0.5
0
-0.5
Minimum INL
-1
-1.5
-2
-1
±40
±7
26
59
92
Free-Air Temperature (ƒC)
±40
125
±7
26
59
92
Free-Air Temperature (ƒC)
C013
125
C015
Figure 35. INL vs Device Temperature
Figure 34. DNL vs Device Temperature
0
0
fIN = 2 kHz
fIN = 100 kHz
±20
±40
±50
±60
Power (dB)
Power (dB)
32768
ADC Output Code (LSB)
C010
±100
±80
±100
±120
±140
±150
±160
±180
±200
±200
0
75
150
225
fIN, Input Frequency (kHz)
300
Figure 36. Typical FFT at 2-kHz Input
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375
0
75
150
225
300
fIN, Input Frequency (kHz)
C001
375
C002
Figure 37. Typical FFT at 100-kHz Input
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Typical Characteristics: ADS8350 (continued)
86
±80
85.5
±82
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
85
84.5
84
83.5
83
82.5
±84
±86
±88
±90
±92
±94
±96
±98
82
±100
0
75
150
225
300
fIN, Input Frequency (kHz)
0
375
225
300
375
C005
Figure 39. THD vs Input Frequency
86
88
85.5
87.5
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distortion (dB)
150
fIN, Input Frequency (kHz)
Figure 38. SNR vs Input Frequency
85
84.5
84
83.5
83
82.5
fIN = 2 kHz
87
86.5
86
85.5
85
84.5
82
84
0
75
150
225
300
fIN, Input Frequency (kHz)
375
±40
±7
26
59
92
Free-Air Temperature (ƒC)
C004
Figure 40. SINAD vs Input Frequency
125
C018
Figure 41. SNR vs Device Temperature
88
±90
fIN = 2 kHz
±92
Signal-to-Noise and Distortion (dB)
Total Harmonic Distortion (dB)
75
C003
±94
±96
±98
±100
±102
±104
±106
fIN = 2 kHz
87.5
87
86.5
86
85.5
85
84.5
84
±40
±7
26
59
92
Free-Air Temperature (ƒC)
Figure 42. THD vs Device Temperature
125
±40
±7
26
59
92
Free-Air Temperature (ƒC)
C021
125
C019
Figure 43. SINAD vs Device Temperature
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Typical Characteristics: ADS8350 (continued)
1000
100
750
75
500
50
Gain Error (m%)
Offset Error (uV)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
250
0
-250
25
0
-25
-500
-50
-750
-75
-1000
-100
±40
±7
26
59
92
125
Free-Air Temperature (ƒC)
±40
26
±7
59
92
Free-Air Temperature (ƒC)
C008
Figure 44. Offset Error vs Device Temperature
125
C009
Figure 45. Gain Error vs Device Temperature
25000
Number of Code Hits
20000
15000
10000
Code
37490
37489
37488
37487
37486
37485
37484
37483
37482
37481
0
37480
5000
C007
Figure 46. DC Histogram
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6.14 Typical Characteristics: All Devices
8
8
7.8
7.5
AVDD Supply Current (mA)
IAVDD Dynamic Current (mA)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
7
6.5
6
5.5
5
4.5
4
3.5
6
3
±40
±7
26
59
Free-Air Temperature (ƒC)
92
125
0
6
Figure 47. Dynamic Current vs Device Temperature
12
18
SCLK Frequency (MHz)
C016
24
C017
Figure 48. Supply Current vs SCLK Frequency
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7 Detailed Description
7.1 Overview
The ADS8350, ADS7850, and ADS7250 belong to a family of dual, high-speed, simultaneous-sampling, analogto-digital converters (ADCs). The devices support pseudo-differential input signals with the input common-mode
equal to the reference voltage and the full-scale input range equal to twice the reference voltage. The devices
provide a simple serial interface to the host controller and operate over a wide range of digital power supplies.
7.2 Functional Block Diagram
Comparator
S/H
CDAC
SAR
ADC_A
Serial
Interface
ADC_B
SAR
S/H
CDAC
Comparator
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7.3 Feature Description
7.3.1 Reference
Each device has two simultaneous-sampling ADCs (ADC_A and ADC_B). ADC_A operates with reference
voltage VREFIN_A and ADC_B operates with reference voltage VREFIN_B. These reference voltages must be
provided on the REFIN_A and REFIN_B pins, respectively. REFIN_A and REFIN_B may be set to different
values as per the application requirement.
As shown in Figure 49, decouple the REFIN_A and REFIN_B pins with the REFGND_A and REFGND_B pins,
respectively, with individual 10-µF decoupling capacitors.
AINP_A
ADC_A
VREFIN_A
AINM_A
REFIN_A
10 PF
REFGND_A
Serial
Interface
AINP_B
ADC_B
VREFIN_B
AINM_B
REFIN_B
10 PF
REFGND_B
Figure 49. Reference Block Diagram
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Feature Description (continued)
7.3.2 Analog Input
The devices support pseudo-differential analog input signals. These inputs are sampled and converted
simultaneously by the two ADCs (ADC_A and ADC_B). ADC_A samples and converts (VAINP_A – VAINM_A), and
ADC_B samples and converts (VAINP_B – VAINM_B).
Figure 50a and Figure 50b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively.
RS (typically 50 Ω) represents the on-state sampling switch resistance, and CSAMPLE represents the device
sampling capacitor (typically 40 pF).
AVDD
AVDD
RS
CSAMPLE
AINP_A
RS
CSAMPLE
RS
CSAMPLE
AINP_B
GND
GND
AVDD
AVDD
RS
AINM_A
CSAMPLE
AINM_B
GND
GND
a) ADC_A
b) ADC_B
Figure 50. Equivalent Circuit for Analog Input Pins
7.3.2.1 Analog Input Full-Scale Range
The analog input full-scale range (FSR) for ADC_A and ADC_B is twice the reference voltage provided to the
particular ADC. By providing different reference voltages (VREFIN_A and VREFIN_B), ADC_A and ADC_B can have
different full-scale input ranges. Therefore, the FSR for ADC_A and ADC_B can be determined by Equation 1
and Equation 2, respectively:
FSR_ADC_A = 2 × VREFIN_A,
VAINP_A = 0 to 2 × VREFIN_A,
VAINM_A = VREFIN_A
(1)
The REFIN_A and AINM_A pins must be shorted and connected to the external reference voltage, VREFIN_A.
FSR_ADC_B = 2 × VREFIN_B,
VAINP_B = 0 to 2 × VREFIN_B,
VAINM_B = VREFIN_B
(2)
The REFIN_B and AINM_B pins must be shorted and connected to the external reference voltage, VREFIN_B.
To use the full dynamic input range on the analog input pins, AVDD must be as shown in Equation 3, Equation 4,
and Equation 5:
AVDD ≥ 2 × VREFIN_A
AVDD ≥ 2 × VREFIN_B
4.5 V ≤ AVDD ≤ 5.5 V
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(3)
(4)
(5)
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Feature Description (continued)
7.3.3 ADC Transfer Function
The device output is in binary twos complement format. Device resolution is calculated by Equation 6:
1 LSB = (FSR_ADC_x) / (2N)
where:
•
•
FSR_ADC_x = 2 x VREFIN_x and
N is the resolution of the ADC : N = 16 for the ADS8350, N = 14 for the ADS7850, and N = 12 for the
ADS7250
(6)
Table 1 shows the different input voltages and the corresponding device output codes.
Table 1. Transfer Characteristics
INPUT
VOLTAGE
(AINM_x)
VREFIN_x
INPUT VOLTAGE
(AINP_x)
PSEUDO-DIFFERENTIAL INPUT TO
ADC
(AINP_x - AINM_x)
OUTPUT CODE (HEX)
CODE
ADS7250
ADS7850
ADS8350
8000
0
–VREFIN_x
NFSR
NFSC
800
2000
1 LSB
– VREFIN_x + 1 LSB
NFSR + 1 LSB
NFSC + 1
801
2001
8001
VREFIN_x – 1 LSB
–1 LSB
–1 LSB
MC
FFF
3FFF
FFFF
VREFIN_x
0
0
PLC
000
0000
0000
2 × VREFIN_x – 1 LSB
VREFIN_x – 1 LSB
PFSR – 1 LSB
PFSC
7FF
1FFF
7FFF
Figure 51 shows the ideal transfer characteristics for the device.
ADC Code (Hex)
PFSC
PLC
MC
NFSC + 1
NFSC
VIN
NFSR
1 LSB
0
PFSR ± 1 LSB
Pseudo-Differential Analog Input
(AINP_x ± AINM_x)
Figure 51. Ideal Transfer Characteristics
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7.4 Device Functional Modes
7.4.1 Serial Interface
The devices support a simple, SPI-compatible serial interface to the external digital host. The CS signal defines
one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge.
The SDO_A and SDO_B pins output the ADC_A and ADC_B conversion results, respectively. Figure 52 shows a
detailed timing diagram for these devices.
Sample
N
Sample
N+1
tTHROUGHPUT
tCONV
tACQ
CS
SCLK
1
2
13
14
15
SDO-A
SDO-B
ADS8350
16
17
22
23
24
25
26
D15
D14
D9
D8
D7
D6
D5
D4
D3
D1
27
28
30
30
31
D3
D2
D1
D0
D2
D1
D0
0
0
D0
0
0
0
0
32
Data From Sample N
SDO-A
SDO-B
ADS7850
D13
D12
D7
D6
D5
D4
Data From Sample N
SDO-A
SDO-B
ADS7850
D11
D10
D5
D4
D3
D2
Data From Sample N
Figure 52. Serial Interface Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a '0' on the SDO_A and SDO_B pins.
The device converts the sampled analog input during the next 14 clocks. SDO_A and SDO_B read '0' during this
period. The sample-and-hold circuit goes back into sample mode on the 15th SCLK falling edge and the MSBs of
ADC_A and ADC_B are output on SDO_A and SDO_B, respectively. The subsequent clock edges are used to
shift out the conversion result using the serial interface, as shown in Table 2. Output data are in binary twos
complement format. A CS rising edge ends the frame and puts the serial bus into 3-state.
Table 2. Data Launch Edge
LAUNCH EDGE
SCLK
DEVICE
ADS8350
ADS7850
ADS7250
24
PIN
CS ↓
↓1
…
↓14
↓15
…
↓26
↓27
↓28
↓29
↓30
↓31
…
CS ↑
SDO-A
0
0
…
0
D15_A
…
D4_A
D3_A
D2_A
D1_A
D0_A
0
…
Hi-Z
SDO-B
0
0
…
0
D15_B
…
D4_B
D3_B
D2_B
D1_B
D0_B
0
…
Hi-Z
SDO-A
0
0
…
0
D13_A
…
D2_A
D1_A
D0_A
0
0
0
…
Hi-Z
SDO-B
0
0
…
0
D13_B
…
D2_B
D1_B
D0_B
0
0
0
…
Hi-Z
SDO-A
0
0
…
0
D11_A
…
D0_A
0
0
0
0
0
…
Hi-Z
SDO-B
0
0
…
0
D11_B
…
D0_B
0
0
0
0
0
…
Hi-Z
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7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature
Referring to Table 2, the ADS8350 requires a minimum of 31 SCLK falling edges between the beginning and end
of the frame to complete the 16-bit data transfer, the ADS7850 requires a minimum of 29 SCLK falling edges
between the beginning and end of the frame to complete the 14-bit data transfer, and the ADS7250 requires a
minimum of 27 SCLK falling edges between the beginning and end of the frame to complete the 12-bit data
transfer. However, CS can be brought high at any time during the frame to abort the frame or to short-cycle the
converter.
As shown in Figure 53, if CS is brought high before the 15th SCLK falling edge, the device aborts the conversion
and starts sampling the new analog input signal.
tPL_CS
tPH_CS_SHRT
CS
1
SCLK
2
tDZ_CSDO
SDO
Figure 53. Frame Aborted before 15th SCLK Falling Edge
If CS is brought high after the 15th SCLK falling edge (as shown in Figure 54), the output data bits latched into
the digital host before this CS rising edge are still valid data corresponding to sample N.
Sample
N
Sample
N+1
tCONV
tACQ
tPH_CS_SHRT
CS
SCLK
1
2
13
14
15
16
17
22
23
24
tDZ_CSDO
SDO-A
SDO-B
ADS8350
D15
D14
SDO-A
SDO-B
ADS7850
D13
D12
SDO-A
SDO-B
ADS7250
D11
D10
D9
D8
D7
Data From Sample N
D7
D6
D5
Data From Sample N
D5
D4
D3
Data From Sample N
Figure 54. Frame Aborted after 15th SCLK Falling Edge
After aborting the current frame, CS must be kept high for tPH_CS_SHRT to ensure that the minimum acquisition
time (tACQ) is provided for the next conversion.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits and provides some application circuits
designed using these devices.
8.2 Typical Applications
8.2.1 DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
5 V+
10 µF
X5R
REFGND-A
1k
0.1
+
REF5025
1 µF
ADC_A
REFIN-A
-
VOUT
ADS8350
5 V+
TRIM
0.22
1k
1 µF
X5R
+
10 µF
X5R
REFIN-B
1 µF
-
ADC_B
0.1
REFGND-B
OPA2350
10 µF
X5R
Figure 55. Reference Drive Circuit with VREF = 2.5 V
26
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Typical Applications (continued)
AVDD
VCM = VREF/2
AVDD
OPA836
+
10
+
1k
AVDD
+
-
AINP
VIN+
3.9 nF
ADS8350
1k
AINM
GND
10
VREF = 2.5 V
ADS8350 : 16-bit, 750kSPS, Pseudo Differential
Input
INPUT DRIVER
Figure 56. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
8.2.1.1 Design Requirements
For the ADS8350, design an input driver and reference driver circuit to achieve > 84-dB SNR and < –90-dB THD
at a 100-kHz input frequency.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 ADC Reference Driver
The external reference source to the device must provide low-drift and very accurate voltage for the ADC
reference input and support the dynamic charge requirements without affecting the noise and linearity
performance of the device. The output broadband noise of most references can be in the order of a few
100 µVRMS. Therefore, in order to prevent any degradation in the noise performance of the ADC, the output of
the voltage reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few
hundred Hertz.
After band-limiting the noise from the reference source, the next important step is to design a reference buffer
that can drive the dynamic load posed by the reference input of the ADC. At the start of each conversion, the
reference buffer must regulate the voltage of the reference pin within 1 LSB of the intended value. This condition
necessitates the use of a large filter capacitor at the reference pin of the ADC. The amplifier selected to drive this
large capacitor should have low output impedance, low offset, and temperature drift specifications.
To reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is
recommended for driving the reference input of each ADC channel.
The application circuit in Figure 55 shows the schematic of a complete reference driver circuit that generates a
voltage of 2.5-V dc using a single 5-V supply.
The 2.5-V reference voltage is generated by the high-precision, low-noise REF5025 circuit. The output
broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.
The decoupling capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise,
and fast settling time makes the OPA2350 a good choice for driving this high capacitive load.
8.2.1.2.2 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of a high-precision ADC.
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Typical Applications (continued)
8.2.1.2.2.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to
maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as
described in Equation 7:
§
1
Unity Gain Bandwidth t 4 u ¨¨
© 2S u ( RFLT RFLT ) u C FLT
•
·
¸¸
¹
(7)
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter, as explained in Equation 8.
§ V 1 _ AM P_ PP ·
¨
¸
NG u 2 u ¨ f
¸¸
6.6
¨
©
¹
2
en2 _ RM S u
S
uf
2
3 dB
d
1 VREF
u
u 10
5
2
§ SNR dB ·
¨
¸
20
©
¹
where:
•
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µVRMS,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to '1' in a buffer configuration.
THD AMP d THD ADC
•
28
(8)
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 9.
10 dB
(9)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™SPICE simulations before selecting the amplifier.
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Typical Applications (continued)
8.2.1.2.2.2 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the ADC inputs during the small acquisition time window. For ac signals, the filter
bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-tonoise ratio (SNR) of the system.
Besides filtering noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge
injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the
ADC inputs (as shown in Figure 57).
RFLT ” 22
f
3 dB
2S u R FLT
1
R FLT u C FLT
V
+
AINP
CFLT • 400 pF
ADS8350
AINM
GND
RFLT ” 22
Figure 57. Antialiasing Filter
This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the
internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor
should be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input
sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than 400 pF. The capacitor
should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and
stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin
with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a
larger differential capacitor is advisable.
The application circuit shown in Figure 56 is optimized to achieve lowest distortion and lowest noise for a 10-kHz
input signal. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting gain
configuration and a low-pass RC filter before being fed into the ADS8350 operating at 750-kSPS throughput.
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Typical Applications (continued)
As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. The low-power OPA836, used as
an input driver, provides exceptional ac performance because of its extremely low-distortion, high-bandwidth
specifications. In addition, the components of the antialiasing filter are such that the noise from the front-end
circuit is kept low without adding distortion to the input signal.
NOTE
The same circuit can be used with the ADS7250 and ADS7850 to achieve their rated
specifications.
8.2.1.3 Application Curve
Figure 58 shows FFT plot and test results obtained with circuit configuration shown in Figure 56.
0
AVDD = 5 V
REF = 2.5 V
TA = 25oC
fIN = 10 kHz
SNR = 85.5 dB
THD = -94 dB
-20
Power (dB)
-40
-60
-80
-100
-120
-140
-160
0
75
150
225
300
Input Frequency (kHz)
375
C10
Figure 58. FFT Plot and Test Results with ADS8350
30
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Typical Applications (continued)
8.2.2 DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
5 V+
10 µF
X5R
REFGND-A
1k
0.1
+
REF5025
1 µF
ADC_A
REFIN-A
-
VOUT
ADS8350
5 V+
TRIM
0.22
1k
+
1 µF
X5R
REFIN-B
10 µF
X5R
1 µF
-
ADC_B
0.1
REFGND-B
OPA2350
10 µF
X5R
Figure 59. Reference Drive Circuit with VREF = 2.5 V
+15 V
VREF/2
AVDD
THS4032
+
4.7
602
AVDD
+
-
VIN+
V
+
AINP
1 nF
-15 V
602
ADS8350
AINM
GND
10 pF
4.7
+15 V
VREF
+
ADS8350 : 16-bit, 750kSPS, Pseudo
Differential Input
-15 V
INPUT DRIVER
THS4032
Figure 60. DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
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Typical Applications (continued)
8.2.2.1 Design Requirements
For the ADS8350, design an input driver and reference driver circuit to achieve > 84-dB SNR and < –90-dB THD
at a 100-kHz input frequency.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 ADC Reference Driver
Refer to the ADC Reference Driver section for a detailed design procedure for the ADC reference driver.
The application circuit in Figure 55 shows the schematic of a complete reference driver circuit that generates a
voltage of 2.5-V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8350 at
sampling rates up to 750 kSPS.
The 2.5-V reference voltage is generated by the high-precision, low-noise REF5025 circuit. The output
broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.
The decoupling capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise,
and fast settling time makes the OPA2350 a good choice for driving this high capacitive load.
8.2.2.2.2 ADC Input Driver
Refer to ADC Input Driver section for the detailed design procedure for an ADC input driver.
The application circuit shown in Figure 60 is optimized to achieve lowest distortion and lowest noise for a 100kHz input signal. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting
gain configuration and a low-pass RC filter before being fed into the ADS8350 operating at 750-kSPS
throughput.
As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of a rail-to-rail swing at the input of the amplifier. The THS4032, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion, low-noise, and high-bandwidth
specifications. The ADC AINM pin is also driven to VREF with the same amplifier to match the source impedance
and to take full advantage of the pseudo-differential input structure of the ADC. In addition, the components of
the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the
input signal.
NOTE
The same circuit can be used with the ADS7250 and ADS7850 to achieve their rated
specifications.
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Typical Applications (continued)
8.2.2.3 Application Curve
Figure 61 shows FFT plot and test results obtained with circuit configuration shown in Figure 60.
0
AVDD = 5 V
REF = 2.5 V
TA = 25oC
fIN = 100 kHz
SNR = 85 dB
THD = -91 dB
-20
Power (dB)
-40
-60
-80
-100
-120
-140
-160
0
75
150
225
300
Input Frequency (kHz)
375
C10
Figure 61. FFT Plot and Test Results with ADS8350
9 Power Supply Recommendations
The devices have two separate power supplies: AVDD and DVDD. The ADC operates on AVDD; DVDD is used
for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible range.
The AVDD supply voltage value defines the permissible voltage swing on the analog input pins. To avoid
saturation of output codes, the external reference voltages VREFIN_A and VREFIN_B should be as shown in
Equation 10:
2 V ≤ VREFIN_x ≤ AVDD / 2
(10)
In other words, in order to use the VREFIN_x external reference voltage and use the full dynamic range on the
analog input pins, AVDD must be set as shown in Equation 11, Equation 12, and Equation 13:
AVDD ≥ 2 × VREFIN_A
AVDD ≥ 2 × VREFIN_B
4.5 V ≤ AVDD ≤ 5.5 V
(11)
(12)
(13)
Decouple the AVDD and DVDD pins with the GND pin using individual 10-µF decoupling capacitors, as shown in
Figure 62.
AVDD
AVDD (pin 14)
10 PF
GND (pin 13)
10 PF
DVDD
DVDD (pin 7)
Figure 62. Power-Supply Decoupling
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10 Layout
10.1 Layout Guidelines
Figure 63 shows a board layout example for the ADS7250, ADS7850, and ADS8350. Use a ground plane
underneath the device and partition the PCB into analog and digital sections. Avoid crossing digital lines with the
analog signal path and keep the analog input signals and the reference input signals away from noise sources.
As shown in Figure 63, the analog input and reference signals are routed on the left side of the board and the
digital connections are routed on the right side of the device.
The power sources to the ADS8350 must be clean and well-bypassed. Use 10-µF ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, lowimpedance paths.
The REFIN-A and REFIN-B reference inputs are bypassed with 10-µF, X7R-grade ceramic capacitors (CREF-x).
Although the reference inputs of the device draw little current on average, there are instantaneous dynamic
current demands placed on the reference circuitry characteristic of SAR ADCs. Place the reference bypass
capacitors as close as possible to the reference REFIN-x pins and connect the bypass capacitors using short,
low-inductance connections. Avoid placing vias between the REFIN-x pins and the bypass capacitors. If the
reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without
oscillation. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series with the reference bypass capacitors to
improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Figure 63 shows the CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.
10.2 Layout Example
CREF-A
AVDD
CIN-A
GND
GND
AVDD
AINP-A
AINM-A
RREF-A
CAVDD
GND
SDO-A
REFIN-A
CIN-B
/CS
GND
AINM-B
RREF-B
CREF-B
SCLK
GND
REFIN-B
GND
SDO-B
REFGND-B
DVDD
GND
REFGND-A
AINP-B
GND
CDVDD
DVDD
GND
GND
Figure 63. Layout Example
34
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference
• OPAx350 High-Speed, Single-Supply, Rail-to-Rail Operational Amplifiers MicroAmplifier Series
• OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative Rail In, Voltage-Feedback Operational Amplifiers
• THS403x 100-MHz Low-Noise High-Speed Amplifiers
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADS8350
Click here
Click here
Click here
Click here
Click here
ADS7850
Click here
Click here
Click here
Click here
Click here
ADS7250
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
TINA, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7250IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7250
ADS7250IRTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7250
ADS7850IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7850
ADS7850IRTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7850
ADS8350IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8350
ADS8350IRTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8350
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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