ADS5403
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SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
Single Channel 12-Bit 500Msps Analog to Digital Converter
Check for Samples: ADS5403
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The ADS5403 is a high linearity single channel 12-bit,
500 MSPS analog-to-digital converter (ADC) easing
front end filter design for wide bandwidth receivers.
The analog input buffer isolates the internal switching
of the on-chip track-and-hold from disturbing the
signal source as well as providing a high-impedance
input. Optionally the output data can be decimated by
two. Designed for high SFDR, the ADC has low-noise
performance and outstanding spurious-free dynamic
range over a large input-frequency range. The device
is available in a 196pin BGA package and is specified
over the full industrial temperature range (–40°C to
85°C).
1
•
Single Channel
12-Bit Resolution
Maximum Clock Rate: 500 Msps
Low Swing Fullscale Input: 1.0 Vpp
Analog Input Buffer with High Impedance Input
Input Bandwidth (3dB): >1.2GHz
Data Output Interface: DDR LVDS
196-Pin BGA Package (12x12mm)
Power Dissipation: 1 W
Spectral Performance at fIN = 230 MHz IF
– SNR: 60.6 dBFS
– SFDR: 80 dBc
Spectral Performance at fIN = 700 MHz IF
– SNR: 59.5 dBFS
– SFDR: 72 dBc
APPLICATIONS
•
•
•
•
•
•
•
Test and Measurement Instrumentation
Ultra-Wide Band Software Defined Radio
Data Acquisition
Power Amplifier Linearization
Signal Intelligence and Jamming
Radar and Satellite Systems
Microwave Receivers
12bit
500Msps
INA
Digital
Block
DA[11 :0]
DACLK
CLKIN
Clk
Buffer
SYNC
Device Part No.
Number of
Channels
Speed Grade
ADS5402
2
800Msps
ADS5401
1
800Msps
ADS5404
2
500Msps
ADS5403
1
500Msps
ADS5407
2
500Msps
ADS5409
2
900Msps
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013–2014, Texas Instruments Incorporated
ADS5403
SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
OVRAP/N
SRESETB
DETAILED BLOCK DIAGRAM
SCLK
OVERRANGE
SDENB
INTERLEAVING
CORRECTION
ADC
CLKOUT
GEN
DC or
Fs/2
Estimator
Gain Correction
DEC
x2
FIR FILTER
Offset Correction
CLKP /N
SYNCP/N
SDO
VOLTAGE
REFERENCE
BUFFER
INA_P/N
SDIO
CONTROL
CLOCK
DISTRIBUTION
SYNCOUTP /M
MULTICHIP
SYNC
DACLKP /N
...
VCM
THRESHOLD
DDR LVDS
OUTPUT BUFFER
VREF
PROGRAMMING
DATA
DA[11:0]P/N
SYNCOUTP /N
Figure 1. Detailed Block Diagram
2
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SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
PINOUT INFORMATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
VREF
VCM
GND
NC
NC
GND
AVDDC
AVDDC
GND
INA_P
INA_N
GND
GND
CLKINP
14
13
SDENB
TEST
MODE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLKINN
13
12
SCLK
SRESET
B
GND
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33
GND
AVDD33
AVDD33
12
11
SDIO
ENABLE
GND
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
AVDD18
GND
AVDD18
AVDD18
11
10
SDO
IOVDD
GND
AVDD18
GND
GND
GND
GND
GND
GND
AVDD18
GND
NC
NC
10
9
DVDD
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SYNCN
SYNCP
9
8
DVDD
DVDD
DVDD
DVDD
GND
GND
GND
GND
GND
GND
DVDD
DVDD
DVDD
DVDD
8
7
NC
NC
DVDD
LVDS
DVDD
LVDS
GND
GND
GND
GND
GND
GND
DVDD
LVDS
DVDD
LVDS
NC
NC
7
6
NC
NC
DVDD
LVDS
DVDD
LVDS
GND
GND
GND
GND
GND
GND
DVDD
LVDS
DVDD
LVDS
NC
NC
6
5
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
OVRAN
OVRAP
SYNC
OUTN
SYNC
OUTP
5
4
NC
NC
NC
NC
NC
NC
NC
DA0P
DA2P
DA4P
DA6P
DA8P
NC
NC
4
3
NC
NC
NC
NC
NC
NC
NC
DA0N
DA2N
DA4N
DA6N
DA8N
DA11N
DA11P
3
2
NC
NC
NC
NC
NC
NC
NC
DACLKP
DA1P
DA3P
DA5P
DA7P
DA10N
DA10P
2
1
NC
NC
NC
NC
NC
NC
NC
DACLKN
DA1N
DA3N
DA5N
DA7N
DA9N
DA9P
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 2. Pinout in DDR output mode (top down view)
PIN ASSIGNMENTS
PIN
NAME
NUMBER
I/O
DESCRIPTION
INPUT/REFERENCE
INA_P/N
K14, L14
I
Analog ADC A differential input signal.
VCM
B14
O
Output of the analog input common mode (nominally 1.9V). A 0.1μF capacitor to AGND is
recommended.
VREF
A14
O
Reference voltage output. A 0.1μF capacitor to AGND is recommended, but not required.
CLKINP/N
P14, P13
I
Differential input clock
SYNCP/N
P9, N9
I
Synchronization input. Inactive if logic low. When clocked in a high state initially, this is used
for resetting internal clocks and digital logic and starting the SYNCOUT signal. Internal 100Ω
termination.
SRESET
B12
I
Serial interface reset input. Active low. Initialized internal registers during high to low
transition. Asynchronous. Internal 50kΩ pull up resistor to IOVDD.
ENABLE
B11
I
Chip enable – active high. Power down function can be controlled through SPI register
assignment. Internal 50kΩ pull up resistor to IOVDD.
SCLK
A12
I
Serial interface clock. Internal 50kΩ pull-down resistor.
CLOCK/SYNC
CONTROL/SERIAL
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PIN ASSIGNMENTS (continued)
PIN
I/O
DESCRIPTION
NAME
NUMBER
SDIO
A11
I/O
SDENB
A13
I
Serial interface enable. Internal 50kΩ pull-down resistor.
SDO
A10
O
Uni-directional serial interface data in 4 pin mode (register x00, D16). The SDO pin is tristated in 3-pin interface mode (default). Internal 50kΩ pull-down resistor.
TESTMODE
B13
–
Factory internal test, do not connect
DA[11:0]P/N
P3, N3, P2, N2,
P1, N1, M4, M3,
M2, M1, L4, L3,
L2, L1, K4, K3,
K2, K1, J4, J3,
J2, J1, H4, H3
O
ADC A Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.
DACLKP/N
H2, H1
O
DDR differential output data clock for Bus A. Register programmable to provide either rising
or falling edge to center of stable data nominal timing.
F2, F1, P5, N5
O
Synchronization output signal for synchronizing multiple ADCs. Can be disabled via SPI.
M5, L5
O
Bus A, Overrange indicator, LVDS output. A logic high signals an analog input in excess of
the full-scale range. Optional SYNC output.
A1, A2, A3, A4,
A5, A6, A7, B1,
B2, B3, B4, B5,
B6, B7, C1, C2,
C3, C4, C5, D1,
D2, D3, D4, D5,
D14, E1, E2, E3,
E4, E14, F3, F4,
G1, G2, G3, G4,
N4, N6, N7, N10,
P4, P6, P7, P10
-
Don’t connect to pin
D12, E12, F12,
G12, H12, J12,
K12, L12, N12,
P12
I
3.3V analog supply
AVDDC
G14, H14
I
1.8V supply for clock input
AVDD18
D10, D11, E11,
F11, G11, H11,
J11, K11, L10,
L11, N11, P11
I
1.8V analog supply
DVDD
A8, A9, B8, B9,
C8, D8, L8, M8,
N8, P8
I
1.8V supply for digital block
DVDDLVDS
C6, C7, D6, D7,
L6, L7, M6, M7
I
1.8V supply for LVDS outputs
B10
I
1.8V for digital I/Os
I
Ground
Bi-directional serial data is 3 pin mode (default). In 4-pin interface mode (register x00, D16),
the SDIO pin in an input only. Internal 50kΩ pull-down.
DATA INTERFACE
SYNCOUTP/N
OVRAP/N
NC
POWER SUPPLY
AVDD33
IOVDD
GND
4
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SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
ECO
PLAN(2)
ADS5403
196-BGA
ZAY
–40C to 85C
GREEN
(RoHS & no
Sb/Br)
LEAD/
BALL
FINISH
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS5403IZAY
Tray
ADS5403IZAYR
Tape and Reel
PACKAGE
MARKING
ADS5403I
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
MAX
UNIT
Supply voltage range, AVDD33
–0.5
4
V
Supply voltage range, AVDDC
–0.5
2.3
V
Supply voltage range, AVDD18
–0.5
2.3
V
Supply voltage range, DVDD
–0.5
2.3
V
Supply voltage range, DVDDLVDS
–0.5
2.3
V
Supply voltage range, IOVDD
–0.5
4
V
INA/B_P, INA/B_N
–0.5
AVDD33 + 0.5
V
CLKINP, CLKINN
–0.5
AVDDC + 0.5
V
SYNCP, SYNCN
–0.5
AVDD33 + 0.5
V
SRESET, SDENB, SCLK, SDIO, SDO, ENABLE
–0.5
IOVDD + 0.5
V
Voltage applied to input pins
Operating free-air temperature range, TA
–40
Operating junction temperature range, TJ
Storage temperature range
–65
ESD, Human Body Model
85
°C
150
°C
150
°C
2
kV
THERMAL INFORMATION
ADS5403
THERMAL METRIC
(1)
nFBGA
UNITS
196 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
37.6
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
16.8
ψJT
Junction-to-top characterization parameter (5)
0.2
ψJB
Junction-to-board characterization parameter (6)
16.4
(1)
(2)
(3)
(4)
(5)
(6)
6.8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Recommended operating junction temperature
TJ
TA
(1)
NOM
MAX
105
Maximum rated operating junction temperature (1)
125
Recommended free-air temperature
–40
25
85
UNIT
°C
°C
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNITS
ADC Clock Frequency
40
500
MSPS
Resolution
12
Bits
SUPPLY
AVDD33
3.15
3.3
3.45
V
AVDDC, AVDD18, DVDD, DVDDLVDS
1.7
1.8
1.9
V
IOVDD
1.7
1.8
3.45
V
POWER SUPPLY
IAVDD33
3.3V Analog supply current
150
170
mA
IAVDD18
1.8V Analog supply current
55
65
mA
IAVDDC
1.8V Clock supply current
27
35
mA
IDVDD
1.8V Digital supply current
Auto Correction Disabled
87
140
mA
IDVDD
1.8V Digital supply current
Auto Correction Enabled
147
170
mA
IDVDD
1.8V Digital supply current
Auto Correction Enabled, decimation filter enabled
164
IDVDDLVDS
1.8V LVDS supply current
IIOVDD
1.8V I/O Voltage supply current
Pdis
Total power dissipation
PSRR
Auto Correction Enabled, decimation filter disabled
250kHz to 500MHz
Shut-down power dissipation
Standby power dissipation
Standby wake up time
Deep-sleep mode power dissipation
mA
2
mA
1.04
1.2
W
40
dB
mW
2.5
ms
7
mW
100
µs
220
mW
Auto correction enabled
305
mW
20
µs
Auto correction disabled
367
mW
Auto correction enabled
448
mW
Light-sleep mode wakeup time
6
90
1
Auto correction disabled
Deep-sleep mode wakeup time
Light-sleep mode power dissipation
73
7
Shut-down wake up time
mA
2
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD3V = 3.3V, AVDD/DRVDD/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNITS
ANALOG INPUTS
Differential input full-scale
Input common mode voltage
1
1.25
1.9
±0.1
Vpp
V
Input resistance
Differential at DC
1
kΩ
Input capacitance
Each input to GND
2
pF
VCM common mode voltage output
1.9
Analog input bandwidth (3dB)
V
1200
MHz
DYNAMIC ACCURACY
Offset Error
Auto Correction Disabled
-20
-7.5
20
Auto Correction Enabled
-1
0
1
Offset temperature coefficient
-611
Gain error
-5
Gain temperature coefficient
mV
mV
µV/°C
5
0.005
%FS
%FS/°C
Differential nonlinearity
fIN = 230 MHz
-1
±0.9
2
LSB
Integral nonlinearity
fIN = 230 MHz
-5
±1.5
5
LSB
500
MHz
CLOCK INPUT
Input clock frequency
40
Input clock amplitude
2
Input clock duty cycle
40
Internal clock biasing
50
Vpp
60
0.9
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
Auto Correction
TYP MAX
Enabled
MIN
TYP MAX
Disabled
UNITS
Vpp
DYNAMIC AC CHARACTERISTICS (1) – Burst Mode Enabled: 12bit High Resolution Output Data
SNR
HD2,3
Non
HD2,3
IL
Signal to Noise Ratio
Second and third harmonic
distortion
Spur Free Dynamic Range
(excluding second and third
harmonic distortion)
Fs/2-Fin interleaving spur
SINAD
THD
IMD3
Signal to noise and distortion
ratio
Total Harmonic Distortion
Inter modulation distortion
fIN = 10 MHz
60.8
60.8
fIN = 100 MHz
60.7
60.8
60.6
60.7
fIN = 450 MHz
60.2
60.6
fIN = 700 MHz
59.5
60.1
fIN = 10 MHz
83
84
fIN = 100 MHz
85
83
fIN = 230 MHz
fIN = 230 MHz
59
82
82
fIN = 450 MHz
81
82
fIN = 700 MHz
76
74
fIN = 10 MHz
79
81
fIN = 100 MHz
78
82
80
81
fIN = 450 MHz
75
82
fIN = 700 MHz
72
80
fIN = 10 MHz
87
81
fIN = 100 MHz
81
79
fIN = 230 MHz
fIN = 230 MHz
70
70
84
80
fIN = 450 MHz
80
77
fIN = 700 MHz
74
73
fIN = 10 MHz
60.6
60.7
fIN = 100 MHz
60.6
60.7
60.6
60.7
fIN = 450 MHz
60.1
60.5
fIN = 700 MHz
59.3
59.9
fIN = 10 MHz
76
78
fIN = 100 MHz
78
78
fIN = 230 MHz
fIN = 230 MHz
70
57.5
68
(1)
8
Effective number of bits
dBc
dBc
dBc
dBFS
79
77
fIN = 450 MHz
76
77
fIN = 700 MHz
74
73
Fin = 129.5 and 130.5MHz, 7dBFS
82
82
Fin = 349.5 and 350.5MHz, 7dBFS
80
80
90
90
dB
fIN = 230 MHz
9.8
9.8
Bit
Crosstalk
ENOB
dBFS
dBc
dBFS
SFDR and SNR calculations do not include the DC or Fs/2 bins when Auto Correction is disabled.
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OVER-DRIVE RECOVERY ERROR
Input overload recovery
Recovery to within 5% (of final value) for 6dB
overload with sine wave input
2
ns
SAMPLE TIMING CHARACTERISTICS
rms
Aperture Jitter
Sample uncertainty
100
fs rms
ADC sample to digital output, auto correction disabled
38
ADC sample to digital output, auto correction enabled
50
Clock
Cycles
ADC sample to digital output, Decimation filter
enabled, Auto correction disabled
74
Sampling
clock
Cycles
ADC sample to over-range output
12
Clock
Cycles
Data Latency
Over-range Latency
ELECTRICAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE
High-level input voltage
Low-level input voltage
All digital inputs support 1.8V and 3.3V logic
levels.
0.7 x
IOVDD
V
0.3 x
IOVDD
V
High-level input current
–50
200
µA
Low-level input current
–50
50
µA
Input capacitance
5
pF
DIGITAL OUTPUTS – SDO
Iload = -100uA
High-level output voltage
Iload = -2mA
IOVDD –
0.2
V
0.8 x
IOVDD
Iload = 100uA
Low-level output voltage
0.2
0.22 x
IOVDD
Iload = 2mA
V
DIGITAL INPUTS – SYNCP/N, TRIGGERP/N
VID
Differential input voltage
VCM
Input common mode voltage
tSU
250
350
450
1.125
1.2
1.375
500
mV
V
ps
DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N, DB[11:0]P/N, DBCLKP/N, OVRBP/N
VOD
Output differential voltage
Iout = 3.5mA
250
350
450
VOCM
Output common mode voltage
Iout = 3.5mA
1.125
1.25
1.375
tsuA
Fs = 500Msps, Data valid to zero-crossing of
DACLK
600
800
ps
thA
Fs = 500Msps, Zero-crossing of DACLK to
data becoming invalid
600
790
ps
tPD
Fs = 500Msps, CLKIN falling edge to
DACLK, DBCLK rising edge
3.28
3.48
3.74
ns
tRISE
10% - 90%
100
150
200
ps
tFALL
90% - 10%
100
150
200
ps
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Data Latency ? Clock Cycles
SAMPLE N
CLKINP
tPD
DACLKP
DCLK edges are centered within
the data valid window
DA[11:0]P/N
OVRAP/N
N-1
N
N+1
CLKIN, DCLK are differential:
Only the ‘P’ positive signal shown for clarity
tsu
th
Figure 3. Timing Diagram for 12-bit DDR Output
10
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TYPICAL CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
FFT FOR 10 MHz INPUT SIGNAL (auto on)
FFT FOR 10 MHz INPUT SIGNAL (auto off)
Figure 4.
Figure 5.
FFT FOR 230 MHz INPUT SIGNAL (auto on)
FFT FOR 230 MHz INPUT SIGNAL (auto off)
Figure 6.
Figure 7.
FFT FOR 450 MHz INPUT SIGNAL (auto on)
FFT FOR 450 MHz INPUT SIGNAL (auto off)
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
12
FFT FOR 700 MHz INPUT SIGNAL (auto on)
FFT FOR 700 MHz INPUT SIGNAL (auto off)
Figure 10.
Figure 11.
SFDR
vs
INPUT FREQUENCY
SNR
vs
INPUT FREQUENCY
Figure 12.
Figure 13.
SFDR
vs
AMPLITUDE (fin = 230MHz)
SNR
vs
Amplitude (fin = 230 MHz)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
Tow Tone Performance Across Input Amplitude (fin =
130MHz)
SFDR
vs
Vref (auto on)
Figure 16.
Figure 17.
SFDR
vs
Vref (auto off)
SNR
vs
Vref (auto on)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
14
SNR
vs
Vref (auto off)
Performance Across Input Common Mode Voltage
Figure 20.
Figure 21.
Performance Across Temperature (fin = 230MHz)
Performance Across AVDD33 (fin = 230MHz)
Figure 22.
Figure 23.
Performance Across AVDD18 (fin = 230MHz)
Performance Across Clock Amplitude
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
INL
DNL
Figure 26.
Figure 27.
CMRR Across Frequency
PSRR Across Frequency
Figure 28.
Figure 29.
Power Across Sampling Frequency
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SFDR Across Input and Sampling Frequencies (auto on)
Figure 31.
16
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SFDR Across Input and Sampling Frequencies (auto off)
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SNR Across Input and Sampling Frequencies (auto on)
Figure 33.
18
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SNR Across Input and Sampling Frequencies (auto on)
Figure 34.
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FEATURES
POWER DOWN MODES
The ADS5403 can be configured via SPI write (address x37) to a stand-by, light or deep sleep power mode
which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low. Different
internal functions stay powered up which results in different power consumption and wake up time between the
two sleep modes.
Sleep mode
Wake up time
Power Consumption Auto
correction disabled
Power Consumption Auto
correction enabled
Complete Shut Down
2.5 ms
7mW
7mW
Stand-by
100µs
7mW
7mW
Deep Sleep
20µs
220mW
305mW
Light Sleep
2µs
367mW
448mW
TEST PATTERN OUTPUT
The ADS5403 can be configured to output different test patterns that can be used to verify the digital interface is
connected and working properly. To enable the test pattern mode, the high performance mode 1 has to be
disabled first via SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D
and x3E. All three registers must be configured for the test pattern to work properly.
First set HP1 = 0 (Addr 0x01, D01)
Register Address
All 0s
All 1s
Toggle (0xAAA => 0x555)
Toggle (0xFFF => 0x000)
0x3C
0x8000
0xBFFC
0x9554
0xBFFC
0x3D
0x0000
0x3FFC
0x2AA8
0x0000
0x3E
0x0000
0x3FFC
0x1554
0x3FFC
Register
Address
x3C
x3D
x3E
Custom Pattern
D15
1
0
0
D14
0
0
0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1
0
0
0
D0
0
0
0
For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, 0x3E all to 0.
CLOCK INPUT
The ADS5403 clock input can be driven differentially with a sine wave, LVPECL or LVDS source with little or no
difference in performance. The common mode voltage of the clock input is set to 0.9V using internal 2kΩ
resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as
possible to the clock inputs in order to minimize signal reflections and jitter degradation.
0.1uF
CLKINP
CLKINP
2kΩ
RT
0.9V
0.1uF
2kΩ
RT
CLKINN
CLKINN
0.1uF
Recommended differential clock driving circuit
Figure 35. Recommended Differential Clock Driving Circuit
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SNR AND CLOCK JITTER
The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not
noticeable in pipeline converters and is 74dB for a 12bit ADC. The thermal noise limits the SNR at low input
frequencies while the clock jitter sets the SNR for higher input frequencies.
SNRQuantization _ Noise
æ
SNR ADC [dBc] = -20 ´ log çç 10 20
è
2
2
2
ö æ
SNRThermalNoise ö æ
SNRJitter ö
+
10
÷÷ + ç 10 ÷ ç
÷
20
20
ø è
ø
ø è
The SNR limitation due to sample clock jitter can be calculated as following:
SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter)
(1)
(2)
The total clock jitter (TJitter) has three components – the internal aperture jitter (100fs for ADS5403) which is set
by the noise of the clock input buffer, the external clock jitter and the jitter from the analog input signal. It can be
calculated as following:
TJitter =
(TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2
(3)
External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass
filters at the clock input while a faster clock slew rate improves the ADC aperture jitter.
The ADS5403 has a thermal noise of 60.8 dBFS and internal aperture jitter of 100fs. The SNR depending on
amount of external jitter for different input frequencies is shown in the following figure.
SNR vs Input Frequency and External Clock Jitter
62
61
35 fs
50 fs
100 fs
150 fs
200 fs
SNR (dBFS)
60
59
58
57
56
55
10
100
1000
Fin (MHz)
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ANALOG INPUTS
The ADS5403 analog signal input is designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source which enables great flexibility
in the external analog filter design as well as excellent 50Ω matching for RF applications. The buffer also helps to
isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a
more constant SFDR performance across input frequencies.
The common-mode voltage of the signal input is internally biased to 1.9V using 500Ω resistors which allows for
AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.25V) and (VCM – 0.25V), resulting in a 1.0Vpp (default) differential input swing. The input sampling circuit has
a 3dB bandwidth that extends up to 1.2GHz.
2nH
0.5Ω
20Ω
INA_P
1.3pF
1.4pF
500Ω
Vcm= 1.9V
2nH
0.5Ω
20Ω
500Ω
INA_N
1.3pF
1.4pF
OVER-RANGE INDICATION
The ADS5403 provides a fast over-range indication on the OVRA/B pins. The fast OVR is triggered if the input
voltage exceeds the programmable overrange threshold and it gets presented after just 12 clock cycles enabling
a quicker reaction to an overrange event. The OVR threshold can be configured using SPI register writes.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the Over-range threshold bits. The threshold at which fast OVR is triggered is (full-scale × [the decimal
value of the FAST OVR THRESH bits] /16). After reset, the default value of the over-range threshold is set to 15
(decimal) which corresponds to a threshold of 0.56dB below full scale (20*log(15/16)).
OVR Detection Threshold
0
Thresholds set to dBFS
-5
-10
-15
-20
-25
0
2
4
6
8
10
12
14
16
Programmed Value (1-15)
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INTERLEAVING CORRECTION
The data converter channel consists of two interleaved ADCs each operating at half of the ADC sampling rate
but 180º out of phase from each other. The front end track and hold circuitry is operating at the full ADC
sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition the ADS5403
is equipped with internal interleaving correction logic that can be enabled via SPI register write.
ADC
ODD
Input
Track &
Hold
Fs
Interleaving
Correction
Fs/2
0 deg
ADC
EVEN
Estimator
Fs/2
180 deg
The interleaving operation creates 2 distinct and interleaving products:
• Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Since internally the front end
track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent
on gain mismatch.
• Fs/2 Spur: due to offset mismatch between ADCs
Input
Signal
Fs/2 Spur
Fs/2 - Fin
Fs/2
The auto correction loop can be enabled via SPI register write in address 0x01 and resetting the correction circuit
in address 0x03 and 0x1A. By default it is disabled for lowest possible power consumption. The default settings
for the auto correction function should work for most applications. However please contact Texas Instruments if
further fine tuning of the algorithm is required.
The auto correction function yields best performance for input frequencies below 250MHz..
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RECEIVE MODE: DECIMATION FILTER
There is an optional digital decimation filter in the data path as shown in Figure 36. The filter can be programmed
as a low-pass or a high-pass filter and the normalized frequency response of both filters is shown in Figure 37.
500 MSPS
Lowpass/
Highpass
selection
Low Latency Filter
250 MSPS
ADC
2
0, Fs/2
Figure 36.
The decimation filter response has a 0.1dB pass band ripple with approximately 41% pass-band bandwidth. The
stop-band attenuation is approximately 40dB.
Decimation Filter Response
Decimation Filter Response
10
0.1
0.08
0
0.06
Low Pass Filter
0.04
High Pass Filter
Attenuation (dB)
Attenuation (dB)
-10
-20
-30
0.02
0
-0.02
-0.04
-40
-0.06
-50
Low Pass Filter
-0.08
-60
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.05
Frequency (MHz)
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (MHz)
Figure 37.
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MULTI DEVICE SYNCHRONIZATION
The ADS5403 simplifies the synchronization of data from multiple ADCs in one common receiver. Upon receiving
the initial SYNC input signal, the ADS5403 resets all the internal clocks and digital logic while also starting a
SYNCOUT signal which operates on a 5bit counter (32 clock cycles). Therefore by providing a common SYNC
signal to multiple ADCs their output data can be synchronized as the SYNCOUT signal marks a specific sample
with the same latency in all ADCs. The SYNCOUT signal then can be used in the receiving device to
synchronize the FIFO pointers across the different input data streams. Thus the output data of multiple ADCs can
be aligned properly even if there are different trace lengths between the different ADCs.
ADS5403
DxCLK
Sample x
Sample 1
SYNCOUT
Sample 2
DA[11:0]
ChA
FIFO
Pointer
Sample 3
Sample 4
Sample 5
Sample 6
...
FPGA
ASIC
SYNC
ADS5403
DxCLK
SYNCOUT
ChA
DA[11:0]
Sample x
Sample 1
FIFO
Pointer
Sample 2
Sample 3
Sample 4
Sample 5
Sample 6
...
The SYNC input signal should be a one time pulse to trigger the periodic 5-bit counter for SYNCOUT or a
periodic signal repeating every 32 CLKIN clock cycles. It gets registered on the rising edge of the ADC input
clock (CLKIN). Upon registering the initial rising edge of the SYNC signal, the internal clocks and logic get reset
which results in invalid output data for 36 samples (1 complete sync cycle and 4 additional samples). The
SYNCOUT signal starts with the next output clock (DACLK) rising edge and operates on a 5-bit counter. If a
SYNCIN rising edge gets registered at a new position, the counter gets reset and SYNCOUT starts from the new
position.
Since the ADS5403 output interface operates with a DDR clock, the synchronization can happen on the rising
edge or falling edge sample. Synchronization on the falling edge sample will result in a half cycle clock stretch of
DACLK. For convenience the SYNCOUT signal is available on the ChA output LVDS bus. When using
decimation the SYNCOUT signal still operates on 32 clock cycles of CLKIN but since the output data is
decimated by 2, only the first 18 samples should be discarded.
CLKIN
16 clock cycles
SYNC
16 clock cycles
DACLK
16 clock cycles
SYNCOUT
16 clock cycles
DA[11 :0]
Data invalid – 36 samples
SYNC
16 clock cycles
16 clock cycles
DACLK
SYNCOUT
16 clock cycles
16 clock cycles
DA[11 :0]
Data invalid – 36 samples
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PROGRAMMING INTERFACE
The serial interface (SIF) included in the ADS5403 is a simple 3 or 4 pin interface. In normal mode, 3 pins are
used to communicate with the device. There is an enable (SDENB), a clock (SCLK) and a bi-directional IO port
(SDIO). If the user would like to use the 4 pin interface one write must be implemented in the 3 pin mode to
enable 4 pin communications. In this mode, the SDO pin becomes the dedicated output. The serial interface has
an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENB goes low will latch the
read/write bit. If a high is registered then a read is requested, if it is low then a write is requested. SDENB must
be brought high again before another transfer can be requested. The signal diagram is shown below:
Device Initialization
After power up, it is recommended to initialize the device through a hardware reset by applying a logic low pulse
on the SRESETb pin (of width greater than 20ns), as shown in Figure 38. This resets all internal digital blocks
(including SPI registers) to their default condition.
Power
Supplies
t1
SRESETb
t2
t3
SDENb
Figure 38. Device Initialization Timing Diagram
Table 1. Reset Timing
PARAMETER
CONDITIONS
MIN
t1
Power-on delay
Delay from power up to active low RESET pulse
t2
Reset pulse width
t3
Register write delay
TYP
MAX UNIT
3
ms
Active low RESET pulse width
20
ns
Delay from RESET disable to SDENb active
100
ns
Recommended Device Initialization Sequence:
1. Power up
2. Reset ADS5403 using hardware reset.
3. Apply clock and input signal.
4. Set register 0x01 bit D15 to ”1” (ChA Corr EN) to enable gain/offset correction circuit and other desired
registers.
5. Set register 0x03 D14 to “1” (Start Auto Corr ChA). This clears and resets the accumulator values in the DC
and gain correction loop.
6. Set register 0x03 D14 to “0” (Start Auto Corr ChA). This starts the DC and gain auto-correction loop.
Serial Register Write
The internal register of the ADS5403 can be programmed following these steps:
1. Drive SDENB pin low
2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address)
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3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
written
4. Write 16bit data which is latched on the rising edge of SCLK
SCLK
SDENB
SDIO
RWB
A6
A5
Read = 1
Write = 0
A4
A3
A2
A1
A0
D15
D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7 bit address space
16bit data: D15 is MSB, D0 is LSB
Figure 39. Serial Register Write Timing Diagram
PARAMETER
MIN
MAX
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1/tSCLK)
tSLOADS
SDENB to SCLK setup time
25
ns
tSLOADH
SCLK to SDENB hold time
25
ns
tDSU
SDIO setup time
25
ns
tDH
SDIO hold time
25
ns
(1)
>DC
TYP (1)
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD3V
= 3.3V, AVDD, DRVDD = 1.9V, unless otherwise noted.
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Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDO/SDIO
pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication
between the external controller and the ADC.
1. Drive SDENB pin low
2. Set the RW bit (A7) to '1'. This setting disables any further writes to the registers
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDO/SDIO pin
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to '0'.
SCLK
SDENB
SDIO
RWB
Read = 1
Write = 0
A6
A5
A4
A3
A2
A1
A0
D15
D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7 bit address space
16bit data: D15 is MSB, D0 is LSB
Figure 40. Serial Register Read Timing Diagram
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SERIAL REGISTER MAP (2)
(2)
Multiple functions in a register can be programmed in a single write operation.
Register
Address
A7–A0 IN
HEX
Register Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
3/4 Wire
SPI
Decimation
Filter
EN
0
ChA
High/
Low
Pass
0
0
0
0
0
0
0
0
0
0
0
0
1
ChA
Corr EN
0
0
0
0
0
0
0
0
0
0
0
Data
Format
0
Hp
Mode1
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
Start
Auto
Corr
ChA
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
Over-range threshold
E
Sync Select
0
0
0
0
0
0
0
Sleep Modes
0
0
0
0
0
0
VREF Set
Reset
38
3A
0
Temp Sensor
2C
37
0
Sync Select
F
2B
1
0
0
HP Mode2
LVDS Current Strength
Internal LVDS
Termination
LVDS SW
66
0
0
0
0
0
0
BIAS
EN
SYNC
EN
LP
Mode 1
1
1
1
1
0
DACLK
EN
LP
Mode 2
0
OVRA
EN
LP
Mode 3
D3
0
D2
0
0
0
LVDS Output Bus A EN
DESCRIPTION OF SERIAL INTERFACE REGISTERS
Register
Address
A7-A0 in hex
0
Register Data
D15
3/4
Wire
SPI
D14
Decimation
Filter
EN
D13
0
D12
ChA
High/
Low
Pass
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D15
3/4 Wire SPI
Default 0
0
3 wire SPI is used with SDIO pin operating as bi-directional I/O port
1
4 wire SPI is used with SDIO pin operating as data input and SDO pin as data output port.
D14
Decimation
Filter EN
Default 0
0
Normal operation with data output at full sampling rate
1
2x decimation filter enabled
D12
ChA High/Low
Pass
Default 0
0
Low Pass
1
High Pass
D1
0
D0
0
Enables 4-bit serial interface when set
2x decimation filter is enabled when bit is set
(Decimation filter must be enabled first: set bit D14)
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ADS5403
SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
Register
Address
A7-A0 in hex
1
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Register Data
D15
ChA
Corr
EN
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D15
ChA Corr EN (should be enabled for maximum performance)
Default 0
0
auto correction disabled
1
auto correction enabled
D3
Data Format
Default 0
0
Two's complement
1
Offset Binary
D1
HP Mode 1
Default 0
1
Must be set to 1 for optimum performance
Register
Address
A7-A0 in
hex
2
D10-D7
D4
0
D3
Data
Format
D2
0
D1
HP
Mode1
D0
0
Register Data
D15
D14
D13
D12
D11
0
0
0
0
0
Over-range threshold
D10
D9
D8
D7
Over-range threshold
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
The over-range detection is triggered 12 output clock cycles after the
overload condition occurs. The threshold at which the OVR is triggered =
1.0V x [decimal value of ]/16. After power up or
reset, the default value is 15 (decimal) which corresponds to a OVR
threshold of 0.56dB below fullscale (20*log(15/16)). This OVR threshold is
applicable to both channels.
Default 1111
OVR Detection Threshold
0
Thresholds set to dBFS
-5
-10
-15
-20
-25
0
2
4
6
8
10
12
14
16
Programmed Value (1-15)
30
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SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
Register
Address
A7-A0 in
hex
3
Register Data
D14
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Start
Auto
Corr
ChA
0
0
1
0
1
1
0
0
0
1
1
0
0
0
D5
D4
D3
D2
D1
D0
0
0
Start Auto Corr ChA
Starts DC offset and Gain correction loop for ChA
Default 1
Starts offset and Gain correction loop for ChA
Clears DC offset correction value to 0 and Gain correction value to 1
0
1
D11, 9, 8, 4, 3
Must be set to 1 for maximum performance
Default 1
Register
Address
A7-A0 in
hex
E
Register Data
D15
0000 0000 0000 00
0101 0101 0101 01
1010 1010 1010 10
1111 1111 1111 11
D15-D12
0000
0101
1010
1111
D6-D4
000
001
010
011
100
Others
D13
D12
D11
D10
D9
D8
D7
D6
Sync Select
D15-D2
Register
Address
A7-A0 in
hex
F
D14
Sync Select
Sync selection for the clock generator block (also
Default 1010 1010
need to see address 0x0F)
1010 10
Sync is disabled
Sync is set to one shot (one time synchronization only)
Sync is derived from SYNC input pins
not supported
Register Data
D15
D14
D13
Sync Select
D12
D11
D10
D9
D8
D7
0
0
0
0
0
D6
D5
D4
VREF Sel
D3
D2
D1
D0
0
0
0
0
Sync Select
Sync selection for the clock generator block
Default 1010
Sync is disabled
Sync is set to one shot (one time synchronization only)
Sync is derived from SYNC input pins
not supported
VREF SEL
Default 000
1.0V
1.25V
0.9V
0.8V
1.15V
external reference
Internal voltage reference selection
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ADS5403
SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
Register
Address
A7-A0 in
hex
2B
D8-D0
Register Data
D15
D14
D13
D12
D11
D10
D9
0
0
0
0
0
0
0
Temp Sensor
Register
Address
A7-A0 in
hex
2C
D15
D14
000000
100000
110000
110101
Register
Address
A7-A0 in
hex
38
32
D7
D6
D5
D4
D3
D2
D1
D0
Temp Sensor
Internal temperature sensor value – read only
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
Reset
Default
0000
1101001011110000
D15-D14
D8
Register Data
D15-D0
Register
Address
A7-A0 in
hex
37
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This is a software reset to reset all SPI registers to their default value. Self
clears to 0.
Perform software reset
Register Data
D15
D14
D13
D12
D11
D10
Sleep Modes
Sleep Modes
Default 00
Complete shut down
Stand-by mode
Deep sleep mode
Light sleep mode
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
Sleep mode selection which is controlled by the ENABLE pin. Sleep modes are active when
ENABLE pin goes low.
Wake up
Wake up
Wake up
Wake up
time 2.5 ms
time 100 µs
time 20 µs
time 2 µs
Register Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
HP Mode 2
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D6
D5
Bias
EN
D4
SYNC
LP
EN
Mode
1
D3
D2
D1
D0
1
1
1
1
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ADS5403
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SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
D15-D7 HP Mode 2
Default 111111111
1
Set to 1 for normal operation
D6
0
1
D5
0
1
D4
0
1
D3-D0
BIAS EN
Default 1
Internal bias powered
down
Internal bias enabled
Enables internal fuse bias voltages – can be disabled after
power up to save power.
SYNC EN
Default 1
SYNC input buffer
disabled
SYNC input bffer enabled
Enables the SYNC input buffer.
LP Mode
Default 1
Internal input buffer
disabled
Internal input buffer
enabled
Low power mode 1 to disable internal unused input buffer.
Reads back 1
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ADS5403
SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
Register
Address
A7-A0 in hex
3A
D15-D13
000
001
010
011
D12-D11
01
11
D10-D9
00
01
10
11
D4
0
1
D3
0
1
D1
0
1
D0
0
1
34
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Register Data
D15 D14 D13
LVDS Current
Strength
LVDS Current
Strength
Default 000
2 mA
2.25 mA
2.5 mA
2.75 mA
D12 D11
LVDS SW
D10
D9
Internal
LVDS
Termination
D8
0
D7
0
D6
0
D5
0
D4
DACLK
EN
D3
LP
Mode 2
D2
0
D1
OVRA
EN
D0
LP
Mode
3
LVDS output current strength.
100
101
110
111
3 mA
3.25 mA
3.5 mA
3.75 mA
LVDS SW
LVDS driver internal switch setting – correct range must be set for setting in D15-D13
Default 01
2 mA to 2.75 mA
3mA to 3.75mA
Internal LVDS
Internal termination
Termination
Default 00
2 kΩ
200 Ω
200 Ω
100 Ω
DACLK EN
Enable DACLK output buffer
Default 1
DACLK output buffer powered down
DACLK output buffer enabled
LP Mode 2
Low power mode to disable unused internal output
buffer
Default 1
Internal output buffer disabled
Internal output buffer enabled
OVRA EN
Enable OVRA output buffer
Default 1
OVRA output buffer powered down
OVRA output buffer enabled
LP Mode 3
Low power mode to disable unused internal output buffer
Default 1
Internal output buffer disabled
Internal output buffer enabled
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ADS5403
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Register
Address
A7-A0 in
hex
66
D15-D0
0
1
D15
D14
D13
D12
D11-D0
SLAS944B – FEBRUARY 2013 – REVISED JANUARY 2014
Register Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LVDS Output Bus A EN
LVDS Output Bus A EN
Default FFFF
Output is powered down
Output is enabled
Individual LVDS output pin power down for channel A
Pins N7, P7 (no connect pins) which are not used and should be powered down for
power savings
Pins N6, P6 (no connect pins) which are not used and should be powered down for
power savings
SYNCOUTP/N (pins N5, P5)
Pins N4, P4 (no connect pins) which are not used and should be powered down for
power savings
corresponds to DA11-DA0
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ADS5403
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REVISION HISTORY
Changes from Revision A (August 2013) to Revision B
Page
•
Changed package from QFN to nFBGA in THERMAL INFORMATION .............................................................................. 5
•
Deleted last sentence in INTERLEAVING CORRECTION section .................................................................................... 23
•
Changed second paragraph in MULTI DEVICE SYNCHRONIZATION section ................................................................. 25
•
Deleted Register Initialization section and added Device Initialization section .................................................................. 26
•
Changed Register Address E Bits D1 and D0 to 0 in SERIAL REGISTER MAP .............................................................. 29
•
Changed Register Address 38 Bits D3 to D0 from 0 to 1 in SERIAL REGISTER MAP .................................................... 29
•
Changed Register Address 38 Bits D3 to D0 from 0 to 1 and add D3 to D0 Read back 1 ................................................ 32
•
Changed Register Address 66 D15-D10 to D15-D0 and DA11-D0 to DA11-DA0 ............................................................. 35
Changes from Original (February 2013) to Revision A
Page
•
Changed D15-10 in register 66 From: Individual LVDS output pin power down for channel B To: Individual LVDS
output pin power down for channel A ................................................................................................................................. 35
•
Changed D13 in Register 66 From: SYNCOUTP/N (pins F1, F2) To: SYNCOUTP/N (pins N5, P5) ................................ 35
•
Changed D12 in egister 66 From: "Pins E3, E4..." To: "Pins N4, P4..." ............................................................................. 35
•
Changed D11-D10 - corresponds to DB11-DB0 in Register 66 To: D11-D0 - corresponds to DA11-D0 .......................... 35
36
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS5403IZAY
ACTIVE
NFBGA
ZAY
196
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS5403I
ADS5403IZAYR
ACTIVE
NFBGA
ZAY
196
1000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS5403I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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