DAC161P997CISQX/NOPB

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 DAC161P997 Single-Wire 16-bit DAC for 4- to 20-mA Loops 1 Features 3 Description • • • • • • • • • • The DAC161P997 is a 16-bit ∑Δ digital-to-analog converter (DAC) for transmitting an analog output current over an industry standard 4-20 mA current loop. It offers 16-bit accuracy with a low output current temperature coefficient (29 ppm/°C) and excellent long-term output current drift (90 ppmFS) while consuming less than 190 µA. 1 • 16-Bit Linearity Single-Wire Interface (SWIF), with Handshake Digital Data Transmission (No Loss of Fidelity) Pin Programmable Power-Up Condition Self Adjusting to Input Data Rate Loop Error Detection and Rreporting Programmable Output Current Error Level No External Precision Components Simple Interface to HART Modulator Small Package: WQFN-16 (4 x 4 mm, 0.5 mm Pitch) Key Specifications – Output Current TempCo: 29 ppmFS/°C (Max) – Long-Term Output Current Drift: 90 ppmFS (Typ) – INL: 3.3/−2.1 µA(Max) – Total Supply Current: 190 µA (Max) The data link to the DAC161P997 is a Single Wire Interface (SWIF) which allows sensor data to be transferred in digital format over an isolation boundary using a single isolation component. The DAC161P997’s digital input is compatible with standard isolation transformers and opto-couplers. Error detection and handshaking features within the SWIF protocol ensure error free communication across the isolation boundary. For applications where isolation is not required, the DAC161P997 interfaces directly to a microcontroller. The loop drive of the DAC161P997 interfaces to a HART (Highway Addressable Remote Transducer) modulator, allowing injection of FSK modulated digital data into the 4-20 mA current loop. This combination of specifications and features makes the DAC161P997 ideal for 2- and 4-wire industrial transmitters. 2 Application • • • • • • • • Two-Wire, 4-20 mA Current Loop Transmitter Industrial Process Control Actuator Control Factory Automation Building Automation Precision Instruments Data Acquisition Systems Test Systems The DAC161P997 is available in a 16–lead WQFN package and is specified over the extended industrial temperature range of -40°C to 105°C. Device Information(1) PART NUMBER DAC161P997 PACKAGE BODY SIZE (NOM) WQFN (16) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic In d u s tr i a l 4 - 2 0m A Tr a n sm i tte r LDO VD VA µC Sensor IN XFRMR DIN GPIO ACKB Single Wire Interface (SWIF) and Controller DAC161P997 DBACK LOOP+ ERRB LOOP SUPPLY 0-24 mA Loop ÐÂ DAC 16 + IDAC + - BASE COMD ERRLVL LOOP RECEIVER Galvanic Boundary COMA 80k LOW 40 OUT NC C1 C2 LOOP- C3 COM HART Modulator Circuit common return node 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Application ............................................................. Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 5 5 5 5 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ............................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 7.5 Programming .......................................................... 12 7.6 Register Maps ........................................................ 18 8 Application and Implementation ........................ 20 8.1 Application Information............................................ 20 8.2 Typical Application ................................................. 26 9 Power Supply Recommendations...................... 30 10 Layout................................................................... 30 10.1 Layout Guidelines ................................................. 30 10.2 Layout Example .................................................... 30 11 Device and Documentation Support ................. 31 11.1 11.2 11.3 11.4 Third-Party Products Disclaimer ........................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 12 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History Changes from Revision F (January 2013) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Changed the second Thead to tbody/row and changed role to hdr in the Timing Requirements table ................................ 7 • Deleted the Related links subsection and checked for setting of single-part ...................................................................... 31 Changes from Revision E (October 2013) to Revision F • Changed O to Ω in table....................................................................................................................................................... 17 Changes from Revision D (March, 2013) to Revision E • 2 Page Page Changed application circuit .................................................................................................................................................. 26 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 5 Pin Configuration and Functions COMA 1 COMD 2 VD 3 DIN 4 VA C1 C2 15 14 13 BASE 16 WQFN (RGH0016A) 16 pins Top View 12 C3 11 NC 10 LOW 9 OUT 6 7 8 ACKB ERRB ERRLVL DBACK 5 DAP=COMA Pin Functions PIN NAME NO. VA 15 DESCRIPTION ESD PROTECTION Analog block positive supply rail ESD Clamp COMA VA COMA 1 Analog block negative supply rail (local COMMMON) ESD Clamp COMA COMD 2 Digital block negative supply rail (local COMMON) Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 3 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com Pin Functions (continued) PIN NAME NO. DESCRIPTION VD 3 DIN 4 SWIF input DBACK 5 SWIF input loop back ACKB 6 SWIF acknowledge output - open drain, active LOW ERRLVL 8 Sets the output current level at power-up LOW 10 Must be tied to COMA, COMD potential C1 14 External capacitor C2 13 External capacitor, HART Input C3 12 External capacitor BASE 16 External NPN base drive N.C. 11 User must not connect to this pin ERRB 7 Error flag output open drain, active LOW ESD PROTECTION Digital block positive supply rail VA COMA COMA COMA OUT DAP 9 Loop output current source - Die Attach Pad. For best thermal conductivity and best noise immunity DAP should be soldered to the PCB pad which is connected directly to circuit common node (COMA, COMD) - 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply relative to common (VA, VD to COMA, COMD) MIN MAX UNIT −0.3 6 V Voltage between any 2 pins (2) 6 V Current IN or OUT of any pin - except OUT (2) 5 mA Output current at OUT 50 mA 150 °C Junction Temperature −65 Storage temperature range, Tstg (1) (2) 4 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. When the input voltage (VIN) at any pin exceeds power supplies (VIN < COMA or VIN > VA), the current at that pin must not exceed 5 mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6.0V. See Pin Fuctions for additional details of input structures. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±5500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Supply Voltage Range MIN MAX UNIT 2.7 3.6 V (VA - VD) 0 0 V (COMA - COMD) 0 0 V BASE load to COMA 0 15 pF OUT load to COMA - - -40 105 Operating Temperature (TA) °C 6.4 Thermal Information THERMAL METRIC (1) RθJA (1) WQFN (16-PINS) UNIT 35 °C/W Junction-to-ambient thermal resistance For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Unless otherwise noted, these specifications apply for VA = VD = 2.7 V to 3.6 V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VA, VD Supply Voltage VA Supply Current VD Supply Current VA = VD 2.7 DACCODE=0x0200 (1) -40 to 105°C Total Supply Current VPOR Power On Reset supply rail potential threshold 1.3 3.6 V 75 µA 115 µA 190 µA 1.9 V DC ACCURACY N Resolution 16 Bits Integral Non-Linearity (2) 0x2AAA < DACCODE < 0xD555 (4mA < ILOOP < 20 mA) -40 to 105°C –2.1 DNL Differential Non-Linearity See (3) -40 to 105°C –0.2 0.2 TUE Total Unadjusted Error 0x2AAA < DACCODE < 0xD555 –0.23% 0.23% FS −9.16 9.16 µA 138 nA/°C INL 3.3 µA (4) OE Offset Error See -40 to 105°C Offset Error Temp. Coefficient (1) (2) (3) (4) At code 0x0200 the BASE current is minimal, i.e., device current contribution to power consumption is minimized. The SWIF link is inactive, i.e., after transmitting code 0x200 to the DAC161P997, there are no more transitions in the channel during the supply current measurement. INL is measured using “best fit” method in the output current range of 4 mA to 20 mA. Specified by design. Here offset is the y-intercept of the straight line defined by 4-mA and 20-mA points of the measured transfer characteristic. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 5 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for VA = VD = 2.7 V to 3.6 V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF. PARAMETER GE Gain Error TEST CONDITIONS See (5) -40 to 105°C MIN TYP −0.22% Gain Error Temp. Coefficient MAX 0.22% 5 FS 29 ppmFS/°C 4 mA Loop Current Error DACCODE = 0x2AAA -40 to 105°C −18 18 20 mA Loop Current Error DACCODE = 0xD555 -40 to 105°C −55 55 IERRL LOW ERROR Current ERR_LOW = default -40 to 105°C 3361 3375 3391 IERRH HIGH ERROR Current ERR_HIGH = default -40 to 105°C 21702 21750 21817 LTD UNIT µA Long Term Drift — mean shift of 12 mA output current after 1000 hrs at 150°C 90 ppmFS LOOP CURRENT OUTPUT (OUT) Output Current Minimum tested at DACCODE = 0x01C2 (6) -40 to 105°C Output Impedance COMA to OUT voltage drop 0.18 24 100 IOUT = 24 mA mA MΩ 960 mV 10 mA 20 nA/√Hz 300 nARMS BASE OUTPUT BASE short circuit output current BASE forced to COMA potential DYNAMIC CHARACTERISTICS Output Noise Density 1 kHz Integrated Output Noise 1 Hz to 1 kHz band SWIF I/O CHARACTERISTICS VIH DIN -40 to 105°C VIL DIN -40 to 105°C CDIN DIN input capacitance VOH DBACK VOL TD DBACK 0.7* VD 0.3*VD 10 I = 3 mA -40 to 105°C 2216 I = 5 mA -40 to 105°C 1783 pF mV I = 3 mA -40 to 105°C 547 I = 5 mA -40 to 105°C 1260 DIN to DBACK delay V 8 ns OPEN DRAIN OUTPUTS VOL VOL (5) (6) 6 ACKB ERRB I = 3 mA -40 to 105°C 550 I = 5 mA -40 to 105°C 1370 I = 300 µA -40 to 105°C 66 I = 3 mA -40 to 105°C 602 mV mV Here Gain Error is the difference in slope of the straight line defined by measured 4-mA and 20-mA points of transfer characteristic, and that of the ideal characteristic. This should be treated as the minimum LOOP current ensured specification. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for VA = VD = 2.7 V to 3.6 V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF. PARAMETER TEST CONDITIONS ACKB IOZ ERRB MIN TYP MAX Leakage current when output device is off -40 to 105°C 1 Leakage current when output device is off -40 to 105°C 1 UNIT µA 6.6 Timing Requirements MIN NOM MAX UNIT 19.2 kHz SWIF TIMING, INTERNAL TIMER Symbol rate: 1/TP 0.3 “D” symbol duty cycle: THD/TP TM 7/16 1/2 “0” symbol duty cycle: TH0/TP 3/16 1/4 5/16 "1” symbol duty cycle: TH1/TP 11/16 3/4 13/16 ACKB assert: TA/TP 1/16 1/4 4/8 ACKB deassert: TB/TP 12/8 7/4 31/16 90 100 110 Timeout PeriodM 9/16 ms pri_tx: ³0´ TH0 pri_tx: ³'´ THD pri_tx: ³1´ TH1 TP TP ACKB: ³$´ TA TB Figure 1. Single-Wire Interface (SWIF) Timing Diagram Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 7 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com 6.7 Typical Characteristics Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF. Data Rate = 300Baud Data Rate = 19200Baud 190 25 FREQUENCY OF OCCURRENCE (%) TOTAL SUPPLY CURRENT (A) 200 180 170 160 150 140 130 120 110 100 20 15 5 0 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 5 4 3 2 1 0 0 4 8 12 16 20 OUTPUT CURRENT (mA) 8 10 12 14 16 18 20 30 25 20 Tail of the distribution follows Gaussian PDF with: =3nA, 1=24nA/°C 15 10 5 0 0 24 20 40 60 80 100 OE TEMPERATURE COEFFICIENT (nA/°C) Figure 5. Offset Error TC Distribution 0 1M -10 100k SETTLING TIME (s) MAGNITUDE RESPONSE (dB) 6 35 Figure 4. Integrated Noise vs ILOOP -20 -30 -40 -50 C1=C2=C3=2.2nF HART Adaptation C1=C2=C3=1nF -60 10k 1k 100 10 -70 -80 C1=C2=C3=2.2nF HART Adaptation C1=C2=C3=1nF 1 1 10 100 1k 10k FREQUENCY (Hz) 100k Figure 6. ΣΔ Modulator Filter Response 8 4 Figure 3. Gain Error TC Distribution FREQUENCY OF OCCURRENCE (%) OUTPUT CURRENT RIPPLE A(rms) Integration BW=1kHz Integration BW=10kHz 2 GE TEMPERATURE COEFFICIENT (ppm/°C) Figure 2. Supply Current vs Supply Voltage 6 Tail of the distribution follows Gaussian PDF with: =2.0, 1=4.8 10 1 10 100 1k 10k INPUT CODE STEP (lsb) 100k Figure 7. Settling Time vs Input Step Size Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 Typical Characteristics (continued) Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF. 2.5 2.0 250 1.5 1.0 200 INL (A) TOTAL SUPLLY CURRENT (A) 300 150 VA=VD=2.7V VA=VD=3.0V VA=VD=3.3V VA=VD=3.6V 100 50 0.0 -0.5 -1.0 -1.5 -2.0 0 -2.5 0 4 8 12 16 20 OUTPUT CURRENT (mA) 24 Figure 8. Supply Current vs ILOOP 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 9. Output Linearity vs Temperature 120 C1=C2=C3=1nF C1=C2=C3=2.2nF C1=C2=C3=10nF C1=C2=C3=100nF 100 C1=C2=C3=1nF C1=C2=C3=2.2nF C1=C2=C3=10nF C1=C2=C3=100nF 100 80 PSRR (dB) PSRR (dB) Min INL Max INL 0.5 60 80 60 40 40 20 20 0 0 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 10. PSRR: ILOOP=4 mA 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 11. PSRR: ILOOP=20 mA Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 9 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The DAC161P997 is a 16-bit DAC realized as a ∑Δ modulator. The DAC’s output is a current pulse train that is filtered by the on-board low pass RC filter. The final output current is a multiplied copy of the filtered modulator output. This architecture ensures an excellent linearity performance, while minimizing power consumption of the device. The DAC161P997 eases the design of robust, precise, long-term stable industrial systems by integrating all precision elements on-chip. Only a few external components are needed to realize a low-power, high-precision industrial 4-20 mA transmitter. In case of a fault, or during initial power-up the DAC161P997 will output current in either upper or lower error current band. The choice of band is user selectable via a device pin. The error current value is user programmable via the SWIF link by the Master. 7.2 Functional Block Diagram VD ERRB LOW ERRLVL SWIF COMD DACCODE DBACK CONTROLLER DIN 6' OSC ERR_LOW CONFIG3 ERR_HIGH CONFIG2 LCK COMD CONFIG1 ACKB POR COMD NC VA VA 15k 15k 15k + - BASE IREF COMA COMA 80k 40 OUT C1 C2 C3 7.3 Feature Description 7.3.1 Error Detection and Reporting The user can modify the CONFIG2:(LOOP | CHANNEL | PARITY | FRAME) bits to mask or enable the reporting of any of the detectable fault conditions. The DAC161P997 reports errors by asserting the ERRB signal, and by setting the current sourced by OUT to a value dictated by the state at ERRLVL pin and the contents of the ERR_HIGH and ERR_LOW registers. Once the condition causing the fault is removed the OUT will return to the last valid output level prior to the occurrence of the fault. 10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 Feature Description (continued) Table 1 below summarizes the detectable faults, and means of reporting. The interval TM is governed by the internal timer and is specified in Electrical Characteristics. Table 1. Error Detection and Reporting REPORTING ERROR LOOP CHANNEL CAUSE The device cannot sustain the required output current at OUT pin, typically caused by drop in loop supply, or increased load impedance. The DAC161P997 automatically clears this fault after interval of TM and attempts to establish output current dictated by the value in the DACCODE register no valid symbols have been received on DIN in last interval of TM ERRB Value used by the DAC to set OUT pin current LOW ERR_LOW LOW PARITY SWIF received a valid data frame, but a bit error has been detected by parity check LOW FRAME invalid symbol received, or an incorrect number of valid symbols were detected in the frame LOW ERRLVL=1: ERR_HIGH ERRLVL=0: ERR_LOW ERRLVL=1: ERR_HIGH ERRLVL=0: ERR_LOW ERRLVL=1: ERR_HIGH ERRLVL=0: ERR_LOW 7.3.2 Alarm Current The DAC161P997 reports faults to the plant controller by forcing the OUT current into one of the error bands. The error current bands are defined as either above 20 mA, or below 4mA. The error band selection is done via the ERRLVL pin. The exact value of the output current used to indicate fault is dictated by the contents of ERR_HIGH and ERR_LOW registers. See ERR_LOW and ERR_HIGH. The default settings for LOW ERROR CURRENT and HIGH ERROR CURRENT are specified in Electrical Characteristics 7.4 Device Functional Modes SWIF is a versatile and robust solution for transmitting digital data over the galvanic isolation boundary using just one isolation element: a pulse transformer. Digital data format achieves the information transmission without the loss of fidelity which usually afflicts transmissions employing PWM (Pulse Width Modulation) schemes. Digital transmission format also makes possible data differentiation: user can specify whether given data word is a DAC input to be converted to loop current, or it is a device configuration word. SWIF was designed to use in conjunction with pulse transformer as an isolation element. The use of the transformers to cross the isolation boundary is typical in the legacy systems due to their robustness, low-power consumption, and low cost. However, system implementation is not limited to the transformer as a link since SWIF easily interfaces with opto-couplers, or it can be directly driven by a CMOS gate. SWIF incorporates a number of features that address robustness aspect of the data link design: Bidirectional signal flow the DAC161P997 can issue an ACKNOWLEDGE pulse back to the master transmitter, via the same physical channel, to confirm the reception of the valid data; Error Detection SWIF protocol incorporates frame length detection and parity checks as a method of verifying the integrity of the received data; Channel Activity Detection SWIF can monitor the data channel and raise an error flag should the expected activity drop below programmable threshold, due to , for example, damage to the physical channel. In the typical system the Master is a micro controller. SWIF has been implemented on a number of popular micro controllers where it places minimum demands on the hardware or software resources even of the simple 8-bit devices. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 11 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com Device Functional Modes (continued) SWIF gives the system designer flexibility is balancing the trade-offs between the data rate, activity monitoring functionality and the power consumption in the transformer coupled data channel. At lowest data rates, with long inactive inter-frame periods, the power consumed by SWIF is negligible. See Inter-Frame Period. 7.5 Programming 7.5.1 Single-Wire Interface (SWIF) SWIF provides flexible and easy to implement digital data link between the Master (transmitter) and the Slave (receiver). The Master encodes the digital data into a square (NRZ) CMOS level waveform which can be generated using common microcontroller resources. The Slave (DAC161P997) translates the waveform back into a bit stream which is then interpreted as the output current update or configuration data. SWIF can operate in both Simplex (unidirectional) and Half-Duplex (bidirectional) modes. In the DAC161P997's implementation of SWIF, an Acknowledge pulse constitutes the reverse data flowing from the Slave back to the Master. In its simplest implementation, the waveform can be directly coupled to the DAC161P997 input. In typical systems, however, SWIF data is transmitted via the galvanic isolation element such as pulse transformer or an opto-coupler. The details of the circuit implementations are discussed in Interface Circuit. Frame Format through Symbol Set describe the data encoding and the SWIF protocol. 7.5.1.1 Frame Format A frame begins with a minimum of one idle symbol. There can be more than one and each has the effect of resetting the frame buffer of the DAC161P997. After idle symbol “D” a Tag Bit specifies the destination of the frame. If the tag is symbol ‘0’ then frame’s destination is the DACCODE register. If tag is a ‘1’ the destination is one of the configuration registers. The following 16 symbols constitute the data payload. If current frame is a DAC frame, the entire payload is a single DACCODE word. If it is a configuration frame, the first byte is the register address and the second byte is the register data. Words are transmitted MSB first. Two parity symbols follow the payload. The first parity symbol is determined by the bit parity of the tag bit and the first byte of payload (HIGH Slice) – a total of nine symbols. The second parity symbol corresponds to bit parity of the second byte of payload only (LOW Slice) – a total of 8 symbols. P0 = [ ( Number of ones in LOW Slice ) mod 2 == 0 ] P1 = [ ( Number of ones in HIGH Slice ) mod 2 == 0 ] Symbol ‘D’ after the parity bits completes a valid frame. The symbol “A” is optional, but if present it has to immediately follow the last “D” symbol of the frame. The duration of acknowledge symbol “A” is always twice the duration of P0 symbol preceding it. See Figure 12. SWIF does not require that all symbols in valid frames are sent by the Master at a fixed Baud rate. Each symbol is evaluated individually and is recognized as valid as long as it conforms to the duration requirement (Tp) and its duty cycle falls outside of noise margins. (See Table 2 below.) 12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 Programming (continued) DAC Input Data Frame Parity Bits Tag Bit D 0 DATA[15:8] DATA[7:0] ³+,*+VOLFH´ P1 P0 D A ³/2:VOLFH´ Configuration Data Frame Tag Bit D 1 Parity Bits REG. ADDRESS[7:0] DATA[7:0] ³+,*+VOLFH´ P1 P0 D A ³/2:VOLFH´ Figure 12. Data Frame Format 7.5.1.2 Inter-Frame Period The fastest DAC update rate is achieved when Master sends the valid frames back to back, Continuous Mode, at the fastest Baud rate. This, however, results in the least power efficient implementation. Frame Frame Frame SWIF is designed to operate in the Burst Mode as well, where the valid frames are separated by the inter-frame periods that do not carry any data. The inter-frame period can be occupied by a stream of idle ‘D’ or ‘L’ symbols. Interframe Period Frame D D D D Frame Sending the ‘D’ symbol in the inter-frame period provides continuous verification of integrity of the data link. The device by default monitors the activity of the SWIF link, and if the activity ceases the ERRB flag is asserted. See CONFIG2 and Error Detection and Reporting. Interframe Period Frame Frame Sending the ‘L’ in the inter-frame period results in the transmission line being inactive (transition-free) except when the data frames are being transmitted. This is the most power efficient implementation of SWIF link, but it does not facilitate link integrity reporting. To avoid ERRB being asserted due to the channel inactivity, CONFIG2.CHANNEL should be cleared. 7.5.1.3 Symbol Set The digital data encoding scheme is outlined in the table below. The signal names in the table correspond to the nodes shown in Figure 27. The signal waveforms due to a random symbol stream are shown in Figure 13. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 13 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com Programming (continued) Table 2. Symbol Set Table Character Mnemonic SWIF Symbol Symbol Period pri_tx “0” Comments • • • • Occupies one symbol period Transmit from Master only 25% duty-cycle square waveform Terminates LOW • • • • Occupies one symbol period Transmit from Master only 75% duty-cycle square waveform Terminates LOW • • • • Occupies one symbol period Transmit from Master only 50% duty-cycle square waveform Terminates LOW • • Occupies two symbol periods Master stops driving the SWIF and “listens” for acknowledge pulse from the Slave Slave pulls ACKB LOW to reverse the direction of data flow through the transformer Slave's DBACK will drive the SWIF pri_rx line between 50% points of the adjacent periods - in this interval Master must de-assert pri_tx_en_n Terminates with pri_tx = LOW and pri_tx_en_n = LOW pri_tx_en_n 25 50 75 Symbol Period pri_tx “1” pri_tx_en_n 25 50 75 Symbol Period pri_tx “D” pri_tx_en_n 25 50 75 Symbol Period Symbol Period pri_tx “A” • driven by Slave pri_rx • pri_tx_en_n 25 50 75 25 50 75 • • Symbol Period “L” • • • • pri_tx pri_tx_en_n Occupies one symbol period, but can be repeated indefinitely Transmit from Master only Always LOW Does not carry any meaningful information Used as an inter-frame symbol, i.e., sent by the Master between valid data frames 25 50 75 14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 ³'011'$'´ Symbol Period Symbol Period Symbol Period Symbol Period Symbol Period Symbol Period Symbol Period Symbol Period 25 50 75 25 50 75 25 50 75 25 50 75 25 50 75 25 50 75 25 50 75 25 50 75 pri_tx pri_tx_en_n pri_rx driven by Slave driven by Master Figure 13. Symbol Stream Example 7.5.1.4 Interface Circuit SWIF interface components are shown in Figure 14. The buffers A and B comprise a square waveform recovery circuit in applications where a pulse transformer is used to cross the galvanic isolation boundary, see Transformer Coupled Interface - Data Flow to the DAC. The ACKB output and its internal NMOS switch provide the means of reversing the direction of data flow through the coupling transformer see Transformer Coupled Interface - Acknowledge Pulse. In simple cases where the data link is DC coupled buffer A alone acts as a data receiver. The buffer C is provided for cases where improved noise immunity is required, see DC-Coupled Interface. DBACK B DAC161P997 C 8k DIN to SWIF decoder A ACKB COMD Figure 14. SWIF Front End 7.5.1.4.1 Transformer Coupled Interface - Data Flow to the DAC In systems requiring galvanic isolation between the transmitter (micro-controller) and the receiver, the commonly used coupling element is a pulse transformer. Transformer passes only the AC components of the square input waveform resulting in an impulse train across the secondary winding. Buffers A and B form a latch circuit around the secondary winding that recovers the square waveform from the impulse train. Figure 15 shows the details of the square waveform transmission from the primary side and recovery of the signal on the secondary side. Transmitter’s DC component is blocked by the capacitor CP. The transmitter’s output waveform VO results in the impulse train VP across the primary winding. Similar impulse train then appears across the secondary winding. If the magnitude of the impulse exceeds the threshold on the A buffer, the latch formed by A and B buffers will change state. The new latch state will persist until an opposite polarity impulse appears across the secondary winding. Note that in Figure 15 the capacitor CS bottom plate floats, and thus does not affect the operation of this circuit. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 15 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com PRIMARY SIDE SECONDARY SIDE VO to SWIF decoder DBACK Tx B + VP - DIN VP CP A CS ACKB FET OFF DAC161P997 COMD Figure 15. Transformer-Coupled SWIF Link With the DAC161P997 as Receiver 7.5.1.4.2 Transformer Coupled Interface - Acknowledge Pulse Since the transformer is a symmetrical device (particularly one with 1:1 winding ratio), it is simple to reverse the data flow through it. Figure 16 shows the SWIF interface circuit during the transmission of the Acknowledge pulse from the DAC161P997 on the secondary side back to the micro-controller on the primary side. On the secondary side buffer B drives the square waveform across the transformer. Capacitor CS, whose bottom plate is now grounded via the ACKB pin, blocks the DC component of the square waveform. Buffer A is inactive. On the primary side a square waveform recovery is performed by the now familiar latch. PRIMARY SIDE SECONDARY SIDE Handshake pulse (Acknowledge) DBACK (Tx) DIN B A N.C. CS ACKB FET ON DAC161P997 COMD Figure 16. Transformer-Coupled SWIF Link With the DAC161P997 as Transmitter 7.5.1.4.3 DC-Coupled Interface DC coupled signal path between the transmitter and the receiver is shown in Figure 17. Such circuit as the internal buffer A is sufficient for the signal recovery as the signal presented at the DIN input is a square CMOS level waveform. In noisy environments it may be necessary to implement a Hysteresis loop around the DIN input to improve noise immunity of the input circuit. Presence of the buffer C and its output resistor facilitate this. The Hysteresis can be easily realized by inserting RIN between the transmitter and DIN input. Note that when RIN = 0 the presence of the buffer C can be ignored. 16 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 to SWIF decoder C 8k DIN Tx A RIN DAC161P997 Figure 17. DC-Coupled SWIF Input 7.5.1.4.4 Transformer Selection and SWIF Data Link Circuit Design In general, the transformers developed for T1/E1 telecom applications are well suited as the interface element for the DAC161P997 in the galvanically isolated industrial transmitter. The application circuit schematic utilizing T1/E1 transformer as the isolation element is shown in Typical Application. A number of suggested off the shelf transformers are listed in Table 3. Table 3. Examples of Transformers Suitable in the DAC161P997 Applications Manufacturer P/N LM (mH) LLP/LLS (µH) RP/RS (Ω) CWW (pF) Isolation Voltage (Vrms) Pulse TX1491 1.2 1.2 2.7 35 1500 Coilcraft S5394–CLB 0.4 Not Specified 0.95 0.92 1500 Halo TG02-1205 1.2 Not Specified 0.7 30 1500 XFMRS XF7856-GD11 0.785 0.5 0.52 Not Specified 1500 Model suitable for simulating the behavior of the pulse transformer is shown in Figure 18. The model parameters are readily available in the datasheets provided by the transformer manufacturers, see Table 3 for examples. I1 RP LLP LLS I2 RS I1' = I2 + VP + CWP I LM + - CWS - VS = VP - Figure 18. Pulse Transformer Model - Winding Ratio 1:1 Table 4. Transformer Model Parameters' Legend Parameter LM Description Magnetizing inductance, in Data Sheets shown as OCL (open circuit inductance) LLP/S Leakage inductance of the primary (secondary) winding CWP/S Winding capacitance. Dominated by the CWW (winding to winding) component. Here it is assumed that CWS=CWP=½CWW RP/S Winding resistance The circuit behavior will be dominated by the DC blocking capacitance CP and the magnetizing inductance LM. In the example circuit shown in Figure 19 the rising edge of VO ultimately results in an impulse at the input DIN, see Figure 20. Once voltage at DIN is above VIH of the A buffer, the A buffer will change its state. However, the latch will acquire a new state only if the voltage at DIN persists above VIH for TPEAK > TD. The parasitic elements in the transformer model: LLS, LSP, CWS, CWP may result in the oscillating component superimposed on the dominant impulse response waveform shown in Figure 20. The oscillation should be controlled so that the condition TPEAK> TD is maintained. The typical method for controlling this parasitic oscillation is to insert a damping element into the signal path. A small resistance in series with transformer winding is such damping element. The typical application example in Typical Application illustrates this. The delay around the SWIF input latch, from DIN to DBACK, TD is specified in Electrical Characteristics. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 17 DAC161P997 SNAS515G – JULY 2011 – REVISED DECEMBER 2014 www.ti.com A RO CP DIN Tx + + VO VP - DELAY=TD + Transformer Model VS B - - CDIN DBACK Use IDEAL device models DAC161P997 Figure 19. NRZ Waveform Transmission and Recovery Circuit Model VDD VO 0V Response due to parasitics Dominant response VIH VS 0V TPEAK Figure 20. SWIF Link Circuit Response to Step-Input 7.6 Register Maps 7.6.1 LCK Address=0x00; Default=0x00 Bit Field Name Description 0x95 - registers unlocked 0x** - any value written locks registers A register lock prevents inadvertent changes to the configuration. The DAC output cannot be updated while software configuration registers are unlocked. 7:0 7.6.2 CONFIG1 Address=0x01; Default=0x08 Bit Field Name RESERVED. Always write 0. 4:3 0b00 - NOP 0b01 - set error 0b10 - clear error 0b11 - NOP Sets or clears the error condition. At power-on the error is set. Error is also cleared after reception of valid SWIF frame. These bits are self clearing. This functionality can be used for diagnostic purposes, e.g. Master can use SERR to force ILOOP into an error band, and then return it to previously held output level. SERR 2:1 0 18 Description 7:5 RESERVED. Always write 0. RST 0 - NOP 1- same as power-on reset. Once device is reset to default state the bit clears automatically Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: DAC161P997 DAC161P997 www.ti.com SNAS515G – JULY 2011 – REVISED DECEMBER 2014 7.6.3 CONFIG2 Address=0x02; Default=0x1F Bit Field Name 7:5 Description RESERVED. Always write 0. ACK_EN Set to enable ACK When enabled, an acknowledgement is indicated on the serial interface upon detection of each valid frame. See Frame Format. 3 FRAME Set to enable framing error reporting. See table in Error Detection and Reporting. 2 PARITY Set to enable parity error reporting. See table in Error Detection and Reporting. 1 CHANNEL 0 LOOP 4 Set to enable channel-inactive reporting. See table in Error Detection and Reporting. Set to enable loop error reporting. See table in Error Detection and Reporting. 7.6.4 CONFIG3 Address=0x03; Default=0x08 Bit Field Name 7:4 3:0 Description RESERVED. Always write 0. RX_ERR_CNT 0