DS91C176, DS91D176
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SNLS146L – MARCH 2006 – REVISED APRIL 2013
DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers
Check for Samples: DS91C176, DS91D176
FEATURES
DESCRIPTION
•
The DS91C176 and DS91D176 are 100 MHz single
channel M-LVDS (Multipoint Low Voltage Differential
Signaling) transceivers designed for applications that
utilize multipoint networks (e.g. clock distribution in
ATCA and uTCA based systems). M-LVDS is a new
bus interface standard (TIA/EIA-899) optimized for
multidrop networks. Controlled edge rates, tight input
receiver thresholds and increased drive strength are
sone of the key enhancements that make M-LVDS
devices an ideal choice for distributing signals via
multipoint networks.
1
2
•
•
•
•
•
•
•
DC to 100+ MHz / 200+ Mbps Low Power, Low
EMI Operation
Optimal for ATCA, uTCA Clock Distribution
Networks
Meets or Exceeds TIA/EIA-899 M-LVDS
Standard
Wide Input Common Mode Voltage for
Increased Noise Immunity
DS91D176 has Type 1 Receiver Input
DS91C176 has Type 2 Receiver with Fail-safe
Industrial Temperature Range
Space Saving SOIC-8 Package
The
DS91C176/DS91D176
are
half-duplex
transceivers that accept LVTTL/LVCMOS signals at
the driver inputs and convert them to differential MLVDS signals. The receiver inputs accept low voltage
differential signals (LVDS, B-LVDS, M-LVDS, LVPECL and CML) and convert them to 3V LVCMOS
signals. The DS91D176 has a M-LVDS type 1
receiver input with no offset. The DS91C176 has an
M-LVDS type 2 receiver which enable failsafe
functionality.
Typical Application in an ATCA Clock Distribution Network
Slot Card N
Slot Card N+1
MLVDS Transceivers
MLVDS Transceivers
80: RT
CLK1A (8 KHz)
80: RT
80: RT
CLK1B (8 KHz)
80: RT
80: RT
CLK2A (19.44 MHz)
80: RT
80: RT
CLK2B (19.44 MHz)
80: RT
80: RT
CLK3A (User Defined up to 100 MHz)
80: RT
80: RT
CLK3B (User Defined up to 100 MHz)
80: RT
ATCA Backplane
Figure 1. System Diagram
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS91C176, DS91D176
SNLS146L – MARCH 2006 – REVISED APRIL 2013
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Connection and Logic Diagram
Top View
Figure 2. SOIC Package
See Package Number D0008A
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
xxxxxx
xxx
Type 1
High
Type 2
2.4 V
High
150 mV
VID
Low
50 mV
0V
-50 mV
Low
-2.4 V
Transition Region
Figure 3. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1) (2)
−0.3V to +4V
Supply Voltage, VCC
Control Input Voltages
−0.3V to (VCC + 0.3V)
Driver Input Voltage
−0.3V to (VCC + 0.3V)
−1.8V to +4.1V
Driver Output Voltages
Receiver Input Voltages
−1.8V to +4.1V
Receiver Output Voltage
−0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
833 mW
Derate SOIC Package
6.67 mW/°C above +25°C
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
150°C/W
θJC
63°C/W
Maximum Junction Temperature
150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature
(Soldering, 4 seconds)
260°C
ESD Ratings:
(HBM 1.5kΩ, 100pF)
≥ 8 kV
≥ 250 V
(EIAJ 0Ω, 200pF)
≥ 1000 V
(CDM 0Ω, 0pF)
(1)
(2)
“Absolute Maximum Ratings” are those beyond which the safety of the device cannot be verified. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage, VCC
3.0
3.3
3.6
V
Voltage at Any Bus Terminal (Separate or Common-Mode)
−1.4
+3.8
V
2.4
V
LVTTL Input Voltage High VIH
2.0
VCC
V
LVTTL Input Voltage Low VIL
0
0.8
V
+25
+85
°C
Typ
Max
Units
650
mV
Differential Input Voltage VID
−40
Operating Free Air Temperature TA
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
(1) (2) (3) (4)
Min
M-LVDS Driver
|VAB|
Differential output voltage magnitude
ΔVAB
Change in differential output voltage magnitude
between logic states
VOS(SS)
Steady-state common-mode output voltage
|ΔVOS(SS)|
Change in steady-state common-mode output
voltage between logic states
VOS(PP)
Peak-to-peak common-mode output voltage
VA(OC)
Maximum steady-state open-circuit output voltage
VB(OC)
Maximum steady-state open-circuit output voltage
(1)
(2)
(3)
(4)
RL = 50Ω, CL = 5pF
See Figure 4 and Figure 6
RL = 50Ω, CL = 5pF
See Figure 4 and Figure 5
(VOS(PP) @ 500KHz clock)
480
−50
0
+50
mV
0.3
1.8
2.1
V
+50
mV
0
135
See Figure 7
mV
0
2.4
V
0
2.4
V
All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
All typicals are given for VCC = 3.3V and TA = 25°C.
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
CL includes fixture capacitance and CD includes probe capacitance.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)
Parameter
Test Conditions
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
Min
RL = 50Ω, CL = 5pF,CD = 0.5pF
See Figure 9 and Figure 10 (5)
Typ
Max
Units
1.2VSS
V
−0.2V
V
SS
-15
15
μA
VIL = 0.8V
-15
15
μA
IIN = -18mA
-1.5
See Figure 8
-43
43
mA
IIH
High-level input current (LVTTL inputs)
VIH = 2.0V
IIL
Low-level input current (LVTTL inputs)
VIKL
Input Clamp Voltage (LVTTL inputs)
IOS
Differential short-circuit output current
V
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See FUNCTION TABLES
VIT−
Negative-going differential input voltage threshold
See FUNCTION TABLES
VOH
High-level output voltage (LVTTL output)
IOH = −8mA
VOL
Low-level output voltage (LVTTL output)
IOL = 8mA
IOZ
TRI-STATE output current
VO = 0V or 3.6V
IOSR
Short-circuit receiver output current (LVTTL output)
VO = 0V
Type 1
20
50
mV
Type 2
94
150
mV
Type 1
Type 2
−50
20
mV
50
94
mV
2.4
2.7
V
0.28
0.4
10
μA
-48
-90
mA
32
µA
+20
µA
−10
V
M-LVDS Bus (Input and Output) Pins
IA
Transceiver input/output current
IB
VA = 3.8V, VB = 1.2V
Transceiver input/output current
VA = 0V or 2.4V, VB = 1.2V
−20
VA = −1.4V, VB = 1.2V
−32
VB = 0V or 2.4V, VA = 1.2V
−20
VB = −1.4V, VA = 1.2V
−32
−4
IAB
Transceiver input/output differential current (IA − IB)
VA = VB, −1.4V ≤ V ≤ 3.8V
IA(OFF)
Transceiver input/output power-off current
VA = 3.8V, VB = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
IB(OFF)
µA
VB = 3.8V, VA = 1.2V
Transceiver input/output power-off current
VA = 0V or 2.4V, VB = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
−20
VA = −1.4V, VB = 1.2V,
DE =VCC
0V ≤ VCC ≤ 1.5V
−32
VB = 3.8V, VA = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
VB = −1.4V, VA = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
−32
Transceiver input/output power-off differential
current (IA(OFF) − IB(OFF))
VA = VB, −1.4V ≤ V ≤ 3.8V,
DE = VCC
0V ≤ VCC ≤ 1.5V
−4
CA
Transceiver input/output capacitance
VCC = OPEN
CB
Transceiver input/output capacitance
CAB
Transceiver input/output differential capacitance
CA/B
Transceiver input/output capacitance balance
(CA/CB)
1.0
4
+20
µA
+4
µA
32
µA
+20
µA
µA
−20
(5)
µA
µA
VB = 0V or 2.4V, VA = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
IAB(OFF)
32
32
µA
+20
µA
µA
+4
µA
9
pF
9
pF
5.7
pF
Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)
Parameter
Test Conditions
Min
Typ
Max
Units
SUPPLY CURRENT (VCC)
ICCD
Driver Supply Current
RL = 50Ω, DE = VCC, RE = VCC
20
29.5
mA
ICCZ
TRI-STATE Supply Current
DE = GND, RE = VCC
6
9.0
mA
ICCR
Receiver Supply Current
DE = GND, RE = GND
14
18.5
mA
Min
Typ
Max
Units
1.3
3.4
5.0
ns
1.3
3.1
5.0
ns
300
420
ps
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
(1) (2)
Test Conditions
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
tPHL
Differential Propagation Delay High to Low
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD|
(3) (4)
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
Figure 9 and Figure 10
(5) (5)
tSKD3
Part-to-Part Skew
tTLH (tr)
Rise Time
tTHL (tf)
Fall Time
tPZH
Enable Time (Z to Active High)
tPZL
Enable Time (Z to Active Low )
tPLZ
Disable Time (Active Low to Z)
tPHZ
Disable Time (Active High to Z)
(4)
(4)
(4)
tJIT
Random Jitter, RJ
fMAX
Maximum Data Rate
1.3
ns
1.0
1.8
3.0
ns
1.0
1.8
3.0
ns
8
ns
8
ns
8
ns
8
ns
5.5
psrms
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
See Figure 11 and Figure 12
100 MHz Clock Pattern
(6)
2.5
200
Mbps
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
tPHL
Propagation Delay High to Low
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD|
tSKD3
Part-to-Part Skew
(4)
Rise Time
Fall Time
tPZH
Enable Time (Z to Active High)
tPZL
Enable Time (Z to Active Low)
tPLZ
Disable Time (Active Low to Z)
tPHZ
Disable Time (Active High to Z)
fMAX
Maximum Data Rate
(6)
4.7
7.5
ns
2.0
5.3
7.5
ns
0.6
1.7
ns
1.3
ns
(5) (4)
tTHL (tf)
(4)
(5)
2.0
(3) (4)
tTLH (tr)
(1)
(2)
(3)
CL = 15 pF
See Figure 13, Figure 14 and Figure 15
(4)
0.5
1.2
2.5
ns
0.5
1.2
2.5
ns
10
ns
10
ns
10
ns
10
ns
RL = 500Ω, CL = 15 pF
See Figure 16 and Figure 17
200
Mbps
All typicals are given for VCC = 3.3V and TA = 25°C.
CL includes fixture capacitance and CD includes probe capacitance.
tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.
tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Stimulus and fixture Jitter has been subtracted.
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Test Circuits and Waveforms
Figure 4. Differential Driver Test Circuit
A
~ 2.1V
B
~ 1.5V
'VOS(SS)
VOS
VOS(PP)
Figure 5. Differential Driver Waveforms
Figure 6. Differential Driver Full Load Test Circuit
Figure 7. Differential Driver DC Open Test Circuit
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Figure 8. Differential Driver Short-Circuit Test Circuit
Figure 9. Driver Propagation Delay and Transition Time Test Circuit
Figure 10. Driver Propagation Delays and Transition Time Waveforms
Figure 11. Driver TRI-STATE Delay Test Circuit
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Figure 12. Driver TRI-STATE Delay Waveforms
Figure 13. Receiver Propagation Delay and Transition Time Test Circuit
Figure 14. Type 1 Receiver Propagation Delay and Transition Time Waveforms
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Figure 15. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 16. Receiver TRI-STATE Delay Test Circuit
Figure 17. Receiver TRI-STATE Delay Waveforms
FUNCTION TABLES
Table 1. DS91D176/DS91C176 Transmitting (1)
Inputs
(1)
Outputs
RE
DE
D
B
A
X
2.0V
2.0V
L
H
X
2.0V
0.8V
H
L
X
0.8V
X
Z
Z
X — Don't care condition
Z — High impedance state
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Table 2. DS91D176 Receiving (1)
Inputs
(1)
Output
RE
DE
A−B
R
0.8V
0.8V
≥ +0.05V
H
0.8V
0.8V
≤ −0.05V
L
0.8V
0.8V
0V
X
2.0V
0.8V
X
Z
X — Don't care condition
Z — High impedance state
Table 3. DS91C176 Receiving (1)
Inputs
(1)
Output
RE
DE
A−B
R
0.8V
0.8V
≥ +0.15V
H
0.8V
0.8V
≤ +0.05V
L
0.8V
0.8V
0V
L
2.0V
0.8V
X
Z
X — Don't care condition
Z — High impedance state
Table 4. DS91D176 Receiver Input Threshold Test Voltages (1)
Resulting Differential
Input Voltage
Applied Voltages
(1)
Resulting Common-Mode
Input Voltage
Receiver Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
2.400V
1.200V
H
0.000V
2.400V
−2.400V
1.200V
L
3.800V
3.750V
0.050V
3.775V
H
3.750V
3.800V
−0.050V
3.775V
L
−1.400V
−1.350V
−0.050V
−1.375V
H
−1.350V
−1.400V
0.050V
−1.375V
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Table 5. DS91C176 Receiver Input Threshold Test Voltages (1)
Applied Voltages
(1)
10
Resulting Differential
Input Voltage
Resulting Common-Mode
Input Voltage
Receiver Output
VID
VIC
R
H
VIA
VIB
2.400V
0.000V
2.400V
1.200V
0.000V
2.400V
−2.400V
1.200V
L
3.800V
3.650V
0.150V
3.725V
H
3.800V
3.750V
0.050V
3.775V
L
−1.250V
−1.400V
0.150V
−1.325V
H
−1.350V
−1.400V
0.050V
−1.375V
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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PIN DESCRIPTONS
Pin No.
Name
Description
1
R
2
RE
Receiver output pin
Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the
receiver is enabled.
3
DE
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.
4
D
5
GND
Driver input pin
6
A
Non-inverting driver output pin/Non-inverting receiver input pin
7
B
Inverting driver output pin/Inverting receiver input pin
8
VCC
Ground pin
Power supply pin, +3.3V ± 0.3V
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Typical Performance Characteristics – DS91D176/DS91C176
Supply Current
vs.
Frequency
Output VOD
vs.
Load Resistance
Supply Current measured using a clock pattern with driver terminated VCC = 3.3V, TA = +25°C
to 50ohms . VCC = 3.3V, TA = +25°C.
Figure 18.
12
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Figure 19.
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REVISION HISTORY
Changes from Revision K (April 2013) to Revision L
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS91C176TMA
NRND
SOIC
D
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
-40 to 85
DS91C
176MA
DS91C176TMA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91C
176MA
DS91C176TMAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91C
176MA
DS91D176TMA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91D
176MA
DS91D176TMAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91D
176MA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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