DS91C180, DS91D180
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SNLS158M – MARCH 2006 – REVISED APRIL 2013
DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair
Check for Samples: DS91C180, DS91D180
FEATURES
DESCRIPTION
•
The DS91D180 and DS91C180 are 100 MHz MLVDS (Multipoint Low Voltage Differential Signaling)
line driver/receiver pairs designed for applications
that utilize multipoint networks (e.g. clock distribution
in ATCA and uTCA based systems). M-LVDS is a
bus interface standard (TIA/EIA-899) optimized for
multidrop networks. Controlled edge rates, tight input
receiver thresholds and increased drive strength are
sone of the key enhancments that make M-LVDS
devices an ideal choice for distributing signals via
multipoint networks.
1
2
•
•
•
•
•
•
•
DC to 100+ MHz / 200+ Mbps Low Power, Low
EMI Operation
Optimal for ATCA, uTCA Clock Distribution
Networks
Meets or Exceeds TIA/EIA-899 M-LVDS
Standard
Wide Input Common Mode Voltage for
Increased Noise Immunity
DS91D180 has Type 1 Receiver Input
DS91C180 has Type 2 Receiver Input for FailSafe Functionality
Industrial Temperature Range
Space Saving SOIC-14 Package (JEDEC MS012)
The DS91D180/DS91C180 driver input accepts
LVTTL/LVCMOS signals and converts them to
differential
M-LVDS
signal
levels.
The
DS91D180/DS91C180 receiver accepts low voltage
differential signals (LVDS, B-LVDS, M-LVDS, LVPECL and CML) and converts them to 3V LVCMOS
signals. The DS91D180 device has a M-LVDS type 1
receiver input with no offset.The DS91C180 device
has a type 2 receiver input which enable failsafe
functionality.
Typical Application in an ATCA Clock Distribution Network
Slot Card N
Slot Card N+1
MLVDS Drivers/Receivers
MLVDS Drivers/Receivers
80W RT
CLK1A (8 KHz)
80W RT
80W RT
CLK1B (8 KHz)
80W RT
80W RT
CLK2A (19.44 MHz)
80W RT
80W RT
CLK2B (19.44 MHz)
80W RT
80W RT
CLK3A (User Defined up to 100 MHz)
80W RT
80W RT
CLK3B (User Defined up to 100 MHz)
80W RT
ATCA Backplane
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS91C180, DS91D180
SNLS158M – MARCH 2006 – REVISED APRIL 2013
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Figure 1. Connection Diagram
Top View
See Package Number D0014A
Logic Diagram
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
xxx
x
xx
xxx
Type 1
High
Type 2
2.4 V
High
150 mV
VID
Low
50 mV
0V
-50 mV
Low
-2.4 V
Transition Region
Figure 2. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1) (2)
−0.3V to +4V
Supply Voltage, VCC
Control Input Voltages
−0.3V to (VCC + 0.3V)
Driver Input Voltage
−0.3V to (VCC + 0.3V)
−1.8V to +4.1V
Driver Output Voltages
Receiver Input Voltages
−1.8V to +4.1V
Receiver Output Voltage
−0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
1.1 W
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
113.7 °C/W
θJC
36.9 °C/W
Derate SOIC Package
8.8 mW/°C above +25°C
Maximum Junction Temperature
150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 4 seconds)
260°C
ESD Ratings:
≥ 5 kV
(HBM 1.5kΩ, 100pF)
≥ 250 V
(EIAJ 0Ω, 200pF)
≥ 1000 V
(CDM 0Ω, 0pF)
(1)
“Absolute Maximum Ratings” are those beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(2)
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage, VCC
3.0
3.3
3.6
V
Voltage at Any Bus Terminal (Separate or Common-Mode)
−1.4
+3.8
V
2.4
V
High Level Input Voltage VIH
2.0
VCC
V
Low Level Input Voltage VIL
0
0.8
V
+85
°C
Differential Input Voltage VID
−40
Operating Free Air Temperature TA
+25
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2) (3) (4)
Min
Typ
Max
Units
650
mV
M-LVDS Driver
|VYZ|
Differential output voltage magnitude
ΔVYZ
Change in differential output voltage magnitude
between logic states
VOS(SS)
Steady-state common-mode output voltage
|ΔVOS(SS)|
Change in steady-state common-mode output voltage
between logic states
VOS(PP)
Peak-to-peak common-mode output voltage
(VOS(pp) @ 500KHz clock)
VY(OC)
Maximum steady-state open-circuit output voltage
Figure 6
VZ(OC)
Maximum steady-state open-circuit output voltage
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
IIH
High-level input current (LVTTL inputs)
(1)
(2)
(3)
(4)
(5)
RL = 50Ω, CL = 5pF
Figure 3 and Figure 5
RL = 50Ω, CL = 5pF
Figure 3 and Figure 4
480
−50
0
+50
mV
0.3
1.8
2.1
V
+50
mV
0
RL = 50Ω, CL = 5pF,
CD = 0.5pF
Figure 8 and Figure 9 (5)
VIH = 2.0V
143
mV
0
2.4
V
0
2.4
V
1.2VSS
V
−0.2VSS
-15
V
15
μA
All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
All typicals are given for VCC = 3.3V and TA = 25°C.
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
CL includes fixture capacitance and CD includes probe capacitance.
Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
IIL
Low-level input current (LVTTL inputs)
VIL = 0.8V
-15
VIKL
Input Clamp Voltage (LVTTL inputs)
IIN = -18 mA
-1.5
IOS
Differential short-circuit output current
Figure 7
-43
Typ
Max
Units
15
μA
43
mA
V
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See Function Tables
Type 1
20
50
mV
Type 2
94
150
mV
Type 1
−50
VIT−
Negative-going differential input voltage threshold
See Function Tables
VOH
High-level output voltage
IOH = −8mA
VOL
Low-level output voltage
IOL = 8mA
IOZ
TRI-STATE output current
VO = 0V or 3.6V
−10
IOSR
Short circuit Rrceiver output current (LVTTL Output)
VO = 0V
-90
Type 2
20
mV
50
94
mV
2.4
2.7
0.28
V
0.4
10
-48
V
μA
mA
M-LVDS Bus (Input and Output) Pins
IA, IY
Receiver input or driver high-impedance output
current
IB, IZ
Receiver input or driver high-impedance output
current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = GND
VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE
= GND
−20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = GND
−32
−20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = GND
−32
−4
IAB, IYZ
Receiver input or driver high-impedance output
differential current (IA − IB or IY − IZ)
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V, DE
= GND
IA(OFF),
IY(OFF)
Receiver input or driver high-impedance output
power-off current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
IB(OFF),
IZ(OFF)
Receiver input or driver high-impedance output
power-off current
VA,Y = 0V or 2.4V, VB,Z = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
−20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
−32
−20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
−32
−4
+20
µA
32
µA
+20
µA
µA
+4
µA
32
µA
+20
µA
µA
VB,Z = 3.8V, VA,Y = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
VB,Z = 0V or 2.4V, VA,Y = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
µA
µA
VB,Z = 3.8V, VA,Y = 1.2V,
DE = GND
VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE
= GND
32
32
µA
+20
µA
µA
IAB(OFF),
IYZ(OFF)
Receiver input or driver high-impedance output
power-off differential current
(IA(OFF) − IB(OFF) or IY(OFF) − IZ(OFF))
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V,
DE = 0V
0V ≤ VCC ≤ 1.5V
CA, CB
Receiver input capacitance
VCC = OPEN
5.1
pF
CY, CZ
Driver output capacitance
8.5
pF
CAB
Receiver input differential capacitance
2.5
pF
CYZ
Driver output differential capacitance
5.5
pF
4
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+4
µA
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SNLS158M – MARCH 2006 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol
CA/B,
CY/Z
Parameter
Conditions
Min
Receiver input or driver output capacitance balance
(CA/CB or CY/CZ)
Typ
Max
Units
29.5
mA
1.0
SUPPLY CURRENT (VCC)
ICCD
Driver Supply Current
RL = 50Ω, DE = VCC, RE = VCC
17
ICCZ
TRI-STATE Supply Current
DE = GND, RE = VCC
7
9.0
mA
ICCR
Receiver Supply Current
DE = GND, RE = GND
14
18.5
mA
ICCB
Supply Current, Driver and Receiver Enabled
DE = VCC, RE = GND
20
29.5
mA
Min
Typ
Max
Units
3.4
5.5
ns
3.1
5.5
ns
300
420
ps
1.9
ns
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2)
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
1.0
tPHL
Differential Propagation Delay High to Low
CD = 0.5 pF
1.0
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD|
tSKD3
Part-to-Part Skew
(3) (4)
Figure 8 and Figure 9
(5) (4)
(4)
tTLH (tr)
Rise Time
tTHL (tf)
Fall Time
1.0
1.8
3.0
ns
1.0
1.8
3.0
tPZH
Enable Time (Z to Active High)
ns
RL = 50Ω, CL = 5 pF,
8
ns
tPZL
tPLZ
Enable Time (Z to Active Low )
CD = 0.5 pF
8
ns
Disable Time (Active Low to Z)
Figure 10 and Figure 11
8
tPHZ
Disable Time (Active High to Z)
ns
tJIT
Random Jitter, RJ
fMAX
Maximum Data Rate
(4)
(4)
100MHz clock pattern (6)
2.5
8
ns
5.5
psrms
200
Mbps
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
2.0
4.7
7.5
ns
tPHL
Propagation Delay High to Low
Figure 12 Figure 13 and Figure 14
2.0
5.3
7.5
ns
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD| (3) (4)
0.6
1.9
ns
tSKD3
Part-to-Part Skew
1.5
ns
(5) (4)
(4)
tTLH (tr)
Rise Time
tTHL (tf)
Fall Time (4)
tPZH
Enable Time (Z to Active High)
tPZL
Enable Time (Z to Active Low)
tPLZ
tPHZ
fMAX
Maximum Data Rate
(1)
(2)
(3)
(4)
(5)
(6)
0.5
1.2
3.0
ns
0.5
1.2
3.0
ns
RL = 500Ω, CL = 15 pF
10
ns
Figure 15 and Figure 16
10
ns
Disable Time (Active Low to Z)
10
ns
Disable Time (Active High to Z)
10
200
ns
Mbps
All typicals are given for V = 3.3V and TA = 25°C.
CL includes fixture capacitance and CD includes probe capacitance.
tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Stimulus and fixture jitter has been subtracted.
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Test Circuits and Waveforms
Figure 3. Differential Driver Test Circuit
A
~ 2.1V
B
~ 1.5V
'VOS(SS)
VOS
VOS(PP)
Figure 4. Differential Driver Waveforms
Figure 5. Differential Driver Full Load Test Circuit
Figure 6. Differential Driver DC Open Test Circuit
6
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Figure 7. Differential Driver Short-Circuit Test Circuit
Figure 8. Driver Propagation Delay and Transition Time Test Circuit
Figure 9. Driver Propagation Delays and Transition Time Waveforms
Figure 10. Driver TRI-STATE Delay Test Circuit
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Figure 11. Driver TRI-STATE Delay Waveforms
Figure 12. Receiver Propagation Delay and Transition Time Test Circuit
Figure 13. Type 1 Receiver Propagation Delay and Transition Time Waveforms
8
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Figure 14. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 15. Receiver TRI-STATE Delay Test Circuit
Figure 16. Receiver TRI-STATE Delay Waveforms
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FUNCTION TABLES
Table 1. DS91D180/DS91C180 Transmitting (1)
Inputs
(1)
Outputs
DE
D
Z
Y
2.0V
2.0V
2.0V
L
H
0.8V
H
0.8V
L
X
Z
Z
X — Don't care condition
Z — High impedance state
Table 2. DS91D180 Receiving (1)
Inputs
(1)
Output
RE
A−B
R
0.8V
≥ +0.05V
H
0.8V
≤ −0.05V
L
0.8V
0V
X
2.0V
X
Z
X — Don't care condition
Z — High impedance state
Table 3. DS91C180 Receiving (1)
Inputs
(1)
Output
RE
A−B
R
0.8V
≥ +0.15V
H
0.8V
≤ +0.05V
L
0.8V
0V
L
2.0V
X
Z
X — Don't care condition
Z — High impedance state
Table 4. DS91D180 Receiver Input Threshold Test Voltages (1)
Applied Voltages
(1)
10
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
2.400V
1.200V
H
0.000V
2.400V
−2.400V
1.200V
L
3.800V
3.750V
0.050V
3.775V
H
3.750V
3.800V
−0.050V
3.775V
L
−1.400V
−1.350V
−0.050V
−1.375V
H
−1.350V
−1.400V
0.050V
−1.375V
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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Table 5. DS91C180 Receiver Input Threshold Test Voltages (1)
Applied Voltages
(1)
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VID
VIC
R
H
VIA
VIB
2.400V
0.000V
2.400V
1.200V
0.000V
2.400V
−2.400V
1.200V
L
3.800V
3.650V
0.150V
3.725V
H
3.800V
3.750V
0.050V
3.775V
L
−1.250V
−1.400V
0.150V
−1.325V
H
−1.350V
−1.400V
0.050V
−1.375V
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
PIN DESCRIPTIONS
Pin No.
Name
1, 8
NC
Description
2
R
3
RE
Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the
receiver is enabled.
4
DE
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.
5
D
6, 7
GND
9
Y
Non-inverting driver output pin
10
Z
Inverting driver output pin
11
B
Inverting receiver input pin
12
A
Non-inverting receiver input pin
13, 14
VCC
Power supply pin, +3.3V ± 0.3V
No connect.
Receiver output pin
Driver input pin
Ground pin
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REVISION HISTORY
Changes from Revision L (April 2013) to Revision M
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS91C180TMA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91C180
TMA
DS91C180TMAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91C180
TMA
DS91D180TMA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91D180
TMA
DS91D180TMAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS91D180
TMA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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