GC5322
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SLWS206D – FEBRUARY 2008 – REVISED NOVEMBER 2010
GC5322 Wideband Digital Predistortion Transmit Processor
Check for Samples: GC5322
FEATURES
1
•
•
2
•
•
•
•
•
Integrated DUC, CFR, and DPD Solutions
40-MHz (28-Mhz) Signal Bandwidth, Third
(Fifth)-Order Expansion BW in DPD Section,
Maximum Complex Rate 140 Mhz
DUC: up to 12 CDMA2000 or TD-SCDMA,
4 W-CDMA, 3–10 MHz or 1–20 MHz OFDMA
Carriers
CFR: Typically Meets 3GPP TS 25.141 1.
Output Formatter and DAC Interface (OFMT)
The output format and DAC interface presents the GC5322 output in the proper format for the different DAC
output interfaces. The output formatter supports a test pattern for testing the DAC5682Z interface. The output
interfaces supported for the GC5322 are:
• DAC5682 interleaved IQ
8
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•
SLWS206D – FEBRUARY 2008 – REVISED NOVEMBER 2010
DAC5688 parallel IQ !!!
GC532x
DAC5682Z
DPD Clock
DAC Clock
CLKIN, CLKINC
ExtTerm
(1)
DataClock
TX21, TX20
DCLK, DCLKC
ExtPullup
TX[]
(See HW Data Sheet)
(2)
Differential Data
D[15:0]P, D[15:0]N
ExtPullup/
PullDown
SYNCP, SYNCN
B0371-01
(1)
100 Ω between P, N of series capacitor on DAC
(2)
500-Ω pullup to 1.8 V only required when DAC data clock is > 337.5 MHz
Figure 4. GC5322 to DAC5682Z Interface
DAC5688
GC532x
DPD Clock
DAC Clock
CLKIN, CLKINC
ExtTerm
(1)
DataClock
TX21, TX20
DCLK, DCLKC
ExtTerm1
TX[] - DACI[]
(See HW Data Sheet)
Single-Ended
1.8-V CMOS
DACA[15:0]
ExtTerm1
TX[] - DACQ[]
(See HW Data Sheet)
(2)
Single-Ended
1.8-V CMOS
DACB[15:0]
ExtTerm1
TX18
(2)
(2)
Single-Ended
1.8-V CMOS
TXENABLE
B0372-01
(1)
100 Ω between P, N of series capacitor on DAC
(2)
Tester uses 50 Ω to 0.9 V for data lines; TXENABLE 100 Ω to 1.8 V, 100 Ω to ground.
Figure 5. GC5322 to DAC5688 (Parallel IQ) Interface
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Feedback Path (FB)
The feedback path has two LVDS input ports. The A port is preferred (it has better timing). The external ADC
input is converted or processed to generate a complex signal. The feedback equalizer has eight complex taps as
a receive equalizer. The feedback path has a mixer to translate the complex IF to the 0IF reference. The ADC
feedback rate is at the same rate as the DPD clock (fS). The typical feedback is fS/4, fS3/4(m), or fS5/4 IF. The
feedback equalizer can provide (m) inverted spectral output, if needed.
The FB complex mixer translates the frequency of the complex input signal to 0IF. The feedback path has the
capability for nonlinear correction with a lookup table. TI ADCs that connect to the feedback path are the SDR
type ADS5444, DDR type ADS5445 (6149, 5517), DDR with reversed-data-phase ADSC217 and ADS5463. The
ADC feedback path has modified connections for shared feedback path operation (see Figure 2). The GC5322
simplifies timing by providing a FIFO for each ADC port.
NOTE
There are eight LVDS data lanes and one LVDS clock lane. If the ADC has < 8 LVDS
data lanes, the MSB of the ADC is connected to LVDS lane 7 (MSB) of the A feedback
port.
ADC
GC532x
MSB ALigned
ADC DDR Data
FB[17:2]
(See HW Data Sheet)
ADC[7P, 7N, 0P, 0N]
DDR Clock
FB[1:0]
ADC_OutClkP, N
B0373-01
Figure 6. LVDS DDR ADC to GC5322 FB Interface
Microprocessor (MPU) Interface
The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in
asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB,
and CEB control signals. There are EMIF control signals which are not directly connected to the DSP:
Table 1. EMIF to GC5322 Microprocessor Interface
6727 DSP EMIF
GC5322
Notes
EM_D[15.0]
UPDATA[15.0]
EM_A[8.0]
UPADDR[9.1]
EM_BA[1]
UPADDR[0]
EM_CS2
CEB
DSP HD[22:20] are used for logic for multiple chip
select, inverted output.
EM_RWB
OEB
Invert RWB, send to OEB
EM_WEB
WRB
EM_OEB
RDB
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HOST UHPI
INTERFACE
Note: One DSP Is
Shared With
GC532xs
Multiplex
Address
Half Data
UHPI
DSP RST
BOOTMODE
EMIF Addr
Cntl SDRAM
EMIF Data
SDRAM
r
e
s
TI6727
DSP
UPDATA[]
EMIF Addr
Cntl GC532x
DSP JTAG
Inv
RDB, CS2[]
INTROUT
To/From
Other GC532x
UPADDRESS[]
and CNTL CS2-2
First GC532x
INTROUT(2)
UPDATA[]
GPIO
Ant
SelCode
CS2-1
INTROUT
INTROUT
UPADDRESS[]
and CNTL
B0374-01
Figure 7. '6727 DSP to GC5322 EMIF Interface
Capture Buffers (CB)
The GC5322 has two capture buffers of 4096 complex words. The capture buffers are normally used to capture
the TX reference signal and the feedback output signal. Other signals can be captured:
• The TX reference from the DPD after the circular hard limiter
• The feedback output; this represents the waveform as seen by the PA.
• The error output
• Testbus(31:16)
• QRD error output
The second capture buffer can be used to provide:
• The TX reference from the DPD after the circular hard limiter
• The feedback output; this represents the waveform as seen by the PA.
• The error output
• Testbus(15:0)
Standard capture mode – The capture buffers can be armed to collect the 4K complex samples after a
programmable delay following a sync event.
Smart capture mode (SCB) – There are two trigger conditions that combine the number of samples greater than
a threshold; these are used to find a number of peak events while the transmit signal is above a threshold. In this
case, the magnitude and magnitude squared of the signal are compared against a threshold and counted. If the
capture buffer finds the trigger condition, the capture logic captures the programmed capture-buffer depth after
the trigger. This is a combination of DSP software and the GC5322 hardware.
NOTE
Capture buffer A has a special mode to source data for diagnostic testing.
The DSP host interface software has a function to select and get capture-buffer data. The
complex data is passed from the GC5322 to the EMIF bus, to the DSP, and back to the
host processor.
The DSP host software has a signal power monitoring function. This uses the
capture-buffer data to perform special monitoring, power measurement, and error
measurements.
A
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NOTE
There are special DSP software PA protection modes that use the capture buffer to
determine the DPD correction applied to the signal, the error between the DPD reference
input and the feedback signal. The capture buffers are also used in the initial bulk delay
and fractional delay alignment.
Input Syncs and Output Sync
The GC5322 features multiple user-programmable input syncs. There are three syncs sampled with the BBClock,
(A, B, C), and the sync D, DC as an LVDS sync is sampled by the DPD clock. Internally, the GC5322 can also
generate timed and software-controlled syncs. The sync A input is required for the GC5322 hardware to initialize.
It should ideally be the start of the frame or frame down link. The output sync is a test signal used for debugging.
The input syncs can be used to trigger:
• Power measurements
• DUC channel delay, dither, and tuner alignment
• Initializing/loading the DUC,, feedback, equalizer, LUTs, etc.
• Feedback path tuner alignment
• Capturing and sourcing of data through SCBs
NOTE
The Sync A external synchronization should match the customer TX frame (total TX period
– i.e., 5 ms). See Figure 3; these synchronization signals must meet the timing of the
BBClk. Sync A should be aligned with the BBFR signal.
Power Meters and Peak I-or-Q Monitors
There are three integrated I2 + Q2 power meters in the GC5322:
• GPP – each baseband input channel
• CFR – the CFR input or output, and which antenna stream (0, 1)
• DPD – the input to the DPD nonlinear correction after the DPDL gain, and which antenna stream (0, 1)
There are several peak I or Q monitors within the GC5322:
• FRW – The resampled combined IQ interleaved input to the DPD
• DPD – The input to the DPD nonlinear correction after the DPDL gain
• DPD – After the nonlinear correction in DPD, and separately after the linear correction in DPD
• FDBK – There is a peak monitor at the output of the feedback path.
NOTE
The DSP host software has a HW POWER meter setup and Get(Monitor) function to
configure and get data from the integrated I2 + Q2 values.
12
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SLWS206D – FEBRUARY 2008 – REVISED NOVEMBER 2010
PIN ASSIGNMENT AND DESCRIPTIONS
ZND Package
(Bottom View)
26
A
25
24
23
22
VSS1 VSS1 VSS1 VSS1 FB1
19
18
16
VDD
SYNC
FB31 FB35 VSSA2
BB15 BB11 BB7
SHV
C
BB3
BB0 VSS1 VSS1 VSS1
FB4
VDD
SYNC
FB30 FB34 VDDA2
FB8 FB10 FB14 FB16 FB20 FB24 FB26
BBFR BB12 BB8
SHV
B
BB4
BB1 VSS1 VSS1 VDD1
BB5
BB2 VSS1 VDD1 VSS1
FB11 FB15 FB17 FB21 FB25 FB27
11
8
6
3
FB9
12
9
5
FB5
14
10
7
20
17
15
13
21
4
2
1
B
VDD1 VSS1 VSS1 VSS1 FB0
C
VSS1 VDD1 VSS1 VSS1
MFIO
FB3
0
FB7 VDD1 FB13
VDD
SYNC
ADC
FB29 FB33 VDD1
FB19 FB23 VDD1
BBCLK BB13 BB9
SHV
A
IREF
D
VSS1 VSS1 VDD1 VSS1
MFIO
FB2
1
FB6 VDD1 FB12
VDD
SYNC
ADC
FB28 FB32 VSS1
FB18 FB22 VDD1
VDD1 BB14 BB10 BB6 VSS1 VDD1 VSS1 VSS1
SHV
OUT
VREF
E
VSS1 VSS1 VSS1 VDD1
VDD1 VSS1 VSS1 VSS1
F
VSS1 VSS1 VSS1 VDD1
VDD1 VDD1 VSS1 VSS1
G
VSS1 VSS1 VSS1
H
MFIO MFIO
VPP1 VDD1
3
2
VDD1
UP
UP
UP
ADDR2 ADDR1 ADDR0
J
VPP1
MFIO MFIO
VDD1
5
4
VDD1
UP
UP
UP
ADDR5 ADDR4 ADDR3
K
MFIO MFIO VDD
VDD1
SHV
6
7
VDD1
UP
UP
UP
ADDR8 ADDR7 ADDR6
L
MFIO MFIO MFIO
VDD1
8
9
10
VDD1
UP
VDD
WRB
SHV
ADDR9
M
MFIO MFIO MFIO
VDD1
13
11
12
VDD1 OEB
N
MFIO MFIO VDD
VDD1
SHV
15
14
UP
UP
UP
VDD1
DATA2 DATA1 DATA0
P
MFIO MFIO MFIO
VDD1
16
18
17
VDD1
VDD
VSS1 VSS1
SHV
R
MFIO MFIO MFIO
VDD1
19
20
21
VDD1
UP
UP
UP
DATA5 DATA4 DATA3
T
MFIO MFIO MFIO
VDD1
23
22
24
VDD1
UP
VDD
VPP2
SHV
DATA6
U
MFIO MFIO VDD
VDD1
SHV
25
26
VDD1
UP
UP
VPP2
DATA8 DATA7
V
MFIO MFIO MFIO
VDD1
28
29
27
VDD1
UP
UP
UP
DATA11 DATA10 DATA9
W
MFIO MFIO MFIO
VDD1
30
31
32
VDD1
UP
UP
UP
DATA14 DATA13 DATA12
Y
MFIO
VSS1 VSS1 VDD1
33
UP
VDD
VSS1 VSS1
DATA15
SHV
AA
VSS1 VSS1 VSS1 VDD1
VDD1 VSS1 VSS1 VSS1
AB
VSS1 VSS1 VSS1 VDD1
VDD1 VDD1 VSS1 VSS1
AC
VSS1 VSS1 VDD1
AD
VSS1 VDD1 VSS1 VSS1
DPD DPD
VSS1 VDDA1 TX3
IREF CLKC
AE
VDD1 VSS1 VSS1 VSS1
DPD SYNC VDD
SHV
D
VREF
AF
VSS1 VSS1 VSS1 VSS1 VSS1
VDD
SHV
VDD
VSS1 VSS1 VSS1
SHV
RESET VDD
SHV
B
DPD
VSS1 VDD1 TX2
CLK
CEB
RDB
TX6 TX10 TX14 VDDS VSS1
DAC
TX25 TX29 TX33 TX37 VSS1 VDD1 VDD2 VSS1 VDD1 VSS1 VSS1
REFP
TX7
TX11 TX15 VDDS VSS1
VDD
DAC
VDD1 VSS2 VSS1 VSS1 VDD1 VSS1
TX24 TX28 TX32 TX36
SHV
REFN
TX12 TX16 VDDS TX19 TX21 TX23 TX27 TX31 TX35 TRSTB TDI
TX0
TX4
TX8
SYNC
VSSA1 TX1
DC
TX5
TX9 TX13 TX17 VSS1 TX18 TX20 TX22 TX26 TX30 TX34 TMS
TCK
INTERVSS1 VSS1 VSS1 VDD1
RUPT
TDO
= Baseband Input
= Transmit Output
= Feedback Input
= Microprocessor Interface
= Miscellaneous
= Multi-Function Input/Output
= Power and Biasing
= JTAG Interface
TEST
VSS1 VSS1 VSS1
MODE
P0077-01
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PIN FUNCTIONS
PIN
NAME
I/O
NO.
DESCRIPTION
MICROPROCESSOR INTERFACE
OEB
M3
I
Output enable
CEB
M2
I
Chip enable
RDB
M1
I
Read
WRB
L2
I
Write
UPADDR[9:0]
L1, K3, K2, K1, J3, J2, J1, H3, H2, H1
I
Microprocessor address
UPDATA[15:0]
Y1, W3, W2, W1, V3, V2, V1, U2, U1, T1, R3, R2, R1,
N3, N2, N1
I/O
Microprocessor data
INTERRUPT
AE5
O
Microprocessor interrupt
POWER AND BIASING
VDD1
B1, B26, C2, C10, C14, C19, C25, D3, D8, D14, D19,
D24, E4, E23, F3, F4, F23, H4, H23, J4, J23, K4, K23,
L4, L23, M4, M23, N4, N23, P4, P23, R4, R23, T4,
T23, U4, U23, V4, V23, W4, W23, Y23, AA4, AA23,
AB3, AB4, AB23, AC3, AC6, AC19, AC24, AD2, AD6,
AD25, AE1, AE26
PWR
1.2-V supply
VSS1
A1, A2, A3, A23, A24, A25, A26, B2, B3, B23, B24,
B25, C1, C3, C23, C24, C26, D1, D2, D4, D10, D23,
D25, D26, E1, E2, E3, E24, E25, E26, F1, F2, F24,
F25, F26, G1, G2, G3, G24, G25, G26, P1, P2, Y2,
Y3, Y24, Y25, AA1, AA2, AA3, AA24, AA25, AA26,
AB1, AB2, AB24, AB25, AB26, AC1, AC2, AC4, AC7,
AC13, AC20, AC25, AC26, AD1, AD3, AD4, AD13,
AD20, AD23, AD24, AD26, AE2, AE3, AE4, AE23,
AE24, AE25, AF1, AF2, AF3, AF14, AF22, AF23,
AF24, AF25, AF26
PWR
Ground
VDD2
AC5
NC
1.2-V monitor, no connect
VSS2
AD5
NC
GND monitor, no connect
VDDS
AC14, AD14, AE14
PWR
1.8-V supply
VDDSHV
A13, B13, C13, D13, G4, G23, K24, L3, N24, P3, T3,
U24, Y4, AC22, AD7, AE20
PWR
3.3-V supply
VDDA1
AD19
PWR
1.2-V supply (requires filtering)
VSSA1
AF20
PWR
Ground (requires filtering)
VDDA2
B10
PWR
1.2-V supply (requires filtering)
VSSA2
A10
PWR
Ground (requires filtering)
VPP1
H24, J26
PWR
1.2-V supply
VPP2
T2, U1
PWR
1.2-V supply
DPDIREF
AD22
PWR
DPD bias, 1 kΩ to VSS
DPDVREF
AE22
PWR
DPD bias to VDD1
DACREFP
AC12
PWR
DAC bias, 50 Ω to VSS
DACREFN
AD12
PWR
DAC bias, 50 Ω to VDDS
ADCIREF
C17
PWR
ADC bias, 1 kΩ to VSS
ADCVREF
D17
PWR
ADC bias to VDD1
BASEBAND INPUT
BB[15:0]
A8, D7, C7, B7, A7, D6, C6, B6, A6, D5, C5, B5, A5,
C4, B4, A4
I
Baseband input signal
BBCLK
C8
I
Baseband input clock
BBFR
B8
I
Baseband frame for sample and channel timing
MFIO[19:18]
R26, P24
I
LSBs for 18-bit baseband input signal [-2, -1]
MISCELLANEOUS
RESETB
AC23
I
Chip reset (active-low)
SYNCA
C9
I
Programmable general-purpose sync
14
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PIN FUNCTIONS (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
SYNCB
B9
I
Programmable general-purpose sync
SYNCC
A9
I
DPDl-purpose sync
SYNCD
AE21
I
Programmable general-purpose sync
SYNCDC
AF21
I
Complementary DPD-purpose sync
SYNCOUT
D9
O
Programmable general-purpose output sync
DPDCLK
AC21
I
Clock to DPD
DPDCLKC
AD21
I
Complementary clock to DPD
TESTMODE
AF4
I
Tie to ground
I
JTAG clock
JTAG INTERFACE
TCK
AF6
TDI
AE6
I
JTAG data in
TDO
AF5
O
JTAG data out
TRSTB
AE7
I
JTAG reset (active-low); pull down if JTAG is not used.
TMS
AF7
I
JTAG mode select
TX[37:0]
AC8, AD8, AE8, AF8, AC9, AD9, AE9, AF9, AC10,
AD10, AE10, AF10, AC11, AD11, AE11, AF11, AE12,
AF12, AE13, AF13, AF15, AE15, AD15, AC15, AF16,
AE16, AD16, AC16, AF17, AE17, AD17, AC17, AF18,
AE18, AD18, AC18, AF19, AE19
O
Transmit to DAC(s)
FB[35:0]
A11,
A15,
A18,
A21,
I
Feedback from ADC(s)
MFIO[33:0]
Y26, W24, W25, W26, V24, V25, V26, U25, U26, T24,
T25, T26, R24, R25, R26, P24, P25, P26, N25, N26,
M24, M25, M26, L24, L25, L26, K25, K26, J24, J25,
H25, H26, D22, C22
SIGNALS (See mode selection guide for pin assignment)
B11,
B15,
B18,
B21,
C11,
C15,
C18,
C21,
D11,
D15,
D18,
D21,
A12,
A16,
A19,
A22,
B12, C12, D12, A14, B14,
B16, C16, D16, A17, B17,
B19, A20, B20, C20, D20,
B22
I/O
MFIO
Special Power Supply Requirements for VDDA1, VSSA1, VDDA2, VSSA2
The two PLLs require a filtered supply. Each pair (VDDA1,VSSA1), (VDDA2,VSSA2) requires a separate filter.
These can be generated by filtering the core digital supply (VDD1). A representative filter is shown in Figure 8.
The filters should be located as close as reasonable to their respective pins (especially the bypass capacitors).
The ferrite beads should be series 50R (similar to Murata P/N: BLM31P500SPT; Description: IND FB
BLM31P500SPT 50R 1206). In particular, supply VDDA1 must be less than or equal to VDD1 when VDD1 is at
the low end of the required range. The series resistor assures this condition is met.
10 W
VDD1
VDDA1 or VDDA2
0.01 mF
1 mF
10 W
VSS1
VSSA1 or VSSA2
S0315-01
Figure 8. Recommended Filter for VDDA1, VDDA2 Power
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TX Output to DAC5682Z and DAC5688
Figure 4 and Figure 5 show the GC5322-to-DAC data, sync, and clock signals. Table 2 and Table 4 list the
specific GC5322-to-DAC TX connections.
Table 2. GC5322 TX Interface Options
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
GC5322 TX (Single-Channel Single-Ended HSTL – DAC5688 – 1.8-V CMOS)
DACI[15:0]
TX15, TX14, TX11, TX10, TX7, TX6, TX3, TX2, TX1, TX0,
TX4, TX5, TX8, TX9, TX12, TX13
O
DAC-I output
DACQ[15:0]
TX24, TX25, TX28, TX29, TX32, TX33, TX36, TX37, TX35,
TX34, TX31, TX30, TX27, TX26, TX23, TX22
O
DAC-Q output
DACCLK
TX21
O
Clock to DAC
DACCLKC
TX20
O
Complementary clock to DAC
DACSYNC
TX18
O
Output data sync (TX enable)
Table 3. GC5322 TX (Single-Channel Differential HSTL – DAC5682Z)
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
GC5322 TX (Differential HSTL) – DAC 5682Z – 1.2-V LVDS
DACI[15:0]P
TX10, TX6, TX2, TX0, TX4, TX8, TX12, TX16, TX23, TX27,
TX31, TX35, TX32, TX36, TX29, TX25
O
DAC positive output
DACQ[15:0]N
TX11, TX7, TX3, TX1, TX5, TX9, TX13, TX17, TX22, TX26,
TX30, TX34, TX33, TX37, TX28, TX24
O
DAC negative output
DACCLK
TX21
O
Clock to DAC
DACCLKC
TX20
O
Complementary clock to DAC
DACSYNCP
TX14
O
Positive output data sync
DACSYNCN
TX15
O
Negative output data sync
FB Input From LVDS ADC
There are several different ADC formats; these are formed from the possible combinations of DDR and SDR
clocking modes with positive-clock-edge even bits and positive-clock-edge odd bits. Figure 6 shows the
DDR-ADC data, and clock signals to the GC5322. Table 4 and Table 5 list the specific ADC to GC5322 FB
connections. There are two feedback (FB) ports, A and B. Port A has faster timing and is preferred. There are
several ADC styles:
• LVDS DDR – ADS5545 (ADS61x9, ADS5517); ADS5463 (1)
• LVDS DDR – ADS62C17 – reversed data alignment (same connections as ADS5545)
• LVDS SDR – ADS5544
(1) Clock aligns with data.
ADCs are typically connected to the GC5322 so the MSB of the ADC is connected to FB Port A MSB. The lower
bit numbers follow until the ADC bits are all connected. Any remaining lower-order bits on the FB port should be
terminated with a P connection to a series resistor to GND, N connection to a series resistor to 1.8 V as a
logic 0. See the GC5325SEK schematic (reference 2 in the References section) for an example.
NOTE
There are special connections for shared-feedback ADCs between GC5322s. The
ADS6149 to GC5325 or GC5322 Shared Feedback Interface application guide, available
as a PDF file from a TI field application engineer, describes the special connections and
routing.
Table 4. Single LVDS SDR ADC to FB Ports A and B
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
Feedback (Single-Channel SDR LVDS or DDR LVDS)
16
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Table 4. Single LVDS SDR ADC to FB Ports A and B (continued)
PIN FUNCTION
I/O
DESCRIPTION
ADC[15:0]P
FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16, FB20,
FB22, FB24, FB26, FB28, FB30, FB32, FB34
PIN NAME
I
ADC positive feedback from PA output
ADC[15:0]N
FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17, FB21,
FB23, FB25, FB27, FB29, FB31, FB33, FB35
I
ADC negative feedback from PA output
ADCCLK
FB0
I
Clock from ADC
ADCLKC
FB1
I
Complementary clock from ADC
Table 5. Single LVDS DDR ADC
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
To FB Port A (Preferred)
ADCA[7:0]P
FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16
I
ADC-A positive feedback from PA output
ADCA[7:0]N
FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17
I
ADC-A negative feedback from PA output
ADCACLK
FB0
I
Clock from ADC-A
ADCACLKC
FB1
I
Complementary clock from ADC-A
ADCB[7:0]P
FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34
I
ADC-B positive feedback from PA output
ADCB[7:0]N
FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35
I
ADC-B negative feedback from PA output
ADCBCLK
FB18
I
Clock from ADC-B
ADCBCLKC
FB19
I
Complementary clock from ADC-B
To FB Port B
Envelope Output
The GC5322 has a magnitude output and magnitude clock that can be delayed to align with the TX output after
DPD. The envelope output is transmitted at the DPD clock rate / 2.
Table 6. Envelope Output
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
Envelope (Single-Ended 3.3-V CMOS)
ENV[14:0]
MFIO33, MFIO32, MFIO28, MFIO27, MFIO26, MFIO25,
MFIO17, MFIO16, MFIO15, MFIO14, MFIO9, MFIO8,
MFIO7, MFIO6, MFIO3
O
Magnitude of the CFR output signal
ENVCLK
MFIO1
O
Clock to envelope modulator
MPU Interface Guidelines
This section describes the hardware interface between the recommended microprocessor and the GC5322.
Users may select a microprocessor that meets their specific system requirements. Although the hardware can
support multiple options, the recommended TMS320C6727 DSP is also fully supported with host control and
adaptation software. Figure 7 and Figure 9 illustrate the hardware interface from the DSP to GC5322 and
SDRAM. The external memory is required to accommodate the computational efforts of the adaptation algorithm.
Reference to the SDRAM used is a 64-Mb/PC133; there are two memory devices for 32-bit SDRAM memory.
The DSP timing is adjusted for the SDRAM; an example is Samsung K4S641632H-TC(L)75.
The use of an external inverter, with minimal propagation delay, is required for OEB of the GC5322; this device is
necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in
the Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP External
Memory Interface (EMIF) user's guide (SPRU711).
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TMS320C6727
GC532x
DATA BUS
EM_D[15.0]
UPDATA[15.0]
ADDR.BUS
EM_A[8.0]
UPADDR[9.1]
EM_BA[1]
UPADDR[0]
CNTL.BUS
HD[22.20]
EM_CS2
Multi-Device
Select Logic
EM_RWB
Invert
To Other
GC532x
CEB
OEB
EM_OEB
EM_WEB
RDB
WRB
Customer Logic Power Supply OK
RESETB
B0377-01
Figure 9. DSP to GC5322/SDRAM Interface Specifications
In a typical implementation, the system configuration software resides locally (in nonvolatile memory) to ensure
proper operation at power up. The size of the software required to support the GC5322 and 'C6727 should be no
more than 128 Mb (16 MB); however, this allocation is subject to change pending algorithm improvements. The
suggested host-to-DSP interface is through the UHPI port. See reference 4 in the References section. The
SDRAM used is a 64-Mb / PC133 SDRAM. There are two SDRAM devices for a 32-bit memory.
The port can be configured into multiple modes of data transfer; the Multiplexed Host Address/Data Dual
Halfword Mode is suggested for this application.
Additional specifications and documents for the TMS320C6727 DSP are available from Texas Instruments at:
http://focus.ti.com/docs/prod/folders/print/tms320c6727b.html.
GENERAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
VDD, VDDA
Core supply voltage
VDDS
Digital supply voltage for TX
VDDSHV
Digital supply voltage
VIN
Input voltage (under/overshoot)
Tstg
VALUE
UNIT
–0.3 to 1.32
V
–0.3 to 2
V
–0.3 to 3.6
V
–0.5 to VDDSHV+ 0.5
V
Clamp current for an input/output
–20 to 20
mA
Storage temperature
–65 to 150
°C
1
week
±100
mA
ESD classification Class 2 (Required 2-kV HBM, 500-V CDM) (Passed 2.5-kV
HBM, 500-V CDM, 200-V MM)
Moisture sensitivity Class 3 (floor life at 30°C/60% H)
Latchup
18
JEDEC Level 2 per JEDEC 78 standard (at 90°C and 1.5 × Vmax)
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
1.14
1.2
1.26
V
VDD, VDDA2, VPP
Core supply voltages.
Note VDDA2 ≤ VDD
VDDA1
Analog supply for DPD PLL
1
1.1
VDD
V
VDDS
Digital supply voltage for TX
1.71
1.8
1.89
V
VDDSHV
Digital supply voltage
3.15
3.3
3.45
V
3
A
0.25
A
See (1)
IDD, IDDA1, IDDA2, Combined supply current for Vdd, Vdda1,
IPP
Vdda2, and VPP
IDDS
Digital supply current for TX
IDDSHV
Digital supply current
TC
Case temperature
See (2)
TJ
Junction temperature
See (3)
(1)
(2)
(3)
–40
30
0.3
A
85
°C
105
°C
VDDA1 must be less than VDD1 when VDD is low. See recommended filtering circuit in Figure 8. Maximum observed current on
VDDA1 is 8 mA.
Chip specifications are production tested to 90°C case temperature. QA tests are performed at 85°C.
Thermal management may be required for full-rate operation. Sustained operation at elevated temperatures reduces long-term reliability.
Lifetime calculations are based on a maximum junction temperature of 105°C.
THERMAL INFORMATION
GC5322
THERMAL METRIC
(1)
ZND
UNIT
352 PINS
Junction-to-ambient thermal resistance (2)
qJA
(3)
qJCtop
Junction-to-case (top) thermal resistance
qJB
Junction-to-board thermal resistance (4)
yJT
Junction-to-top characterization parameter (5)
yJB
Junction-to-board characterization parameter (6)
qJCbot
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Junction-to-case (bottom) thermal resistance
(7)
19
°C/W
0.8
°C/W
9
°C/W
0.5
°C/W
8
°C/W
N/A
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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GENERAL ELECTRICAL CHARACTERISTICS
Describes the electrical characteristics for the baseband interface, multifunction I/O (MFIO), DPD clock and fast sync, MPU
and JTAG interfaces over recommended operating conditions. Device is production tested at 90°C for the given specification
and characterized at –40°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS INTERFACE
VIL
CMOS voltage input, low
VIH
CMOS voltage input, high
0.8
V
2
VDDSHV
V
VOL
CMOS voltage output, low
IOL = 2 mA
VOH
CMOS voltage output, high
0.5
V
IOH = –2 mA
2.4
VDDSHV
|IPU|
V
Pullup current
VIN = 0 V
40
200
mA
|IIN|
Leakage current
VIN = 0 or VIN = VDDSHV
5
mA
100
DAC INTERFACE (DACP/N[15:0])
Vo(diff)
Output differential swing
| VOD | = | VOH – VOL | (1)
Vcomm
Common mode
(VOH + VOL) / 2 (1)
250
mV
1000
mV
LVDS INTERFACE (FB[35:0], DPDCLK/C, SYNCD/C)
VI
Input voltage range
VI(diff)
Input differential voltage,
|Vpos – Vneg|
RIN
Input differential impedance
0
0 < Vi < 2000 mV
1000 mV < VI < 1400 mV, FB[35:0] only
2000
250
mV
90
80
mV
120
Ω
2.2
A
POWER SUPPLY
Idyn
(1)
(2)
20
Core current
See (2)
HSTL output levels measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360. Contact TI for operations
above 675 Mb/s.
Operating at 280 MHz core, TX 840 MHz, maximum filtering, nominal supplies
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GENERAL SWITCHING CHARACTERISTICS
Describes the electrical characteristics for the baseband interface, MFIO[19:18], Sync A, B, C, and BB clock over
recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
GPP is ACTIVE.
25
93.3
GPP is BYPASSED.
25
140
UNIT
BASEBAND INTERFACE
fCLK(BB)
Baseband input clock frequency
tsu(BB)
Input data setup time before BBCLK↑
BB[15:0], BBFR, SYNCA, SYNCB, and
SYNCC; MFIO18/19
1.3
ns
th(BB)
Input data hold time after BBCLK↑
BB[15:0], BBFR, MFIO18/19
1.5
ns
th(SYNCA, -B, -C)
Input data hold time after BBCLK↑
SYNCA, SYNCB, and SYNCC
DutyCLK(BB)
Duty cycle
2
30%
MHz
ns
70%
1/fCLK(BB)
BBCLK
BB[15:0]
tsu(BB)
I(ch = 1, t = 1)
Q(ch = 1, t = 1)
Q(ch = N, t = 1)
I(ch = 1, t = 2)
th(BB)
BBFR
T0284-01
Figure 10. Baseband Timing Specifications (ex. Four Interleaved I/Q Channels)
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DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS
MIN
MAX
UNIT
fCLK(DPD)
DPD input clock frequency
PARAMETER
TEST CONDITIONS
100
280
MHz
DutyCLK(DPD)
DPD input clock duty cycle
30%
70%
th(SYNCD)
Input hold time after DPDCLK↑
0.2
ns
tsu(SYNCD)
Input setup time after DPDCLK↑
0.4
ns
th(SYNCA, -B, -C)
Input hold time after DPDCLK↑
2
ns
tsu(SYNCA, -B, -C)
Input setup time after DPDCLK↑
0.4
ns
tjCLK(DPD)
DPD output clock cycle-to-cycle jitter
–2.5%
2.5%
DPDCLK
DPDCLKC
SYNCDC
SYNCD
tsu(SYNCD)
th(SYNCD)
SYNCA
SYNCB
SYNCC
tsu(SYNCA, -B, -C)
th(SYNCA, -B, -C)
T0286-01
Figure 11. DPD Clock and Fast Sync Timing Specifications
22
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MPU SWITCHING CHARACTERISTICS (READ)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tsu(AD)
ADDR setup time to RDB↓
WRB is HIGH.
5
ns
tsu(CEB)
CEB setup time to RDB↓
WRB is HIGH.
7
ns
tsu(OEB)
OEB setup time to RDB↓
WRB is HIGH.
2
ns
td(RD)
DATA valid time after RDB↓
WRB is HIGH.
th(RD)
ADDR hold time to RDB↑
WRB is HIGH.
OEB, CEB hold time to RDB↑
tHIGH(RD)
Time RDB must remain HIGH between READs.
WRB is HIGH (1).
tZ(RD)
DATA goes high-impedance after OEB↑ or RDB↑.
WRB is HIGH (1).
(1)
14
2
ns
ns
0
7
ns
7
ns
These values are obtained from testing during characterization.
RDB
tHIGH(RD)
WRB
th(OEB)
tsu(OEB)
OEB
tsu(CEB)
CEB
tsu(AD)
ADDR
DATA
3-State
td(RD)
tZ(RD)
th(RD)
T0287-01
Figure 12. MPU READ Timing Specifications
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MPU SWITCHING CHARACTERISTICS (WRITE)
PARAMETER
TEST CONDITIONS
DATA and ADDR setup time to WRB↓
tsu(WR)
MAX
UNIT
5
CEB setup time to WRB↓
OEB and RDB are HIGH.
OEB setup time to WRB↓
7
ns
2
DATA and ADDR hold time after WRB↑
th(WR)
MIN
OEB and RDB are HIGH.
OEB and CEB hold time after WRB↑
2
ns
0
tlow(WR)
Time WRB and CEB must remain simultaneously LOW
OEB and RDB are HIGH.
15
ns
thigh(WR)
Time CEB or WRB must remain HIGH between WRITEs.
OEB and RDB are HIGH.
10
ns
RDB
tlow(WR)
thigh(WR)
WRB
OEB
th(WR)
tsu(WR)
CEB
ADDR
DATA
T0288-01
Figure 13. MPU WRITE Timing Specifications
24
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JTAG SWITCHING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
50
MHz
fTCK
JTAG clock frequency
tp(TCKL)
JTAG clock low period
10
ns
tp(TCKH)
JTAG clock high period
10
ns
tsu(TDI)
Input data setup time before TCK↑
Valid for TDI and TMS
1
ns
th(TDI)
Input data hold time after TCK↑
Valid for TDI and TMS
6
td(TDO)
Output data delay from TCK↓
ns
8
ns
1/fTCK
TCK
tp(TCKH)
tp(TCKL)
TDI
tsu(TDI)
th(TDI)
TDO
td(TDO)
T0289-01
Figure 14. JTAG Timing Specifications
DIFFERENTIAL HSTL SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
420
MHz
TBD
ps
HSTL MODE – DDR ex. DAC5682
fCLK(DAC)
DAC output clock frequency
RL= 100 Ω (1)
tSKW(DAC)
DACCLK to DACData
RL= 100 Ω
(1)
DDR interface; DAC clock is 1/2 DAC data rate.
1/fCLK(DAC)
DACCLKC
DACCLK
DAC[15:0]P
I
Q
I
DAC[15:0]N
tSKW(DAC)
T0290-01
Figure 15. TX Timing Specifications (HSTL – DDR)
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SINGLE-ENDED HSTL SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HSTL MODE – SDR ex. DAC5688
fCLK(DAC)
DAC output clock frequency
2-mA load (1)
200
MHz
td
DACCLK-to-DACData delay time
2-mA load (2)
1.5
ns
tho
DACCLK-to-DACData hold time
2-mA load (2)
(1)
(2)
1.5
ns
Because the output clock is SDR, the positive edge of the clock is used to register the data at the DAC receiver. The clock rate is limited
to 200 MHz.
td and tho clock-to-data is measured during characterization.
DACCLKC
DACCLK
DAC[15:0]
I or Q
tho
td
T0448-01
Figure 16. TX Timing Specifications (HSTL – SDR)
ENVELOPE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MFIO CMOS – SDR to Envelope Modulator
fCLK(ENV)
ENVELOPE data output clock frequency
2-mA load (1)
140
MHz
td
ENVCLK-to-ENVData delay time
2-mA load (2)
1.5
ns
tho
ENVCLK-to-ENVData hold time
2-mA load (2)
(1)
(2)
1.5
ns
Envelope output is magnitude; this is a real output at a DPDClk/2 (140-MHz) rate.
td and tho clock-to-data is measured during characterization.
ENVCLK
ENVDATA[15:0]
tho
td
T0449-01
Figure 17. Envelope Timing (MFIO-CMOS 3.3 V)
26
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LVDS SWITCHING CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM.
N means the number of differential pairs used to transmit data from one ADC and M means the number of bits sent serially
down each LVDS pair. Thus, 8x2 means 8 LVDS pairs each containing 2 bits of information sent serially.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
280
MHz
16 × 1 SDR LVDS MODE ex. ADS5444
fCLK(ADC)
ADC interface clock frequency
See (1)
tsu(ADC[#]P)
Input data setup time before CLK↑
See (1) (2)
300
ps
(1) (2)
600
ps
th(ADC[#]P)
Input data hold time after CLK↑
See
16 × 1 DDR LVDS MODE ex. ADS5463
fCLK(ADC)
See (1)
ADC interface clock frequency
140
MHz
(1) (2)
100
ps
1200
ps
tsu(ADC[#]P)
Input data setup time before CLK↑↓
See
th(ADC[#]P)
Input data hold time after CLK↑↓
See (1) (2)
8 × 2 DDR LVDS MODE ex. ADS5545, ADS6149
fCLK(ADCA)
See (1)
ADCA interface clock frequency
280
(1) (3)
MHz
tsu(ADCA[#/2]P)
Input data setup time before CLK↑↓
See
. For port A
430
th(ADCA[#/2]P)
Input data hold time after CLK↑↓
See (1) (3). For port A
260
fCLK(ADCB)
ADCB interface clock frequency
See (1)
tsu(ADCB[#/2]P)
Input data setup time before CLK↑↓
See (1) (4). For port B
800
ps
th(ADCB[#/2]P)
Input data hold time after CLK↑↓
See (1) (4). For port B
400
ps
(1)
(2)
(3)
(4)
ps
ps
280
MHz
Specifications are limited by GC5322 performance and may exceed the example ADC capabilities for the given interface.
Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (VOD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing
(VOD = 0).
Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (VOD > 250 mV) to/from ADCACLK and ADCACLKC clock crossing
(VOD = 0).
Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (VOD > 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing
(VOD = 0).
1/fCLK(ADC)
CLK
CLKC
ADC[15:0]P
ADC[15:0]N
tsu(ADC[#]P)
th(ADC[#]P)
T0291-01
Figure 18. LVDS Timing Specifications (16 × 1 SDR LVDS)
1/fCLK(ADC)
CLK
CLKC
tsu(ADC[#]P)
ADC[15:0]P
ADC[15:0]N
th(ADC[#]P)
T0292-01
Figure 19. LVDS Timing Specifications (16 × 1 DDR LVDS)
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1/fCLK(ADCx)
CLK
CLKC
ADC[# bits/2]P
Even Bits
Odd Bits
Even Bits
Odd Bits
ADC[# bits/2]N
tsu(ADCx[#/2]P)
th(ADCx[#/2]P)
t=N
t=N+1
T0293-01
Figure 20. LVDS Timing Specifications (8 × 2 DDR LVDS)
GLOSSARY OF TERMS
3G
Third generation (refers to next-generation wideband cellular systems that use CDMA)
3GPP
Third generation partnership project (W-CDMA specification,www.3gpp.org)
3GPP2
Third generation partnership project 2 (cdma2000 specification,www.3gpp2.org)
ACLR
Adjacent channel leakage ratio (measure of out-of-band energy from one CDMA carrier)
ACPR
Adjacent channel power ratio
ADC
Analog-to-digital converter
BW
Bandwidth
CCDF
Complementary cumulative distribution function
CDMA
Code division multiple access (spread spectrum)
CEVM
Composite error vector magnitude
CFR
Crest factor reduction
CMOS
Complementary metal oxide semiconductor
DAC
Digital-to-analog converter
dB
Decibels
dBm
Decibels relative to 1 mW (30 dBm = 1 W)
DDR
Dual data rate (ADC output format)
DSP
Digital signal processing or digital signal processor
DUC
Digital upconverter (usually provides the GC5322 input)
EVM
Error vector magnitude
FIR
Finite impulse response (type of digital filter)
I/Q
In-phase and quadrature (signal representation)
IF
Intermediate frequency
IIR
Infinite impulse response (type of digital filter)
JTAG
Joint Test Action Group (chip debug and test standard 1149.1)
LO
Local oscillator
LSB
Least-significant bit
Mb
Megabits (divide by 8 for megabytes MB)
28
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SLWS206D – FEBRUARY 2008 – REVISED NOVEMBER 2010
MSB
Most-significant bit
MSPS
Megasamples per second (1×106 samples/s)
PA
Power amplifier
PAR
Peak-to-average ratio
PCDE
Peak code domain error
PDC
Peak detection and cancellation (stage)
PDF
Probability density function
RF
Radio frequency
RMS
Root mean square (method to quantify error)
SDR
Single data rate (ADC output format)
SEM
Spectrum emission mask
SNR
Signal-to-noise ratio (usually measured in dB or dBm)
UMTS
Universal mobile telephone service
W-CDMA
Wideband code division multiple access (synonymous with 3GPP)
WiBro
Wireless broadband (Korean initiative IEEE 802.16e)
WiMAX
Worldwide Interoperability of Microwave Access (IEEE 802.16e)
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29
GC5322
SLWS206D – FEBRUARY 2008 – REVISED NOVEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (February 2008) to Revision A
•
Page
Updated the LVDS INTERFACE section of the General Electrical Characteristics ........................................................... 20
Changes from Revision A (August 2008) to Revision B
Page
•
Changed Changed ADS5444 18-bit to ADS6149 14-bit ....................................................................................................... 4
•
Deleted Deleted Related Material and Documents section ................................................................................................ 12
•
Deleted Deleted paragraph "For systems that......implementation". Also deleted Figure 3. DSP to ....Interface ............... 18
•
Changed Changed from HSTL interface (TX[37:0] ) to DAC interface (DACP/N [15:0]) ................................................... 20
•
Changed changed the first 2 rows and deleted 5 rows from this subsection in the table .................................................. 20
•
Changed Deleted note 1 and changed note 2, original 3 notes ......................................................................................... 20
•
Deleted Deleted last row of the TX Switching table and added note 2 .............................................................................. 25
•
Changed Changed from 800 to 430 ................................................................................................................................... 27
•
Changed Changed from 400 to 260 ................................................................................................................................... 27
Changes from Revision B (December 2008) to Revision C
Page
Changes from Revision C (February 2009) to Revision D
Page
•
Changed the FEATURES list ................................................................................................................................................ 1
•
Changed the APPLICATIONS list ......................................................................................................................................... 1
•
Revised the system block diagram ....................................................................................................................................... 1
•
Rewrote DESCRIPTION section .......................................................................................................................................... 1
•
Added Created Description (Continued), so description paragraphs would fall below the ESDS statement on second
page ...................................................................................................................................................................................... 2
•
Revised the functional block diagram ................................................................................................................................... 3
•
Added the REFERENCES section ....................................................................................................................................... 3
•
Deleted "to 30 dB" ................................................................................................................................................................ 4
•
Added an 800-MSPS DAC ................................................................................................................................................... 4
•
Added a CDCE72010 clock generator .................................................................................................................................. 4
•
Added "ADC" ........................................................................................................................................................................ 4
•
Changed second sentence of System Arhitecture section ................................................................................................... 5
•
Deleted last row of System Architecture table ...................................................................................................................... 5
•
Deleted the Dual Antenna, GC5322, Shared Feedback figure ............................................................................................ 6
•
Revised text in Baseband Interface paragraph; added Figure 3 .......................................................................................... 6
•
Inserted new BB Clock Input section .................................................................................................................................... 7
•
Revised text in Gain/Pilot Insertion/AntCal Insertion/Power Meter paragraph ..................................................................... 7
•
Revised the Digital Upconverters (DUCs) section ................................................................................................................ 7
•
Revised the Crest Factor Reduction (CFR) section ............................................................................................................. 8
•
Replaced text of Fractional Farrow Resampler (FR) section ................................................................................................ 8
•
Revised the Digital Predistortion (DPD) section ................................................................................................................... 8
•
Inserted new DPD Clock Input section ................................................................................................................................. 8
•
Inserted new SyncD – DPD Clocked Sync Input section ..................................................................................................... 8
•
Revised text paragraph of Bulk Upconverter (BUC) section ................................................................................................ 8
•
Deleted "DPD clock /2 the" ................................................................................................................................................... 8
30
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SLWS206D – FEBRUARY 2008 – REVISED NOVEMBER 2010
•
Inserted new Output Formatter and DAC Interface (OFMT) section .................................................................................... 8
•
Removed last bullet from OFMT list ..................................................................................................................................... 9
•
Deleted GC5322 to Dual DAC5688 (Interleaved IQ) Interface illustration ........................................................................... 9
•
Replaced all text of Feedback Path (FB) section and added an illustration ....................................................................... 10
•
Changed section title from Smart Capture Buffers (SCB) section to Capture Buffers (CB) ............................................... 11
•
Deleted existing paragraph; inserted two new paragraphs and four notes ........................................................................ 11
•
Revised title and first paragraph of the Input Syncs and Output Sync section; deleted a bullet from the list, and
added a note ....................................................................................................................................................................... 12
•
Changed title and replaced all text of Power Meters and Peak I-or-Q Monitors section .................................................... 12
•
Changed names of some pins in the pinout diagram ......................................................................................................... 13
•
Changed package from GND to ZND on pinout drawing ................................................................................................... 13
•
Made changes to Terminal Functions table in the areas of UPDATA, VSS1, VDD2, VSS2, RESETB, SYNCD,
SYNCDC, SYNCOUT, and MFIO ....................................................................................................................................... 14
•
Made changes to Terminal Functions table in the areas of UPDATA, VSS1, VDD2, VSS2, RESETB, SYNCD,
SYNCDC, SYNCOUT, and MFIO ....................................................................................................................................... 15
•
Added title for Special Power Supply Requirements for VDDA1, VSSA1, VDDA2, VSSA2 section .................................. 15
•
Inserted one sentence in this paragraph and revised another ........................................................................................... 15
•
Changed analog supply to filtered supply ........................................................................................................................... 15
•
Changed caption of Figure 8 and moved figure to the end of the section ......................................................................... 15
•
Added title and introductory paragraph to TX Output to DAC5682Z and DAC5688 section; major overhaul of Table 2
and Table 4 ......................................................................................................................................................................... 16
•
Changed to new figure reference as a result of deleted illustration ................................................................................... 16
•
Deleted Single- or Dual-Channel DDR LVDS section of table ........................................................................................... 16
•
Added new FB Input From LVDS ADC section .................................................................................................................. 16
•
Added new Envelope Output section .................................................................................................................................. 17
•
Revised the MPU Interface Guidelines section .................................................................................................................. 17
•
Replaced Figure 9 graphic .................................................................................................................................................. 18
•
Deleted sentence: "The adaptation algorithm..." ................................................................................................................ 18
•
Deleted Typical Baseband Interface section ...................................................................................................................... 18
•
Changed fCLK(ENV) MAX value to 140 MHz .......................................................................................................................... 26
•
Changed the LVDS 16 × 1 DDR timing digram .................................................................................................................. 27
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31
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
GC5322IZND
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
BGA
ZND
352
40
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
GC5322IZND
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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