Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
ISO5852S-EP High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver
With Split Outputs and Active Protection Features
1 Features
3 Description
•
The ISO5852S-EP device is a 5.7-kVRMS, reinforced
isolated gate driver for IGBTs and MOSFETs with
split outputs, OUTH and OUTL, providing 2.5-A
source and 5-A sink current. The input side operates
from a single 2.25-V to 5.5-V supply. The output side
allows for a supply range from minimum 15-V to
maximum 30-V. Two complementary CMOS inputs
control the output state of the gate driver. The short
propagation time of 76 ns provides accurate control
of the output stage.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
100-kV/μs Minimum Common-Mode Transient
Immunity (CMTI) at VCM = 1500 V
Split Outputs to Provide 2.5-A Peak Source and
5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Soft Turn-Off (STO) during Short Circuit
Fault Alarm upon Desaturation Detection is
Signaled on FLT and Reset Through RST
Input and Output Undervoltage Lockout (UVLO)
with Ready (RDY) Pin Indication
Active Output Pulldown and Default Low Outputs
with Low Supply or Floating Inputs
2.25-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients
Shorter Than 20 ns
Operating Temperature: –55°C to +125°C
Ambient
Surge Immunity 12800-VPK (according to IEC
61000-4-5)
Safety-Related Certifications:
– 8000-VPK VIOTM and 2121-VPK VIORM
Reinforced Isolation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
– 5700-VRMS Isolation for 1 Minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1, IEC 60601-1 and IEC 61010-1 End
Equipment Standards
– CQC Certification per GB4943.1-2011
– All Certifications Complete per UL, VDE, CQC,
TUV and Planned for CSA
An internal desaturation (DESAT) fault detection
recognizes when the IGBT is in an overcurrent
condition. Upon a DESAT detect, a mute logic
immediately blocks the output of the isolator and
initiates a soft-turnoff procedure which disables the
OUTH pin and pulls the OUTL pin to low over a time
span of 2 μs. When the OUTL pin reaches 2 V with
respect to the most-negative supply potential, VEE2,
the gate-driver output is pulled hard to the VEE2
potential which turns the IGBT immediately off.
When desaturation is active, a fault signal is sent
across the isolation barrier pulling the FLT output at
the input side low and blocking the isolator input.
Mute logic is activated through the soft-turnoff period.
The FLT output condition is latched and can be reset
only after the RDY pin goes high, through a lowactive pulse at the RST input.
Device Information(1)
PART NUMBER
ISO5852S-EP
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
IN±
Mute
9V
IN+
GND2
VCC2
VCC1
2 Applications
•
Isolated IGBT and MOSFET Drives in
– Industrial Motor Control Drives
– Industrial Power Supplies
– Solar Inverters
– HEV and EV Power Modules
– Induction Heating
RDY
Gate Drive
Ready
OUTH
and
Encoder
Logic
STO
VCC1
FLT
Q
S
Q
R
VCC1
OUTL
Decoder
2V
Fault
CLAMP
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Function ...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
9
9.1
9.2
9.3
9.4
1
1
1
2
3
4
5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
23
23
24
25
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Applications .............................................. 26
11 Power Supply Recommendations ..................... 36
12 Layout................................................................... 36
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety Limiting Values .............................................. 8
Safety-Related Certifications..................................... 8
Electrical Characteristics........................................... 9
Switching Characteristics ...................................... 10
Insulation Characteristics Curves ......................... 11
Typical Characteristics .......................................... 12
12.1 Layout Guidelines ................................................. 36
12.2 PCB Material ......................................................... 36
12.3 Layout Example .................................................... 36
13 Device and Documentation Support ................. 37
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
14 Mechanical, Packaging, and Orderable
Information ........................................................... 37
Parameter Measurement Information ................ 19
Detailed Description ............................................ 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2016
*
Initial release.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
5 Description (continued)
When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to
VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a
low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits
monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low,
otherwise this output is high.
The ISO5852S-EP device is available in a 16-pin SOIC package. Device operation is specified over a
temperature range from –55°C to +125°C ambient.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
3
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
6 Pin Configuration and Function
DW Package
16-Pin SOIC
Top View
VEE2
1
16
GND1
DESAT
2
15
VCC1
GND2
3
14
RST
OUTH
4
13
FLT
VCC2
5
12
RDY
OUTL
6
11
IN±
CLAMP
7
10
IN+
VEE2
8
9
GND1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CLAMP
7
O
Miller clamp output
DESAT
2
I
Desaturation voltage input
FLT
13
O
Fault output, active-low during DESAT condition
—
Input ground
GND1
9
16
GND2
3
—
Gate drive common. Connect to IGBT emitter.
IN+
10
I
Non-inverting gate drive voltage control input
IN–
11
I
Inverting gate drive voltage control input
OUTH
4
O
Positive gate drive voltage output
OUTL
6
O
Negative gate drive voltage output
RDY
12
O
Power-good output, active high when both supplies are good.
RST
14
I
Reset input, apply a low pulse to reset fault latch.
VCC1
15
—
Positive input supply (2.25-V to 5.5-V)
VCC2
5
—
Most positive output supply potential.
—
Output negative supply. Connect to GND2 for unipolar supply application.
VEE2
4
1
8
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
GND1 – 0.3
6
V
–0.3
35
V
–17.5
0.3
V
–0.3
35
V
Positive gate-driver output voltage
VEE2 – 0.3
VCC2 + 0.3
V
Negative gate-driver output voltage
VEE2 – 0.3
VCC2 + 0.3
V
2.7
A
5.5
A
GND1 – 0.3
VCC1 + 0.3
V
10
mA
GND2 – 0.3
VCC2 + 0.3
V
VEE2 – 0.3
VCC2 + 0.3
V
VCC1
Supply-voltage input side
VCC2
Positive supply-voltage output side
(VCC2 – GND2)
VEE2
Negative supply-voltage output side
(VEE2 – GND2)
V(SUP2)
Total-supply output voltage
(VCC2 - VEE2)
V(OUTH)
V(OUTL)
I(OUTH)
Gate-driver high output current
Maximum pulse width = 10 μs, Maximum
duty cycle = 0.2%)
I(OUTL)
Gate-driver low output current
Maximum pulse width = 10 μs, Maximum
duty cycle = 0.2%)
V(LIP)
Voltage at IN+, IN–,FLT, RDY, RST
I(LOP)
Output current of FLT, RDY
V(DESAT)
Voltage at DESAT
V(CLAMP)
Clamp voltage
TJ
Junction temperature
–55
150
°C
TSTG
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC1
Supply-voltage input side
2.25
5.5
V
VCC2
Positive supply-voltage output side (VCC2 – GND2)
15
30
V
V(EE2)
Negative supply-voltage output side (VEE2 – GND2)
–15
0
V
V(SUP2)
Total supply-voltage output side (VCC2 – VEE2)
15
30
V
V(IH)
High-level input voltage (IN+, IN–, RST)
0.7 × VCC1
VCC1
V
V(IL)
Low-level input voltage (IN+, IN–, RST)
0
0.3 × VCC1
tUI
Pulse width at IN+, IN– for full output (CLOAD = 1 nF)
tRST
Pulse width at RST for resetting fault latch
800
TA
Ambient temperature
–55
40
ns
125
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
V
ns
°C
5
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
7.4 Thermal Information
ISO5852S-EP
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
99.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.5
°C/W
RθJB
Junction-to-board thermal resistance
56.5
°C/W
ψJT
Junction-to-top characterization parameter
29.2
°C/W
ψJB
Junction-to-board characterization parameter
56.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
Full-chip power dissipation is derated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a
maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient
temperature and board design, while ensuring that the junction temperature does not exceed 150°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Maximum power dissipation (both sides)
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C
1255
mW
PD(I)
Maximum input power dissipation
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C
175
mW
PD(O)
Maximum output power dissipation
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C
1080
mW
6
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
External clearance (1)
Shortest terminal-to-terminal distance through air
8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
21
µm
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; Material
Group I according to IEC 60664-1; UL 746A
600
V
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
CLR
CTI
Material group
I
Overvoltage Category
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
VIOWM
(2)
Maximum repetitive peak isolation voltage AC voltage (bipolar)
Maximum isolation working voltage
2121
VPK
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test, see Figure 1
1500
VRMS
DC voltage
2121
VDC
8000
VPK
8000
VPK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM; t = 60 s (qualification); t = 1 s (100%
production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Isolation resistance, input to output (5)
RIO
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK ,
tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK ,
tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875× VIORM = 3977 VPK ,
tm = 10 s
≤5
VIO = 0.4 sin (2πft), f = 1 MHz
pC
1
pF
VIO = 500 V, TA = 25°C
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 1011
Ω
9
VIO = 500 V at TS = 150°C
> 10
Pollution degree
2
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
7
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
7.7 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 99.6°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see Figure 2
456
RθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 2
346
RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 2
228
RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C,
see Figure 2
84
RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C,
see Figure 2
42
RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C, see Figure 3
255 (1)
150
UNIT
mA
mW
°C
Input, output, or the sum of input and output power should not exceed this value.
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
7.8 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to DIN V
VDE V 0884-10
(VDE V 0884-10):2006-12
and DIN EN 61010-1 (VDE
0411-1):2011-07
Plan to certify under CSA
Recognized under UL 1577
Component Acceptance
Component Recognition
Notice 5A, IEC 60950-1, and Program
IEC 60601-1
Certified according to
GB4943.1-2011
Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced Insulation
Maximum Transient isolation
voltage, 8000 VPK;
Maximum surge isolation
voltage, 8000 VPK,
Maximum repetitive peak
isolation voltage, 2121 VPK
Isolation Rating of 5700
VRMS;
Reinforced insulation per
CSA 60950-1- 07+A1+A2
and IEC 60950-1 (2nd Ed.),
800 VRMS max working
voltage (pollution degree 2,
material group I) ;
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (354 VPK)
max working voltage
Single Protection, 5700
VRMS (1)
Reinforced Insulation,
Altitude ≤ 5000m, Tropical
climate, 400 VRMS maximum
working voltage
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS
5700 VRMS Reinforced insulation per
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS
Certification completed
Certificate number:
40040142
Certificate planned
Certification completed
File number: E181974
Certification completed
Certificate number:
CQC16001141761
Certification completed
Client ID number: 77311
(1)
8
Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
7.9 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 –
GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.25
V
VOLTAGE SUPPLY
VIT+(UVLO1)
Positive-going UVLO1 threshold-voltage
input side
VIT-(UVLO1)
Negative-going UVLO1 threshold-voltage
input side
VHYS(UVLO1)
UVLO1 Hysteresis voltage (VIT+ – VIT–)
input side
0.2
VIT+(UVLO2)
Positive-going UVLO2 threshold-voltage
output side
12
VIT–(UVLO2)
Negative-going UVLO2 threshold-voltage
output side
VHYS(UVLO2)
UVLO2 hysteresis voltage (VIT+ – VIT–)
output side
IQ1
Input-supply quiescent current
2.8
4.5
mA
IQ2
Output-supply quiescent current
3.6
6
mA
1.7
9.5
V
V
13
V
11
V
1
V
LOGIC I/O
VIT+(IN,RST)
Positive-going input-threshold voltage (IN+,
IN–, RST)
VIT–(IN,RST)
Negative-going input-threshold voltage
(IN+, IN–, RST)
VHYS(IN,RST)
Input hysteresis voltage (IN+, IN–, RST)
IIH
High-level input leakage at (IN+) (1)
IN+ = VCC1
IIL
Low-level input leakage at (IN–, RST) (2)
IN– = GND1, RST = GND1
IPU
Pullup current of FLT, RDY
V(RDY) = GND1, V(FLT) = GND1
V(OL)
Low-level output voltage at FLT, RDY
I(FLT) = 5 mA
0.7 × VCC1
0.3 × VCC1
V
V
0.15 × VCC1
V
100
µA
-100
µA
100
µA
0.2
V
2
V
GATE DRIVER STAGE
V(OUTPD)
Active output pulldown voltage
I(OUTH/L) = 200 mA, VCC2 = open
VOUTH
High-level output voltage
I(OUTH) = –20 mA
VOUTL
Low-level output voltage
I(OUTL) = 20 mA
I(OUTH)
High-level output peak current
IN+ = high, IN– = low,
V(OUTH) = VCC2 - 15 V
1.5
2.5
A
I(OUTL)
Low-level output peak current
IN+ = low, IN– = high,
V(OUTL) = VEE2 + 15 V
3.4
5
A
I(OLF)
Low-level output current during fault
condition
VCC2 – 0.5
VCC2 – 0.24
VEE2 + 13
V
VEE2 + 50
130
mV
mA
ACTIVE MILLER CLAMP
V(CLP)
Low-level clamp voltage
I(CLP) = 20 mA
I(CLP)
Low-level clamp current
V(CLAMP) = VEE2 + 2.5 V
V(CLTH)
Clamp threshold voltage
VEE2 + 0.015
VEE2 + 0.08
V
1.6
2.5
3.3
A
1.6
2.1
2.5
V
SHORT CIRCUIT CLAMPING
V(CLP-OUTH)
Clamping voltage
(VOUTH – VCC2)
IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTH) = 500 mA
1.1
1.3
V
V(CLP-OUTL)
Clamping voltage
(VOUTL – VCC2)
IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTL) = 500 mA
1.3
1.5
V
V(CLP-CLP)
Clamping voltage
(VCLP – VCC2)
IN+ = high, IN– = low, tCLP = 10 µs,
I(CLP) = 500 mA
1.3
V(CLP-CLAMP)
Clamping voltage at CLAMP
IN+ = High, IN– = Low, I(CLP) = 20
mA
0.7
1.1
V
V(CLP-OUTL)
Clamping voltage at OUTL
(VCLP – VCC2)
IN+ = High, IN– = Low, I(OUTL) = 20
mA
0.7
1.1
V
0.58
mA
V
DESAT PROTECTION
I(CHG)
Blanking-capacitor charge current
V(DESAT) – GND2 = 2 V
0.42
0.5
I(DCHG)
Blanking-capacitor discharge current
V(DESAT) – GND2 = 6 V
9
14
(1)
(2)
mA
IIH for IN–, RST pin is zero as they are pulled high internally.
IIL for IN+ is zero as it is pulled low internally.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
9
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 –
GND2 = 15 V, GND2 – VEE2 = 8 V
MIN
TYP
MAX
V(DSTH)
DESAT threshold voltage with respect to
GND2
PARAMETER
TEST CONDITIONS
UNIT
8.3
9
9.5
V
V(DSL)
DESAT voltage with respect to GND2,
when OUTH or OUTL is driven low
0.4
1
V
7.10 Switching Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 –
GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Output-signal rise time at OUTH
CLOAD = 1 nF
12
18
35
ns
tf
Output-signal fall time at OUTL
CLOAD = 1 nF
12
20
37
ns
tPLH, tPHL
Propagation Delay
CLOAD = 1 nF
76
110
ns
tsk-p
Pulse skew |tPHL – tPLH|
CLOAD = 1 nF
20
ns
(1)
ns
30
40
ns
553
760
ns
2
3.5
μs
See Figure 44, Figure 45,
and Figure 46
tsk-pp
Part-to-part skew
CLOAD = 1 nF
tGF (IN,/RST)
Glitch filter on IN+, IN–, RST
CLOAD = 1 nF
tDS
(90%)
DESAT sense to 90% VOUTH/L delay
CLOAD = 10 nF
tDS
(10%)
DESAT sense to 10% VOUTH/L delay
CLOAD = 10 nF
tDS
(GF)
DESAT-glitch filter delay
CLOAD = 1 nF
(FLT)
DESAT sense to FLT-low delay
See Figure 46
tLEB
Leading-edge blanking time
See Figure 44 and Figure 45
tGF(RSTFLT)
Glitch filter on RST for resetting FLT
tDS
(2)
CI
Input capacitance
CMTI
Common-mode transient immunity
(1)
(2)
10
30
20
330
310
400
300
VI = VCC1 / 2 + 0.4 × sin (2πft), f = 1 MHz,
VCC1 = 5 V
VCM = 1500 V, see Figure 47
2
100
120
ns
1.4
μs
480
ns
800
ns
pF
kV/μs
Measured at same supply voltage and temperature condition.
Measured from input pin to ground.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
7.11 Insulation Characteristics Curves
1.E+11
87.5%
1.E+9
Time to Fail (s)
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = 5.5 V
VCC2 = 15 V
VCC2 = 30 V
450
Safety Limiting Current (mA)
1.E+10
500
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (ICC1 Supply Current vs Input Frequency
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
5
5.5
4.5
5
ICC2 - Supply Current (mA)
ICC2 - Supply Current (mA)
Typical Characteristics (continued)
4
3.5
3
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
2.5
2
-55
4.5
4
3.5
3
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
2.5
2
-35
-15
5
25
45
65
Ambient Temperature (qC)
85
105
125
0
Input frequency = 1 kHz
Figure 22. ICC2 Supply Current vs Temperature
250
300
D009
Figure 23. ICC2 Supply Current vs Input Frequency
100
90
60
80
Propagation Delay (ns)
ICC2 - Supply Current (mA)
100
150
200
Input Frequency - (kHz)
No CL
70
50
40
30
20
70
60
50
40
30
tpLH at VCC2 = 15 V
tpHL at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 30 V
20
10
VCC2 = 15 V
VCC2 = 30 V
10
0
-55
0
0
10
20
RGH = 10 Ω
30
40
50
60
70
Load Capacitance (nF)
80
90
100
-15
5
25
45
65
Ambient Temperature (qC)
CL = 1 nF
VCC1 = 5 V
RGL = 5 Ω, 20 kHz
85
105
125
D012
RGH = 0 Ω
RGL = 0 Ω
Figure 25. Propagation Delay vs Temperature
Figure 24. ICC2 Supply Current vs Load Capacitance
1200
tpLH at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 15 V
tpHL at VCC2 = 30 V
90
1000
Propagation Delay (ns)
80
70
60
50
40
30
tpLH at VCC1 = 3.3 V
tpHL at VCC1 = 3.3 V
tpLH at VCC1 = 5 V
tpHL at VCC1 = 5 V
20
10
0
-55
-35
D011
100
Propagation Delay (ns)
50
D010
800
600
400
200
0
-35
-15
CL = 1 nF
VCC2 = 15 V
5
25
45
65
Ambient Temperature (qC)
RGH = 0 Ω
85
105
125
0
10
20
D013
RGL = 0 Ω
Figure 26. Propagation Delay vs Temperature
RGH = 10 Ω
30
40
50
60
70
Ambient Temperature (qC)
RGL = 5 Ω
80
90
100
D014
VCC1 = 5 V
Figure 27. Propagation Delay vs Load Capacitance
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
15
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
Typical Characteristics (continued)
600
1000
VCC2 = 15 V
VCC2 = 30 V
900
500
Transistion Time (ns)
800
Transistion Time (ns)
VCC2 = 15 V
VCC2 = 30 V
700
600
500
400
300
400
300
200
200
100
100
0
0
0
10
20
30
40
50
60
70
Load Capacitance (nF)
RGH = 0 Ω
80
90
0
100
10
RGL = 0 Ω
VCC1 = 5 V
30
40
50
60
70
Load Capacitance (nF)
RGH = 0 Ω
Figure 28. tr Rise Time vs Load Capacitance
80
90
100
D016
RGL = 0 Ω
VCC1 = 5 V
Figure 29. tf Fall Time vs Load Capacitance
6000
2000
VCC2 = 15 V
VCC2 = 30 V
5000
VCC2 = 15 V
VCC2 = 30 V
1800
1600
Transistion Time (ns)
Transistion Time (ns)
20
D015
4000
3000
2000
1400
1200
1000
800
600
400
1000
200
0
0
0
10
20
RGH = 10 Ω
30
40
50
60
70
Load Capacitance (nF)
80
90
100
0
RGL = 5 Ω
VCC1 = 5 V
440
420
400
380
360
340
VCC2 = 15 V
VCC2 = 30 V
-15
5
25
45
65
Ambient Temperature (qC)
85
105
125
D019
tDESAT(10%) - DESAT Sense to 10% VOUT Delay (Ps)
tLEB - Leading Edge Blanking Time (ns)
460
-35
80
90
100
D018
RGL = 5 Ω
VCC1 = 5 V
4
VCC2 = 15 V
VCC2 = 30 V
3.5
3
2.5
2
1.5
1
-55
-35
-15
CL = 10 nF
Figure 32. Leading Edge Blanking Time With Temperature
16
30
40
50
60
70
Load Capacitance (nF)
Figure 31. tf Fall Time vs Load Capacitance
480
300
-55
20
RGH = 10 Ω
Figure 30. tr Rise Time vs Load Capacitance
500
320
10
D017
5
25
45
65
Ambient Temperature (qC)
RGH = 0 Ω
85
105
125
D020
RGL = 0 Ω
Figure 33. DESAT Sense to VOUT 10% Delay vs Temperature
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
610
VCC2 = 15 V
VCC2 = 30 V
590
570
550
530
510
490
470
450
-55
-35
-15
5
25
45
65
Ambient Temperature (qC)
CL = 10 nF
85
105
125
tDESAT(/FLT) - DESAT Sense to /FLT Low Delay (Ps)
tDESAT(90%) - DESAT Sense to 90% VOUT Delay (Ps)
Typical Characteristics (continued)
VCC2 = 15 V
VCC2 = 30 V
1.2
1.15
1.1
1.05
-55
RGH = 0 Ω
-15
5
25
45
65
Ambient Temperature (qC)
85
105
125
D022
RGL = 0 Ω
Figure 35. DESAT Sence to Fault Low Delay vs Temperature
120
5
4.8
Reset To Fault Delay (ns)
100
4.6
4.4
4.2
4
3.8
80
60
40
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
20
3.6
VCC1 = 5 V, VCC2 = 15 V
3.4
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
0
-40
110 125
2
1.8
4
1.6
Active Pulldown Voltage (V)
5
3.5
3
2.5
2
1.5
0.5
0
-40
V(CLAMP) = 2 V
V(CLAMP) = 4 V
V(CLAMP) = 6 V
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
-10
110 125
95
110 125
D023
1.2
1
0.8
0.6
0.4
I(OUTH/L) = 100 mA
I(OUTH/L) = 200 mA
0
-55
-35
D025
Figure 38. Miller Clamp Current vs Temperature
20 35 50 65 80
Ambient Temperature (qC)
1.4
0.2
95
5
Figure 37. Reset to Fault Delay Across Temperature
4.5
1
-25
D024
Figure 36. Fault and RDY Low to RDY High Delay vs
Temperature
ICLP - Clamp Low-Level Current (A)
-35
D021
Figure 34. DESAT Sense to VOUT 90% Delay vs Temperature
/FLT and RDY Low to RDY High Delay (Ps)
1.25
-15
5
25
45
65
Ambient Temperature (qC)
85
105
125
D026
Figure 39. Active Pulldown Voltage vs Temperature
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
17
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
Typical Characteristics (continued)
Short Circuit Clamp Voltage on OUTH (mV)
VCLIP_CLAMP Short Circuit Clamp
Voltage on Clamp Across Temperature
1500
1350
1200
1050
900
750
600
450
300
20 mA at VCC2 = 15 V
20 mA at VCC2 = 30 V
250 mA at VCC2 = 15 V
150
0
-55
-35
-15
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
5
25
45
65
Ambient Temperature (qC)
85
105
125
1350
1200
1050
900
750
600
450
0
-55
20 mA at VCC2 = 15 V
20 mA at VCC2 = 30 V
250 mA at VCC2 = 15 V
-35
-15
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
5
25
45
65
Ambient Temperature (qC)
85
105
125
1000
800
600
400
200
0
-55
-35
-15
85
105
125
D027
-420
-440
-460
-480
-500
-520
-540
-560
-580
VDESAT = 6 V
-600
-55
-35
-15
VCC2 = 15 V
18
5
25
45
65
Ambient Temperature (qC)
-400
D028
Figure 42. Short-Circuit Clamp Voltage on OUTL Across
Temperature
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
Figure 41. Short-Circuit Clamp Voltage on OUTH Across
Temperature
ICHG - Blanking Capacitor Charging Current (PA)
Short Circuit Clamp Voltage on OUTL (mV)
1500
150
20 mA at VCC2 = 15 V
20 mA at VCC2 = 30 V
250 mA at VCC2 = 15 V
1200
D029
Figure 40. Short-Circuit Clamp Voltage on Clamp Across
Temperature
300
1400
5
25
45
65
Ambient Temperature (qC)
85
105
125
D030
DESAT = 6 V
Figure 43. Blanking Capacitor Charging Current vs
Temperature
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
8 Parameter Measurement Information
IN±
IN+
0V
50 %
50 %
tr
tf
90%
50%
OUTH/L
10%
tPLH
tPHL
Figure 44. OUTH and OUTL Propagation Delay, Non-Inverting Configuration
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
19
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
Parameter Measurement Information (continued)
IN±
50 %
IN+
50 %
VCC1
tr
tf
90%
50%
OUTH/L
10%
tPLH
tPHL
Figure 45. OUTH and OUTL Propagation Delay, Inverting Configuration
20
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
Parameter Measurement Information (continued)
Inputs
blocked
Inputs
released
The inputs are muted for 5 µs by internal circuit after
DESAT is detected. RDY is also low until the mute time.
FLT can be reset, only if RDY goes high.
IN+
(IN± = GND1)
90%
VOUTH/L
tDS(90%)
10%
tDS(10%)
VDSTH
tLEB
DESAT
FLT
tDS(FLT)
RDY
tMute
RST-rising edge
turns FLT high
RST
tRST
Figure 46. DESAT, OUTH/L, FLT, RST Delay
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
21
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
Parameter Measurement Information (continued)
15
VCC2
VCC1
5
14
10
S1
-
11
13
3
GND1
GND2
VEE2 1, 8
RST
I s ol ati o n B a rri e r
9 , 16
+
15V
1µF
0.1µF
2.25 V- 5.5 V
IN+
IN -
OUTL
CL
FLT
DESAT
RDY
CLAMP
12
OUTH
+
VCM
6
-
1nF
+
Pass ± Fail Criterion :
OUT must remain stable
2
-
7
4
Copyright © 2016, Texas Instruments
Incorporated
Figure 47. Common-Mode Transient Immunity Test Circuit
22
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
9 Detailed Description
9.1 Overview
The ISO5852S-EP device is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output
power stage are separated by a Silicon dioxide (SiO2) capacitive isolation.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET
(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to
supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as
well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The
capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and
receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S-EP device also
contains undervoltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output
pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The
ISO5852S-EP device also has an active Miller clamp which can be used to prevent parasitic turnon of the
external power transistor, due to Miller effect, for unipolar supply operation.
9.2 Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
IN±
Mute
9V
IN+
GND2
VCC2
VCC1
RDY
Gate Drive
Ready
OUTH
and
Encoder
Logic
STO
VCC1
FLT
Q
S
Q
R
VCC1
OUTL
Decoder
2V
Fault
CLAMP
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
23
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
9.3 Feature Description
9.3.1 Supply and Active Miller clamp
The ISO5852S-EP device supports both bipolar and unipolar power supply with active Miller clamp.
For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its
emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its
gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the
IGBT gate. Typical values of VCC2 and VEE2 for bipolar operation are 15-V and -8-V with respect to GND2.
For operation with unipolar supply, typically, VCC2 is connected to 15-V with respect to GND2, and VEE2 is
connected to GND2. In this use case, the IGBT can turn on due to additional charge from IGBT Miller
capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the
CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.
Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage
transitions below 2-V the CLAMP current output is activated.
9.3.2 Active Output Pulldown
The Active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to VEE2 to ensure safe IGBT
off-state, when the output side is not connected to the power supply.
9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1
drops below VIT-(UVLO1), irrespective of IN+, IN– and RST input till VCC1 goes above VIT+(UVLO1).
In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN– and
RST input till VCC2 goes above VIT+(UVLO2).
Ready (RDY) pin indicates status of input and output side Undervoltage Lockout (UVLO) internal protection
feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise,
RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for
operation.
9.3.4 Soft Turnoff, Fault (FLT) and Reset (RST)
During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables, OUTH, and
pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation
barrier pulling the FLT output at the input side low and blocking the isolator input. mute logic is activated through
the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a
active-low pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for atleast the specified minimum duration (800 ns), device input logic can be enabled or disabled.
9.3.5 Short Circuit Clamp
Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP
pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes
on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly
higher than the output side supply.
24
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
9.4 Device Functional Modes
In ISO5852S-EP OUTH/L to follow IN+ in normal functional mode, FLT pin must be in the high state. Table 1 lists
the device functions.
Table 1. Function Table (1)
VCC1
VCC2
IN+
IN–
RST
RDY
OUTH/L
PU
PD
X
X
X
Low
Low
PD
PU
X
X
X
Low
Low
PU
PU
X
X
Low
High
Low
PU
Open
X
X
X
Low
Low
PU
PU
Low
X
X
High
Low
PU
PU
X
High
X
High
Low
PU
PU
High
Low
High
High
High
(1)
PU: Power Up (VCC1 ≥ 2.25 V, VCC2 ≥ 13 V), PD: Power Down (VCC1 ≤ 1.7 V, VCC2 ≤ 9.5 V), X: Irrelevant
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
25
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO5852S-EP device is an isolated gate driver for power semiconductor devices such as IGBTs and
MOSFETs. It is intended for use in applications such as motor control, industrial inverters and switched mode
power supplies. In these applications, sophisticated PWM control signals are required to turn the power devices
on and off, which at the system level eventually may determine, for example, the speed, position, and torque of
the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the
outputs of a microcontroller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required
by the MOSFETs and IGBTs, however, are in the range of 30-V (using unipolar output supply) to 15-V (using
bipolar output supply), and require high-current capability to drive the large capacitive loads offered by those
power transistors. The gate drive must also be applied with reference to the emitter of the IGBT (source for
MOSFET), and by construction, the emitter node in a gate-drive system swings between 0 to the DC-bus voltage,
which can be several 100s of volts in magnitude.
The ISO5852S-EP device is therefore used to level shift the incoming 2.5-V, 3.3-V, and 5-V control signals from
the microcontroller to the 30-V (using unipolar output supply) to 15-V (using bipolar output supply) drive required
by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller
side.
10.2 Typical Applications
Figure 48 shows the typical application of a three-phase inverter using six ISO5852S-EP isolated gate drivers.
Three-phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for
high-power applications such as high-voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5852SEP devices that are connected to one of the three load terminals. The operation of the three switches is
coordinated so that one switch operates at each 60 degree point of the fundamental output waveform, therefore
creating a six-step line-to-line output waveform. In this type of applications, carrier-based PWM techniques are
applied to retain waveform envelope and cancel harmonics.
26
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
Typical Applications (continued)
PWM
3-Phase
Input
1
2
3
4
5
6
ISO
5852S
ISO
5852S
ISO
5852S
ISO
5852S
ISO
5852S
ISO
5852S
µC
M
FAULT
Figure 48. Typical Motor-Drive Application
10.2.1 Design Requirements
Unlike optocoupler-based gate drivers which required external current drivers and biasing circuitry to provide the
input control signals, the input control to the ISO5852S-EP device is CMOS and can be directly driven by the
microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a
pullup resistor on the common-drain FLT output signal, and a high-voltage protection diode between the IGBT
collector and the DESAT input. Additional details are explained in the subsequent sections. Table 2 lists the
allowed range for input and output supply voltage, and the typical current output available from the gate-driver.
Table 2. Design Parameters
PARAMETER
VALUE
Input supply voltage
2.25 V to 5.5 V
Unipolar output-supply voltage (VCC2 – GND2 = VCC2 – VEE2)
15 V to 30 V
Bipolar output-supply voltage (VCC2 – VEE2)
15 V to 30 V
Bipolar output-supply voltage (GND2 – VEE2)
0 V to 15 V
Output current
2.5 A
10.2.2 Detailed Design Procedure
10.2.2.1 Recommended ISO5852S-EP Application Circuit
The ISO5852S-EP device has both, inverting and noninverting gate-control inputs, an active-low reset input, and
an open-drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 49
shows a typical gate-driver implementation with unipolar output supply. Figure 50 shows a typical gate-driver
implementation with bipolar output supply using the ISO5852S-EP device.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
27
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
A 0.1-μF bypass capacitor, recommended at the VCC1 input supply pin, and 1-μF bypass capacitor,
recommended at the VCC2 output supply pin, provide the large transient currents required during a switching
transition to ensure reliable operation. The 220-pF blanking capacitor disables DESAT detection during the off-toon transition of the power device. The DESAT diode (DDST) and the 1-kΩ series resistor on the DESAT pin are
external protection components. The RG gate resistor limits the gate-charge current and indirectly controls the
rise and fall times of the IGBT collector voltage. The open-drain FLT output and RDY output have a passive 10kΩ pullup resistor. In this application, the IGBT gate driver is disabled when a fault is detected and does not
resume switching until the microcontroller applies a reset signal.
10R
2.25 to
5V
+
±
0.1 µF
+
10 k
15
10 k
±
VCC1
ISO5852S
VCC2
9
GND1
16
10
11
12
13
14
GND2
IN+
VEE2
IN±
DESAT
RDY
CLAMP
OUTL
FLT
OUTH
RST
10R
5
+
3
0.1 µF
±
2.25 to
5V
15 V
0.1 µF
±
1
8
2
+
DDST
1k
10 k
10 k
±
4
RGL
10
11
13
RGH
VCC1
ISO5852S
9
GND1
16
12
7
6
15
+
14
VCC2
GND2
5
+
3
0.1 µF
±
+
IN+
VEE2
IN±
DESAT
RDY
CLAMP
FLT
OUTL
OUTH
RST
220 pF
1 0.1 µF
8
1k
2
±
15 V
15 V
DDST
7
6
4
RGL
RGH
220 pF
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Unipolar Output Supply
Figure 50. Bipolar Output Supply
10.2.2.2 FLT and RDY Pin Circuitry
A is 50-kΩ pullup resistor exists internally on FLT and RDY pins. The FLT and RDY pins are an open-drain
output. A 10-kΩ pullup resistor can be used to make it faster rise and to provide logic high when FLT and RDY is
inactive, as shown in Figure 51.
Fast common-mode transients can inject noise and glitches on FLT and RDY pins because of parasitic coupling.
The injection of noise and glitches is dependent on board layout. If required, additional capacitance (100 pF to
300 pF) can be included on the FLT and RDY pins.
10R
2.25 to 5 V
VCC1
ISO5852S
+
0.1 µF
±
10 k
15
9
GND1
16
10 k
12
13
RDY
FLT
µC
14
10
11
RST
IN+
IN±
Copyright © 2016, Texas Instruments Incorporated
Figure 51. FLT and RDY Pin Circuitry for High CMTI
28
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
10.2.2.3 Driving the Control Inputs
The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the
high-voltage output circuit to the low-voltage input side of the ISO5852S-EP device. For maximum CMTI
performance, the digital control inputs, IN+ and IN–, must be actively driven by standard CMOS, push-pull drive
circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching
of the ISO5852S-EP output under extreme common-mode transient conditions. Passive drive circuits, such as
open-drain configurations using pullup resistors, must be avoided. A 20-ns glitch filter exists that can filter a glitch
up to 20 ns on IN+ or IN–.
10.2.2.4 Local Shutdown and Reset
In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the
individual reset lines are independently asserted low to reset the motor controller after a fault condition.
10R
15
0.1 µF
2.25 V - 5.5 V
9 , 16 GND1
GND1
10 k
10 k
12
13
10 k
12 RDY
RDY
13
FLT
µC
ISO 5852S - EP
15 V
CC1
0.1 µF
2.25 V - 5.5 V
9 , 16
10 k
10R
ISO 5852S - EP
VCC1
FLT
µC
14
10
11
14
RST
RST
IN+
10 IN+
IN±
11 IN±
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
29
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
10.2.2.5 Global-Shutdown and Reset
When configured for inverting operation, the ISO5852S-EP device can be configured to shutdown automatically
in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT
outputs of multiple ISO5852S-EP devices can be wired together forming a single, common fault bus for
interfacing directly to the microcontroller. When any of the six gate drivers of a three-phase inverter detects a
fault, the active-low FLT output disables all six gate drivers simultaneously.
10R
2.25 to 5 V
VCC1
ISO5852S
+
0.1 µF
±
10 k
15
9
GND1
16
10 k
12
13
RDY
FLT
µC
14
10
11
To other
RST pins
RST
IN+
IN±
To other
FLT pins
Copyright © 2016, Texas Instruments Incorporated
Figure 53. Global Shutdown With Inverting Input Configuration
30
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
10.2.2.6 Auto-Reset
In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching
cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault
state until the gate control signal changes to the gate-low state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch is always reset before IN+ goes high again.
This configuration protects the IGBT on a cycle-by-cycle basis and automatically resets before the next on cycle.
10R
15
2.25 V- 5.5 V
0.1 µF
2.25 V- 5.5 V
9 , 16
10k
10R
ISO 5852S - EP
VCC1
9 , 16
10k
13
µC
14
13
FLT
µC
14
RST
GND1
10k
12
RDY
10
RDY
FLT
RST
10
IN +
IN +
11
ISO 5852S - EP
VCC1
0.1 µF
GND1
10k
12
15
11
IN -
IN -
Copyright © 2016, Texas Instruments Incorporated
Figure 54. Auto Reset for Noninverting and Inverting Input Configuration
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
31
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
10.2.2.7 DESAT Pin Protection
Switching inductive loads causes large, instantaneous forward-voltage transients across the freewheeling diodes
of the IGBTs. These transients result in large negative-voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in
series with the DESAT diode.
Further protection is possible through an optional Schottky diode, whose low-forward voltage assures clamping of
the DESAT input to GND2 potential at low-voltage levels.
ISO5852S
VCC2
GND2
5
+
3
1 µF
±
+
VEE2
DESAT
CLAMP
OUTL
OUTH
1
8
2
0.1 µF
RS
±
15 V
15 V
DDST
7
6
4
220 pF
±
RGL
VFW-Inst
RGH
+
VFW
Copyright © 2016, Texas Instruments Incorporated
Figure 55. DESAT Pin Protection With Series Resistor and Schottky Diode
32
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
10.2.2.8 DESAT Diode and DESAT Threshold
The function of the DESAT diode is to conduct forward current, allowing sensing of the saturated collector-toemitter voltage of the IGBT, V(DESAT), (when the IGBT is on), and to block high voltages (when the IGBT is off).
During the short transition time when the IGBT is switching, a commonly high dVCE/dt voltage ramp rate occurs
across the IGBT. This ramp rate results in a charging current I(CHARGE) = C(D-DESAT) × dVCE/dt, charging the
blanking capacitor. C(D-DESAT) is the diode capacitance at DESAT.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ C(BLANK) / C(D-DESAT).
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = V(DESAT), the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 9 V – n × VF (where n is the number of DESAT diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating can be
selected.
10.2.2.9 Determining the Maximum Available, Dynamic Output Power, POD-max
The ISO5852S-EP maximum-allowed total power consumption of PD = 251 mW consists of the total input power,
PID, the total output power, POD, and the output power under load, POL:
PD = PID + POD + POL
(1)
PID = VCC1-max × ICC1-max = 5.5 V × 4.5 mA = 24.75 mW
(2)
POD = (VCC2 – VEE2) × ICC2-max = (15 V – [–8 V]) × 6 mA = 138 mW
(3)
POL = PD – PID – POD = 251 mW – 24.75 mW – 138 mW = 88.25 mW
(4)
With:
and:
then:
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
POL-WC = 0.5 ´ fINP ´ QG ´
(VCC2
æ ron-max
ö
roff-max
+
- VEE2 ) ´ ç
÷
roff-max + RG ø
è ron-max + RG
where
•
•
•
•
•
•
•
fINP = signal frequency at the control input IN+
QG = power device gate charge
VCC2 = positive output supply with respect to GND2
VEE2 = negative output supply with respect to GND2
ron-max = worst case output resistance in the on-state: 4 Ω
roff-max = worst case output resistance in the off-state: 2.5 Ω
RG = gate resistor
(5)
When RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 56 shows a simplified
output stage model for calculating POL-WC.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
33
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
ISO5852S
VCC2
+
±
Ron-max
15 V
RG
OUTH/L
QG
Roff-max
+
±
8V
VEE2
Copyright © 2016, Texas Instruments Incorporated
Figure 56. Simplified Output Model for Calculating POL-WC
10.2.2.10 Example
This examples considers an IGBT drive with the following parameters:
• ION-PK = 2 A
• QG = 650 nC
• fINP = 20 kHz
• VCC2 = 15 V
• VEE2 = –8 V
Applying the value of the gate resistor RG = 10 Ω.
Then, calculating the worst-case output-power consumption as a function of RG, using Equation 5 ron-max = worst
case output resistance in the on-state: 4 Ω, roff-max = worst case output resistance in the off-state: 2.5 Ω, RG =
gate resistor yields
4Ω
2.5 Ω
æ
ö
POL-WC = 0.5 ´ 20 kHz ´ 650 nC ´ (15 V - ( - 8 V) )´ ç
+
÷ = 72.61 mW
è 4 Ω + 10 Ω 2.5 Ω + 10 Ω ø
(6)
Because POL-WC = 72.61 mW is less than the calculated maximum of POL = 88.25 mW, the resistor value of RG =
10 Ω is suitable for this application.
34
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
10.2.2.11 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in
Figure 57) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10
pair for up to 15 A maximum.
ISO5852S
VCC2
GND2
5
+
3
1 µF
±
+
VEE2
DESAT
CLAMP
OUTL
OUTH
1 0.1 µF
8
2
±
1k
15 V
15 V
DDST
7
6
4
RG
10
10
220 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 57. Current Buffer for Increased Drive Current
CH 2: 10 V/Div
CH 2: 10 V/Div
CH 1: 5 V/Div
CH 1: 5 V/Div
10.2.3 Application Curves
5 µs/Div
CL = 1 nF
VCC2 – GND2 = 15 V
(VCC2 – VEE2 = 23 V)
RGH = 10 Ω
GND2 - VEE2 = 8 V
5 µs/Div
RGL = 10 Ω
Figure 58. Normal Operation - Bipolar Supply
CL = 1 nF
RGH = 10 Ω
VCC2 – VEE2 = VCC2 - GND2 = 20 V
RGL = 10 Ω
Figure 59. Normal Operation - Unipolar Supply
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
35
ISO5852S-EP
SLLSEW1 – DECEMBER 2016
www.ti.com
11 Power Supply Recommendations
To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the VCC1 input supply pin and a 1-μF bypass capacitor is recommended at the VCC2output
supply pin. The capacitors should be placed as close to the supply pins as possible. The recommended
placement of the capacitors is 2 mm (maximum) from the input and output power supply pins (VCC1 and VCC2).
12 Layout
12.1 Layout Guidelines
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 60). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects between the gate driver and the microcontroller and
power transistors. Gate driver control input, Gate driver output OUTH/L and DESAT should be routed in the
top layer.
• Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for
the return current flow. On the driver side, use GND2 as the ground plane.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2. On the gate-driver VEE2 and VCC2 can be used as power planes. They can share
the same layer on the PCB as long as they are not connected together.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,
routing, and other details, see the Digital Isolator Design Guide (SLLA284).
12.2 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.3 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 60. Recommended Layer Stack
36
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
ISO5852S-EP
www.ti.com
SLLSEW1 – DECEMBER 2016
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Digital Isolator Design Guide
• ISO5852S Evaluation Module (EVM) User’s Guide
• Isolation Glossary
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5852S-EP
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO5852SMDWREP
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO5852SM
V62/16623-01XE
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO5852SM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
