ISO5852SQDWQ1

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO5852S-Q1 SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 ISO5852S-Q1 High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features 1 Features 2 Applications • • • 1 • • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM Classification Level 3A – Device CDM Classification Level C6 100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at VCM = 1500 V Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents Short Propagation Delay: 76 ns (Typ), 110 ns (Max) 2-A Active Miller Clamp Output Short-Circuit Clamp Soft Turn-Off (STO) during Short Circuit Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs 2.25-V to 5.5-V Input Supply Voltage 15-V to 30-V Output Driver Supply Voltage CMOS Compatible Inputs Rejects Input Pulses and Noise Transients Shorter Than 20 ns Isolation Surge Withstand Voltage 12800-VPK Safety-Related Certifications: – 8000-VPK VIOTM and 2121-VPK VIORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 – 5700-VRMS Isolation for 1 Minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards – TUV Certification per EN 61010-1 and EN 60950-1 – GB4943.1-2011 CQC Certification – All Certifications Complete per UL, VDE, CQC, TUV and Planned for CSA Isolated IGBT and MOSFET Drives in: – HEV and EV Power Modules – Industrial Motor Control Drives – Industrial Power Supplies – Solar Inverters – Induction Heating 3 Description The ISO5852S-Q1 device is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage. An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, VEE2, the gate-driver output is pulled hard to the VEE2 potential, turning the IGBT immediately off. Device Information(1) PART NUMBER ISO5852S-Q1 PACKAGE BODY SIZE (NOM) SOIC (16) 10.30 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram VCC2 VCC1 VCC1 UVLO1 UVLO2 500 µA DESAT IN± Mute 9V IN+ GND2 VCC2 VCC1 RDY Gate Drive Ready OUTH and Encoder Logic STO VCC1 FLT Q S Q R VCC1 OUTL Decoder 2V Fault CLAMP RST GND1 VEE2 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO5852S-Q1 SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Function ........................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 9 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Power Ratings........................................................... 5 Insulation Specifications............................................ 6 Safety-Related Certifications..................................... 7 Safety Limiting Values .............................................. 7 Electrical Characteristics........................................... 8 Switching Characteristics ........................................ 9 Insulation Characteristics Curves ......................... 10 Typical Characteristics .......................................... 11 Parameter Measurement Information ................ 18 Detailed Description ............................................ 20 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 20 20 21 22 10 Application and Implementation........................ 23 10.1 Application Information.......................................... 23 10.2 Typical Applications .............................................. 23 11 Power Supply Recommendations ..................... 31 12 Layout................................................................... 31 12.1 Layout Guidelines ................................................. 31 12.2 PCB Material ......................................................... 31 12.3 Layout Example .................................................... 31 13 Device and Documentation Support ................. 32 13.1 13.2 13.3 13.4 13.5 13.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 32 14 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2016) to Revision A Page • Changed the title of the data sheet from Active Safety Features to Active Protection Features ........................................... 1 • Changed the Electrostatic Discharge Caution...................................................................................................................... 32 2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 ISO5852S-Q1 www.ti.com SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 5 Description (continued) When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input. When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions. The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high. The ISO5852S-Q1 device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient. 6 Pin Configuration and Function DW Package 16-Pin SOIC Top View VEE2 1 16 GND1 DESAT 2 15 VCC1 GND2 3 14 RST OUTH 4 13 FLT VCC2 5 12 RDY OUTL 6 11 IN± CLAMP 7 10 VEE2 8 9 IN+ GND1 Not to scale Pin Functions PIN I/O DESCRIPTION NAME NO. CLAMP 7 O Miller clamp output DESAT 2 I Desaturation voltage input FLT 13 O Fault output, active-low during DESAT condition — Input ground GND1 9 16 GND2 3 — Gate drive common. Connect to IGBT emitter. IN+ 10 I Non-inverting gate drive voltage control input IN– 11 I Inverting gate drive voltage control input OUTH 4 O Positive gate drive voltage output OUTL 6 O Negative gate drive voltage output RDY 12 O Power-good output, active high when both supplies are good. RST 14 I Reset input, apply a low pulse to reset fault latch. VCC1 15 — Positive input supply (2.25-V to 5.5-V) VCC2 5 — Most positive output supply potential. — Output negative supply. Connect to GND2 for unipolar supply application. VEE2 1 8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 3 ISO5852S-Q1 SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT GND1 – 0.3 6 V –0.3 35 V –17.5 0.3 V –0.3 35 V Positive gate-driver output voltage VEE2 – 0.3 VCC2 + 0.3 V Negative gate-driver output voltage VEE2 – 0.3 VCC2 + 0.3 V 2.7 A 5.5 A GND1 – 0.3 VCC1 + 0.3 V 10 mA GND2 – 0.3 VCC2 + 0.3 V VEE2 – 0.3 VCC2 + 0.3 V VCC1 Supply-voltage input side VCC2 Positive supply-voltage output side (VCC2 – GND2) VEE2 Negative supply-voltage output side (VEE2 – GND2) V(SUP2) Total-supply output voltage (VCC2 – VEE2) V(OUTH) V(OUTL) I(OUTH) Gate-driver high output current Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%) I(OUTL) Gate-driver low output current Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%) V(LIP) Voltage at IN+, IN–,FLT, RDY, RST I(LOP) Output current of FLT, RDY V(DESAT) Voltage at DESAT V(CLAMP) Clamp voltage TJ Junction temperature –40 150 °C TSTG Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±4000 Charged-device model (CDM), per AEC Q100-011 ±1500 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC1 Supply-voltage input side VCC2 V(EE2) V(SUP2) Total supply-voltage output side (VCC2 – VEE2) V(IH) High-level input voltage (IN+, IN–, RST) V(IL) Low-level input voltage (IN+, IN–, RST) tUI Pulse width at IN+, IN– for full output (CLOAD = 1 nF) tRST TA 4 NOM MAX UNIT 2.25 5.5 V Positive supply-voltage output side (VCC2 – GND2) 15 30 V Negative supply-voltage output side (VEE2 – GND2) –15 0 V 15 30 V 0.7 × VCC1 VCC1 V 0 0.3 × VCC1 V 40 ns Pulse width at RST for resetting fault latch 800 ns Ambient temperature –40 Submit Documentation Feedback 125 °C Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 ISO5852S-Q1 www.ti.com SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 7.4 Thermal Information ISO5852S-Q1 THERMAL METRIC (1) DW (SOIC) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 99.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.5 °C/W RθJB Junction-to-board thermal resistance 56.5 °C/W ψJT Junction-to-top characterization parameter 29.2 °C/W ψJB Junction-to-board characterization parameter 56.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). 7.5 Power Ratings Full-chip power dissipation is derated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that the junction temperature does not exceed 150°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Maximum power dissipation (both sides) VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C 1255 mW PID Maximum input power dissipation VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C 175 mW POD Maximum output power dissipation VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C 1080 mW Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 5 ISO5852S-Q1 SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7.6 Insulation Specifications PARAMETER TEST CONDITIONS VALUE UNIT GENERAL External clearance (1) Shortest terminal-to-terminal distance through air 8 mm CPG External creepage (1) Shortest terminal-to-terminal distance across the package surface 8 mm DTI Distance through the insulation Minimum internal gap (internal clearance) 21 µm Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; Material Group I according to IEC 60664-1; UL 746A >600 V CLR CTI Material group I Overvoltage Category DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III (2) Maximum repetitive peak isolation voltage AC voltage (bipolar) VIOWM Maximum isolation working voltage 2121 VPK AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test, see Figure 1 1500 VRMS DC voltage 2121 VDC 8000 8000 VIOTM Maximum transient isolation voltage VTEST = VIOTM; t = 60 s (qualification); t = 1 s (100% production) VIOSM Maximum surge isolation voltage (3) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification) Apparent charge (4) qpd Barrier capacitance, input to output (5) CIO Isolation resistance, input to output (5) RIO VPK Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK , tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK , tm = 10 s ≤5 Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 60 s; Vpd(m) = 1.875× VIORM = 3977 VPK , tm = 10 s ≤5 VIO = 0.4 sin (2πft), f = 1 MHz pC 1 pF VIO = 500 V, TA = 25°C > 1012 VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 Ω 9 VIO = 500 V at TS = 150°C > 10 Pollution degree 2 UL 1577 VISO (1) (2) (3) (4) (5) 6 Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production) 5700 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 ISO5852S-Q1 www.ti.com SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 7.7 Safety-Related Certifications VDE CSA Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):200612 and DIN EN 61010-1 (VDE 0411-1):2011-07 Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1 UL Recognized under UL 1577 Component Recognition Program CQC TUV Certified according to GB4943.1-2011 Certified according to EN 61010-1:2010 (3rd Ed) and EN 609501:2006/A11:2009/A1:2010/ A12:2011/A2:2013 Isolation Rating of 5700 VRMS; Reinforced insulation per CSA 60950-1Reinforced Insulation 07+A1+A2 and IEC Maximum Transient 60950-1 (2nd Ed.), 800 isolation voltage, 8000 VRMS max working VPK; voltage (pollution Single Protection, 5700 Maximum surge isolation degree 2, material VRMS (1) voltage, 8000 VPK, group I) ; Maximum repetitive peak 2 MOPP (Means of isolation voltage, 2121 Patient Protection) per VPK CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage 5700 VRMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to Reinforced Insulation, working voltage of 600 VRMS Altitude ≤ 5000m, Tropical 5700 VRMS Reinforced climate, 400 VRMS insulation per maximum working voltage EN 609501:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 VRMS Certification completed Certificate number: 40040142 Certification completed Certificate number: CQC16001141761 (1) Certificate planned Certification completed File number: E181974 Certification completed Client ID number: 77311 Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577. 7.8 Safety Limiting Values Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current PS Safety input, output, or total power TS Maximum ambient safety temperature (1) TEST CONDITIONS MIN TYP MAX RθJA = 99.6°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2 456 RθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2 346 RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2 228 RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C, see Figure 2 84 RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C, see Figure 2 42 RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C, see Figure 3 255 (1) 150 UNIT mA mW °C Input, output, or the sum of input and output power should not exceed this value The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 7 ISO5852S-Q1 SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7.9 Electrical Characteristics Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.25 V VOLTAGE SUPPLY VIT+(UVLO1) Positive-going UVLO1 threshold-voltage input side (VCC1 – GND1) VIT-(UVLO1) Negative-going UVLO1 threshold-voltage input side (VCC1 – GND1) VHYS(UVLO1) UVLO1 Hysteresis voltage (VIT+ – VIT–) input side 0.2 VIT+(UVLO2) Positive-going UVLO2 threshold-voltage output side (VCC2 – GND2) 12 VIT–(UVLO2) Negative-going UVLO2 threshold-voltage output side (VCC2 – GND2) VHYS(UVLO2) UVLO2 hysteresis voltage (VIT+ – VIT–) output side IQ1 Input-supply quiescent current 2.8 4.5 mA IQ2 Output-supply quiescent current 3.6 6 mA 1.7 9.5 V V 13 V 11 V 1 V LOGIC I/O VIT+(IN,RST) Positive-going input-threshold voltage (IN+, IN–, RST) VIT–(IN,RST) Negative-going input-threshold voltage (IN+, IN–, RST) VHYS(IN,RST) Input hysteresis voltage (IN+, IN–, RST) IIH High-level input leakage at (IN+) (1) IN+ = VCC1 IIL Low-level input leakage at (IN–, RST) (2) IN– = GND1, RST = GND1 IPU Pullup current of FLT, RDY V(RDY) = GND1, V(FLT) = GND1 V(OL) Low-level output voltage at FLT, RDY I(FLT) = 5 mA 0.7 × VCC1 0.3 × VCC1 V V 0.15 × VCC1 V 100 µA -100 µA 100 µA 0.2 V 2 V GATE DRIVER STAGE V(OUTPD) Active output pulldown voltage I(OUTH/L) = 200 mA, VCC2 = open VOUTH High-level output voltage I(OUTH) = –20 mA VOUTL Low-level output voltage I(OUTL) = 20 mA I(OUTH) High-level output peak current IN+ = high, IN– = low, V(OUTH) = VCC2 - 15 V 1.5 2.5 A I(OUTL) Low-level output peak current IN+ = low, IN– = high, V(OUTL) = VEE2 + 15 V 3.4 5 A I(OLF) Low-level output current during fault condition VCC2 – 0.5 VCC2 – 0.24 VEE2 + 13 V VEE2 + 50 130 mV mA ACTIVE MILLER CLAMP V(CLP) Low-level clamp voltage I(CLP) = 20 mA I(CLP) Low-level clamp current V(CLAMP) = VEE2 + 2.5 V V(CLTH) Clamp threshold voltage VEE2 + 0.015 VEE2 + 0.08 V 1.6 2.5 3.3 A 1.6 2.1 2.5 V SHORT CIRCUIT CLAMPING V(CLP-OUTH) Clamping voltage (VOUTH – VCC2) IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA 1.1 1.3 V V(CLP-OUTL) Clamping voltage (VOUTL – VCC2) IN+ = high, IN– = low, tCLP = 10 µs, I(OUTL) = 500 mA 1.3 1.5 V V(CLP-CLP) Clamping voltage (VCLP – VCC2) IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA 1.3 V(CLP-CLAMP) Clamping voltage at CLAMP IN+ = High, IN– = Low, I(CLP) = 20 mA 0.7 1.1 V V(CLP-OUTL) Clamping voltage at OUTL (VCLP – VCC2) IN+ = High, IN– = Low, I(OUTL) = 20 mA 0.7 1.1 V 0.58 mA V DESAT PROTECTION I(CHG) Blanking-capacitor charge current V(DESAT) – GND2 = 2 V 0.42 0.5 I(DCHG) Blanking-capacitor discharge current V(DESAT) – GND2 = 6 V 9 14 (1) (2) 8 mA IIH for IN–, RST pin is zero as they are pulled high internally IIL for IN+ is zero, as it is pulled low internally Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 ISO5852S-Q1 www.ti.com SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 Electrical Characteristics (continued) Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V MIN TYP MAX V(DSTH) DESAT threshold voltage with respect to GND2 PARAMETER TEST CONDITIONS UNIT 8.3 9 9.5 V V(DSL) DESAT voltage with respect to GND2, when OUTH or OUTL is driven low 0.4 1 V 7.10 Switching Characteristics Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Output-signal rise time at OUTH CLOAD = 1 nF 12 18 35 ns tf Output-signal fall time at OUTL CLOAD = 1 nF 12 20 37 ns tPLH, tPHL Propagation Delay CLOAD = 1 nF 76 110 ns tsk-p Pulse skew |tPHL – tPLH| CLOAD = 1 nF 20 ns (1) ns 30 40 ns 553 760 ns 2 3.5 μs See Figure 44, Figure 45, and Figure 46 tsk-pp Part-to-part skew CLOAD = 1 nF tGF (IN,/RST) Glitch filter on IN+, IN–, RST CLOAD = 1 nF tDS (90%) DESAT sense to 90% VOUTH/L delay CLOAD = 10 nF tDS (10%) DESAT sense to 10% VOUTH/L delay CLOAD = 10 nF tDS (GF) DESAT-glitch filter delay CLOAD = 1 nF (FLT) DESAT sense to FLT-low delay See Figure 46 tLEB Leading-edge blanking time See Figure 44 and Figure 45 tGF(RSTFLT) Glitch filter on RST for resetting FLT tDS (2) CI Input capacitance CMTI Common-mode transient immunity (1) (2) 30 20 330 310 400 300 VI = VCC1 / 2 + 0.4 × sin (2πft), f = 1 MHz, VCC1 = 5 V VCM = 1500 V, see Figure 47 ns 1.4 μs 480 ns 800 ns 2 100 120 pF kV/μs Measured at same supply voltage and temperature condition Measured from input pin to ground. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5852S-Q1 9 ISO5852S-Q1 SLLSEQ2A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7.11 Insulation Characteristics Curves 1.E+11 87.5% 1.E+9 Time to Fail (s) 1.E+8 1.E+7 1.E+6 1.E+5 1.E+4 1.E+3 VCC1 = 2.75 V VCC1 = 3.6 V VCC1 = 5.5 V VCC2 = 15 V VCC2 = 30 V 450 Safety Limiting Current (mA) 1.E+10 500 Safety Margin Zone: 1800 VRMS, 254 Years Operating Zone: 1500 VRMS, 135 Years TDDB Line (