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LM25122-Q1
SNVSAF0B – DECEMBER 2015 – REVISED MAY 2016
LM25122-Q1 Wide-Input Synchronous Boost Controller With Multiple Phase Capability
1 Features
2 Applications
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AEC-Q100 Qualified with the following results:
– Device Temperature Grade 1: -40°C to +125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Maximum Input Voltage : 42 V
Min Input Voltage : 3 V (4.5 V for startup)
Output Voltage up to 50 V
Bypass (VOUT = VIN) Operation
1.2 V Reference with ±1.0% Accuracy
Free-Run and Synchronizable Switching to 600
kHz
Peak Current Mode Control
Robust 3 A Integrated Gate Drivers
Adaptive Dead-Time Control
Optional Diode Emulation Mode
Programmable Cycle-by-Cycle Current Limit
Hiccup Mode Overload Protection
Programmable Line UVLO
Programmable Soft-Start
Thermal Shutdown Protection
Low Shutdown Quiescent Current: 9 μA
Programmable Slope Compensation
Programmable Skip Cycle Mode Reduces
Standby Power
Allows External VCC Supply
Inductor DCR Current Sensing Capability
Multiphase Capability
Thermally Enhanced 20-Pin HTSSOP
12-V, 24-V, and 48-V Power Systems
Automotive Start-Stop
Audio Power Supply
High Current Boost Power Supply
3 Description
The LM25122 is a multiphase capable synchronous
boost
controller
intended
for
high-efficiency
synchronous boost regulator applications. The control
method is based upon peak current mode control.
Current mode control provides inherent line feedforward, cycle-by-cycle current limiting and ease of
loop compensation.
The switching frequency is programmable up to 600
kHz. Higher efficiency is achieved by two robust Nchannel MOSFET gate drivers with adaptive deadtime control. A user-selectable diode emulation mode
also enables discontinuous mode operation for
improved efficiency at light load conditions.
An internal charge pump allows 100% duty cycle for
high-side synchronous switch (Bypass operation). A
180º phase shifted clock output enables easy multiphase interleaved configuration. Additional features
include thermal shutdown, frequency synchronization,
hiccup mode current limit and adjustable line
undervoltage lockout.
Device Information(1)
PART NUMBER
LM25122-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
VOUT
VIN
+
VCC
BST
SW
LO
CSN
HO
CSP
COMP
VIN
UVLO
SLOPE
FB
RES
SS
SYNCIN/RT
MODE
SYNCOUT
PGND
AGND
OPT
LM25122
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25122-Q1
SNVSAF0B – DECEMBER 2015 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
5
5
5
6
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 33
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 41
11 Device and Documentation Support ................. 42
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
Changes from Revision A (December 2015) to Revision B
Page
•
Added Automotive ESD Features .......................................................................................................................................... 1
•
Added second equation and paragraph .............................................................................................................................. 19
•
Changed equation ................................................................................................................................................................ 19
Changes from Original (December 2015) to Revision A
•
2
Page
Product Preview to Production Data Release ....................................................................................................................... 1
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SNVSAF0B – DECEMBER 2015 – REVISED MAY 2016
5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP With Exposed Pad
Top View
SYNCOUT
1
20
BST
OPT
2
19
HO
CSN
3
18
SW
CSP
4
17
VCC
VIN
5
16
LO
EP
UVLO
6
15
PGND
SS
7
14
RES
SYNCIN/RT
8
13
MODE
AGND
9
12
SLOPE
FB
10
11
COMP
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
AGND
9
G
Analog ground connection. Return for the internal voltage reference and analog circuits.
BST
20
P
High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap
diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the highside N-channel MOSFET gate and should be placed as close to controller as possible. An internal
BST charge pump will supply 200-µA current into bootstrap capacitor for bypass operation.
COMP
11
O
Output of the internal error amplifier. The loop compensation network should be connected between
this pin and the FB pin.
CSN
3
I
Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor.
CSP
4
I
Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense
resistor.
FB
10
I
Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin
sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. The controller is
configured as slave mode if the FB pin voltage is above 2.7 V at initial power-on.
HO
19
O
High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous
N-channel MOSFET switch through a short, low inductance path.
LO
16
O
Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel
MOSFET switch through a short, low inductance path.
MODE
13
I
Switching mode selection pin. 700-kΩ pullup and 100-kΩ pulldown resistor internal hold MODE pin
to 0.15 V as a default. By adding external pullup or pulldown resistor, MODE pin voltage can be
programmed. When MODE pin voltage is greater than 1.2 V diode emulation mode threshold,
forced PWM mode is enabled, allowing current to flow in either direction through the high-side Nchannel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode
emulation mode. Skip cycle comparator is activated as a default. If MODE pin is grounded, the
controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered
in normal operation, this enables pulse skipping operation at light load.
OPT
2
I
Clock synchronization selection pin. This pin also enables/disables SYNCOUT related with
master/slave configuration. The OPT pin should not be left floating.
PGND
15
G
Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the
source terminal of the low-side N-channel MOSFET switch.
RES
14
O
The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay
during over load conditions. Connect directly to the AGND when hiccup mode operation is not
required.
(1)
G = Ground, I = Input, O = Output, P = Power
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Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
SLOPE
12
I
Slope compensation is programmed by a single resistor between SLOPE and the AGND.
SS
7
I
Soft-start programming pin. An external capacitor and an internal 10-μA current source set the ramp
rate of the internal error amplifier reference during soft-start.
SW
18
I/O
Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET
switch through short, low inductance paths.
SYNCIN/RT
8
I
The internal oscillator frequency is programmed by a single resistor between RT and the AGND.
The internal oscillator can be synchronized to an external clock by applying a positive pulse signal
into this SYNCIN pin. The recommended maximum internal oscillator frequency in master
configuration is 1.2 MHz which leads to 600 kHz maximum switching frequency.
SYNCOUT
1
O
Clock output pin. SYNCOUT provides 180º shifted clock output for an interleaved operation.
SYNCOUT pin can be left floating when it is not used. See Slave Mode and SYNCOUT section.
UVLO
6
I
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below
1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the
HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10-μA
current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external
UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC
17
P/O/I
VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
VIN
5
P/I
Supply voltage input source for the VCC regulator. Connect to input capacitor and source power
supply connection with short, low impedance paths.
EP
EP
N/A
Exposed pad of the package. No internal electrical connections. Should be soldered to the large
ground plane to reduce thermal resistance.
6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN, CSP, CSN
–0.3
50
V
BST to SW, FB, MODE, UVLO, OPT, VCC (2)
–0.3
15
V
SW
–5.0
60
V
BST
–0.3
75
V
SS, SLOPE, SYNCIN/RT
–0.3
7
V
CSP to CSN, PGND
–0.3
0.3
V
HO to SW
–0.3
BST to SW+0.3
V
LO
–0.3
VCC+0.3
V
COMP, RES, SYNCOUT
–0.3
7
V
Thermal
Junction Temperature
–40
150
ºC
Tstg
Storage temperature
–55
150
°C
Input
Output (3)
(1)
(2)
(3)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless
otherwise specified, all voltages are referenced to AGND pin.
See Application Information when input supply voltage is less than the VCC voltage.
All output pins are not specified to have an external voltage applied.
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SNVSAF0B – DECEMBER 2015 – REVISED MAY 2016
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner pins (1, 10, 11,
and 20)
±1000
Other pins
±1000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Input supply voltage (2)
VIN
Low-side driver bias voltage
VCC
High-side driver bias voltage
BST to SW
Current sense common mode
range (2)
CSP, CSN
Switch node voltage
SW
Junction temperature
TJ
(1)
(2)
NOM
4.5
MAX
UNIT
42
V
14
V
3.8
14
V
3
42
–40
V
50
V
125
ºC
Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not
guarantee specific performance limits.
Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3.0 V after start-up, assuming VIN
voltage is supplied from an available external source.
6.4 Thermal Information
LM25122-Q1
THERMAL METRIC
(1)
PWP
(HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
36.0
ºC/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.1
ºC/W
RθJB
Junction-to-board thermal resistance
16.8
ºC/W
ψJT
Junction-to-top characterization parameter
0.4
ºC/W
ψJB
Junction-to-board characterization parameter
16.7
ºC/W
ψJCbot
Junction-to-case (bottom) thermal resistance
1.7
ºC/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VUVLO = 0 V
9
17
µA
VUVLO = 2 V, non-switching
4
5
mA
7.6
8.3
V
0.25
V
VIN SUPPLY
ISHUTDOWN VIN shutdown current
IBIAS
VIN operating current (exclude
the current into RT resistor)
VCC REGULATOR
VCC(REG)
VCC regulation
VCC dropout (VIN to VCC)
IVCC
No load
6.9
VVIN = 4.5 V, no external load
VVIN = 4.5 V, IVCC = 25 mA
0.28
VVCC = 0 V
VCC operating current (exclude
the current into RT resistor)
VVCC = 8.3 V
3.5
5
mA
VVCC = 12 V
4.5
8
mA
4.0
4.1
V
3.7
V
VCC undervoltage threshold
3.9
62
V
VCC sourcing current limit
VCC rising, VVIN = 4.5 V
50
0.5
VCC falling, VVIN = 4.5 V
VCC undervoltage hysteresis
mA
0.385
V
UNDERVOLTAGE LOCKOUT
UVLO threshold
UVLO rising
UVLO hysteresis current
VUVLO = 1.4 V
UVLO standby enable threshold
UVLO rising
1.17
1.20
1.23
V
7
10
13
µA
0.3
0.4
0.5
V
0.1
0.125
V
1.24
1.28
V
UVLO standby enable hysteresis
MODE
Diode emulation mode threshold
MODE rising
1.20
Diode emulation mode hysteresis
0.1
Default MODE voltage
Default skip cycle threshold
Skip cycle hysteresis
145
155
COMP rising, measured at COMP
1.290
COMP falling, measured at COMP
1.245
Measured at COMP
V
170
mV
V
V
40
mV
ERROR AMPLIFIER
VREF
FB reference voltage
Measured at FB, VFB= VCOMP
FB input bias current
VFB= VREF
VOH
COMP output high voltage
VOL
COMP output low voltage
AOL
DC gain
fBW
Unity gain bandwidth
Slave mode threshold
1.188
1.200
1.212
5
ISOURCE = 2 mA, VVCC = 4.5 V
2.75
ISOURCE = 2 mA, VVCC = 12 V
3.40
V
V
ISINK = 2 mA
0.25
FB rising
V
nA
V
80
dB
3
MHz
2.7
3.4
V
450
500
kHz
OSCILLATOR
fSW1
Switching frequency 1
RT = 20 kΩ
400
RT output voltage
1.2
RT sync rising threshold
RT rising
RT sync falling threshold
RT falling
Minimum sync pulse width
2.5
1.6
V
2.9
2.0
V
V
100
ns
SYNCOUT
SYNCOUT high-state voltage
ISYNCOUT = –1 mA
SYNCOUT low-state voltage
ISYNCOUT = 1 mA
3.3
4.3
0.15
V
0.25
V
OPT
6
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Electrical Characteristics (continued)
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
Synchronization selection
threshold
TEST CONDITIONS
OPT rising
MIN
TYP
MAX
UNIT
2.0
3.0
4.0
V
SLOPE COMPENSATION
SLOPE output voltage
VSLOPE
Slope compensation amplitude
1.17
1.20
1.23
V
RSLOPE = 20 kΩ, fSW = 100 kHz, 50%
duty cycle, TJ = –40ºC to +125ºC
1.375
1.650
1.925
V
RSLOPE= 20 kΩ, fSW= 100 kHz, 50% duty
cycle, TJ = 25ºC
1.400
1.650
1.900
V
7.5
10
12
µA
SOFT-START
ISS-SOURCE SS current source
VSS = 0 V
SS discharge switch RDS-ON
13
Ω
PWM COMPARATOR
tLO-OFF
tON-MIN
Forced LO off-time
Minimum LO on-time
COMP to PWM voltage drop
VVCC = 5.5 V
330
400
ns
VVCC = 4.5 V
560
750
ns
RSLOPE = 20 kΩ
150
ns
RSLOPE = 200 kΩ
300
ns
TJ = –40ºC to +125ºC
0.95
1.10
1.25
V
TJ = 25ºC
1.00
1.10
1.20
V
CSP to CSN, TJ = –40ºC to +125ºC
65.5
75.0
87.5
mV
CSP to CSN, TJ = 25ºC
67.0
75.0
86.0
mV
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT
VCS-TH1
VCS-ZCD
Cycle-by-cycle current limit
threshold
Zero cross detection threshold
CSP to CSN, rising
CSP to CSN, falling
7
0.5
6
mV
12
mV
Current sense amplifier gain
10
V/V
ICSP
CSP input bias current
12
µA
ICSN
CSN input bias current
11
µA
Bias current matching
ICSP - ICSN
CS to LO delay
Current sense / current limit delay
–1.75
1
3.75
150
µA
ns
HICCUP MODE RESTART
VRES
VHCP-
Restart threshold
Hiccup counter upper threshold
UPPER
RES rising
1.15
1.20
1.25
V
RES rising
4.2
V
RES rising,
VVIN = VVCC = 4.5 V
3.6
V
RES falling
2.15
V
Hiccup counter lower threshold
RES falling,
VVIN = VVCC = 4.5 V
1.85
V
IRESSOURCE1
RES current source1
Fault-state charging current
IRES-SINK1
RES current sink1
Normal-state discharging current
IRESSOURCE2
RES current source2
Hiccup mode off-time charging current
IRES-SINK2
RES current sink2
Hiccup mode off-time discharging current
VHCPLOWER
Hiccup cycle
RES discharge switch RDS-ON
Ratio of hiccup mode off-time to
restart delay time
20
30
40
µA
5
µA
10
µA
5
µA
8
Cycles
40
Ω
122
HO GATE DRIVER
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Electrical Characteristics (continued)
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
0.15
0.24
V
IHO = 100 mA, VOLH = VHO –VSW
0.1
0.18
V
HO rise time (10% to 90%)
CLOAD = 4700 pF, VBST = 12 V
25
ns
HO fall time (90% to 10%)
CLOAD = 4700 pF, VBST = 12 V
20
ns
VHO = 0 V, VSW = 0 V, VBST = 4.5 V
0.8
A
VHO = 0 V, VSW = 0 V, VBST = 7.6 V
1.9
A
VHO = VBST = 4.5 V
1.9
A
VHO = VBST= 7.6 V
3.2
A
µA
VOHH
HO high-state voltage drop
IHO = –100 mA, VOHH = VBST –VHO
VOLH
HO low-state voltage drop
IOHH
Peak HO source current
IOLH
Peak HO sink current
IBST
BST charge pump sourcing
current
BST charge pump regulation
VVIN = VSW = 9.0 V , VBST - VSW = 5.0 V
100
200
BST to SW, IBST= –70 μA,
VVIN = VSW = 9.0 V
5.3
6.2
6.75
V
7
8.5
9
V
2.0
3.0
3.5
V
30
45
µA
BST to SW, IBST = –70 μA,
VVIN = VSW = 12 V
BST to SW undervoltage
BST DC bias current
MIN
VBST - VSW = 12 V, VSW = 0 V
LO GATE DRIVER
VOHL
LO high-state voltage drop
ILO = –100 mA, VOHL = VVCC –VLO
0.15
0.25
V
VOLL
LO low-state voltage drop
ILO = 100 mA, VOLL = VLO
0.1
0.17
V
LO rise time (10% to 90%)
CLOAD = 4700 pF
25
ns
LO fall time (90% to 10%)
CLOAD = 4700 pF
20
ns
VLO = 0 V, VVCC = 4.5 V
0.8
A
VLO = 0 V
2.0
A
VLO = VVCC = 4.5 V
1.8
A
VLO = VVCC
3.2
A
IOHL
Peak LO source current
IOLL
Peak LO sink current
SWITCHING CHARACTERISTICS
tDLH
LO fall to HO rise delay
No load, 50% to 50%
50
80
115
ns
tDHL
HO fall to LO rise delay
No load, 50% to 50%
60
80
105
ns
Thermal shutdown
Temperature rising
THERMAL
TSD
Thermal shutdown hysteresis
8
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165
ºC
25
ºC
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6.6 Typical Characteristics
6.00
5.00
4.00
3.00
LO PEAK CURRENT [A]
HO PEAK CURRENT [A]
5.00
SINK
2.00
SOURCE
1.00
4.00
SINK
3.00
SOURCE
2.00
1.00
0.00
0.00
4
5
6
7
8
9
10
11
12
13
VBST - VSW [V]
14
4
5
VVIN = 12 V
7
VSW = 0 V
9
11
12
13
14
C001
Figure 2. LO Peak Current vs VVCC
90.00
95
80.00
90
70.00
85
Dead-time [ns]
100
60.00
10
VVIN = 12 V
100.00
tDHL
50.00
40.00
30.00
8
VVCC [V]
Figure 1. HO Peak Current vs VBST - VSW
Dead-time [ns]
6
C001
tDLH
80
75
70
tDLH
65
20.00
60
10.00
55
0.00
tDHL
50
4
5
6
7
8
9
10
11
VVCC [V]
VVIN = 12 V
VSW = 12 V
12
-50
-25
0
CLOAD = 2600pF
25
50
75
100
125
Temperature [ƒC]
C001
150
C001
1 V to 1 V
Figure 3. Dead Time vs VVCC
Figure 4. Dead Time vs Temperature
100.0
20
90.0
15
70.0
tDHL
ISHUTDOWN [PA]
Dead-time [ns]
80.0
60.0
50.0
tDLH
40.0
30.0
10
5
20.0
10.0
0.0
0
0
10
20
30
40
VSW [V]
VVIN = 12 V
VVCC = 7.6 V
CLOAD = 2600pF
50
60
-50
C001
-25
0
25
50
75
100
125
Temperature [ƒC]
150
C001
1 V to 1 V
Figure 5. Dead Time vs VSW
Figure 6. ISHUTDOWN vs Temperature
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Typical Characteristics (continued)
8
8
No load
6
VVCC [V]
VVCC [V]
6
4
4
2
2
0
0
No load
0
10
20
30
40
50
60
70
0
80
IVCC [mA]
1
2
3
4
5
6
8
9
10
11
12
13
14
C001
Figure 8. VVCC vs VVIN
Figure 7. VVCC vs IVCC
40
15
180
ACL=101, COMP unload
30
ICSP
PHASE
20
90
10
45
0
10000
100000
FREQUENCY [Hz]
10
ICSN
5
0
GAIN
-10
1000
ICSP, ICSN [PA]
135
PHASE [°]
GAIN [dB]
7
VVIN [V]
C001
0
-45
10000000
1000000
-50
-25
0
25
50
75
100
125
Temperature [ƒC]
C002
Figure 9. Error Amp Gain and Phase
vs Frequency
150
C001
Figure 10. ICSP, ICSN vs Temperature
15.0
300
280
BST Charging Current [PA]
IBST = -70uA
VBST-SW [V]
10.0
5.0
VVIN=VSW=9V
260
240
220
200
180
160
140
120
100
0.0
4
9
14
VSW [V]
19
-50
C001
Figure 11. VBST-SW vs VSW
10
-25
0
25
50
75
100
Temperature [ƒC]
125
150
C001
Figure 12. IBST vs Temperature
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Typical Characteristics (continued)
80
90
VVIN=VCSP
VCS-TH1 [mV]
VCS-TH1 [mV]
85
75
80
75
70
65
60
70
4
5
6
7
8
9
10
11
12
VVIN [V]
-50
-25
0
25
50
75
100
125
Temperature [ƒC]
C001
Figure 13. VCS-TH1 vs VVIN
150
C001
Figure 14. VCS-TH1 vs Temperature
12.00
11.00
10.00
VSW = 12V
9.00
VBST-SW [V]
8.00
7.00
6.00
5.00
VSW = 9V
4.00
3.00
VVIN = VSW
IBST = -70uA
2.00
1.00
0.00
-50
-25
0
25
50
75
100
Temperature [ƒC]
125
150
C001
Figure 15. VBST-SW vs Temperature
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7 Detailed Description
7.1 Overview
The LM25122 wide input range synchronous boost controller features all of the functions necessary to implement
a highly efficient synchronous boost regulator. The regulator control method is based upon peak current mode
control. Peak current mode control provides inherent line feed-forward and ease of loop compensation. This
highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive
dead-time control. The switching frequency is user programmable up to 600 kHz set by a single resistor or
synchronized to an external clock. The LM25122’s 180º shifted clock output enables easy multi-phase
configuration.
The control mode of high-side synchronous switch can be configured as either forced PWM (FPWM) or diode
emulation mode. Fault protection features include cycle-by-cycle current limiting, hiccup mode over load
protection, thermal shutdown and remote shutdown capability by pulling down the UVLO pin. The UVLO input
enables the controller when the input voltage reaches a user selected threshold, and provides a tiny 9 μA
shutdown quiescent current when pulled low. The device is available in 20-pin HTSSOP package featuring an
exposed pad to aid in thermal dissipation.
7.2 Functional Block Diagram
VIN
RS
LIN
CIN
CSP
VIN
10uA
CSN
LM25122
1.2V
RUV2
+
RUV1
STANDBY
+
UVLO
A=10
0.4V/0.3V
+
VIN
CS
AMP
SHUTDOWN
SLOPE
RSLOPE
BST Charge Pump
SLOPE
Generator
9
VSLOPE =
COMP
+
BST
QH
VSENSE2
1.2 V
+
-
- ZCD threshold
LEVEL SHIFT
DIODE EMULATION
ERR
AMP
C/L
Comparator
+
SS
SW
COUT
VCC
PWM
Comparator
10uA
S
Q
PWM
QL
R Q
1.2V
RFB2
Skip Cycle
Comparator
700k
20mV
+
MODE
100k
CLK
LO
ADAPTIVE
TIMER
+
-
CSS
VOUT
CBST
+
-
FB
1.2V
HO
+
750mV
+
CVCC
DBST
VSENSE1
6 u 10
RSLOPE u fSW
CHF
CCOMP RCOMP
VCC
VCC
Regulator
1.2V
-
+
+
-
Diode
Emulation
Comparator
Diode
Emulation
OPT
30uA
40mV
Hysteresis
10uA
RESTART
TIMER
CLK
Clock Generator
/SYNC Detector
SYNCIN/RT
SYNCOUT
RFB1
RES
fCLK / 2
or
fCLK
5uA
CRES
AGND PGND
RT
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The LM25122 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4-V UVLO
standby enable threshold, the LM25122 is in the shutdown mode with all functions disabled. The shutdown
comparator provides 0.1 V of hysteresis to avoid chatter during transition. If the UVLO pin voltage is greater than
0.4 V and below 1.2 V during power up, the controller is in standby mode with the VCC regulator operational and
no switching at the HO and LO outputs. This feature allows the UVLO pin to be used as a remote shutdown
function by pulling the UVLO pin down below the UVLO standby enable threshold with an external open collector
or open drain device.
VIN
UVLO Hysteresis
Current
RUV2
RUV1
STANDBY
UVLO
UVLO
Threshold
UVLO Standby
Enable Threshold
SHUTDOWN
+
+
STANDBY
SHUTDOWN
Figure 16. UVLO Remote Standby and Shutdown Control
If the UVLO pin voltage is above the 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV threshold, a
startup sequence begins. UVLO hysteresis is accomplished with an internal 10-μA current source that is switched
on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds 1.2 V, the
current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below
the 1.2-V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. In
addition to the UVLO hysteresis current source, a 5-μs deglitch filter on both rising and falling edge of UVLO
toggling helps preventing chatter upon power up or down.
An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input
operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater
than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO
pin is 15 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not
be left floating. The values of RUV1 and RUV2 can be determined from Equation 1 and Equation 2.
VHYS
RUV2
ª: º
10 $ ¬ ¼
(1)
1.2V u RUV2
RUV1
ª: º
VIN(STARTUP) 1.2V ¬ ¼
(2)
where
•
•
VHYS is the desired UVLO hysteresis
VIN(STARTUP) is the desired startup voltage of the regulator during turn-on.
Typical shutdown voltage during turn-off can be calculated as follows:
VIN(SHUTDOWN) VIN(STARTUP) VHYS [V]
(3)
7.3.2 High Voltage VCC Regulator
The LM25122 contains an internal high voltage regulator that provides typical 7.6 V VCC bias supply for the
controller and N-channel MOSFET drivers. The input of VCC regulator, VIN, can be connected to an input
voltage source as high as 42 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V.
When the input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage.
The output of the VCC regulator is current limited at 50 mA minimum.
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Feature Description (continued)
Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. The
recommended capacitance range for the VCC capacitor is 1.0 μF to 47 μF and is recommended to be at least 10
times greater than CBST value. When operating with a VIN voltage less than 6 V, the value of VCC capacitor
should be 4.7 µF or greater.
The internal power dissipation of the LM25122 device can be reduced by supplying VCC from an external supply.
If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC
bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 17.
External VCC Supply
VCC
LM25122
CVCC
Figure 17. External Bias Supply when 9 V
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