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LM53602-Q1, LM53603-Q1
SNVSA42B – JUNE 2015 – REVISED MAY 2016
LM53603-Q1 (3 A), LM53602-Q1 (2 A) 3.5 V to 36 V Wide-VIN Synchronous 2.1 MHz StepDown Converters for Automotive Applications
1 Features
2 Applications
•
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•
1
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The LM53603-Q1, LM53602-Q1 are available as
AEC-Q1-Qualified Automotive Grade Products
With Following Results:
– Device Temperature Grade 1: -40°C to +125°C
Ambient Operating Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C4B
3 A or 2 A maximum load current
Input Voltage Range from 3.5 V to 36 V:
Transients to 42 V
Output Voltage Options: 5 V, 3.3 V, ADJ
2.1 MHz Fixed Switching Frequency
±2% Output Voltage Tolerance
–40°C to 150°C Junction Temperature Range
1.7 µA Shutdown Current (typical)
24 µA Input Supply Current at No Load (typical)
No external Feed-back Divider Required for 5 V or
3.3 V output
Reset Output With Filter and Delay
Automatic Light Load Mode for Improved
Efficiency
User-Selectable Forced PWM mode (FPWM)
Built-in Loop Compensation, Soft-start, Current
Limit, Thermal Shutdown, UVLO, and External
Frequency Synchronization
Thermally Enhanced 16-lead Package:
5 mm x 4.4 mm x 1 mm
Navigation/GPS
Instrument Cluster
ADAS, Infotainment, HUD
3 Description
The LM53603-Q1, LM53602-Q1 buck regulators are
specifically designed for automotive applications,
providing an output voltage of 5 V or 3.3 V (with ADJ
option) at 3 A or 2 A, from an input voltage of up to
36 V. Advanced high-speed circuitry allows the
device to regulate from an input of up to 20 V, while
providing an output of 5 V at a switching frequency of
2.1 MHz. The innovative architecture allows the
device to regulate a 3.3 V output from an input
voltage of only 3.5 V. All aspects of this product are
optimized for the automotive customer. An input
voltage range up to 36 V, with transient tolerance up
to 42 V, eases input surge protection design. An open
drain reset output, with filtering and delay, provides a
true indication of system status. This feature negates
the requirement for an additional supervisory
component, saving cost and board space. Seamless
transition between PWM and PFM modes, along with
a no-load operating current of only 24 µA, ensures
high efficiency and superior transient response at all
loads.
Device Information(1)
PART NUMBER
LM53603-Q1
LM53602-Q1
PACKAGE
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
VIN
CIN
LM53603
EN
RESET
CBOOT
FPWM
VOUT
COUT
CBOOT
VCC
CVCC
Automotive Power Supply with 5 V, 3 A Output
L
SW
Rbias
BIAS
CBIAS
SYNC
AGND
FB
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM53602-Q1, LM53603-Q1
SNVSA42B – JUNE 2015 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
5
5
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
System Characteristics .............................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................ 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Applications ................................................ 18
9.3 Do's and Don't's ...................................................... 28
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
34
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2015) to Revision B
Page
•
Added Automotive Features .................................................................................................................................................. 1
•
changed representation of RESET threshold for clarity (physical parameter unchanged) .................................................... 6
•
added CFF recommendation table for ADJ version ............................................................................................................ 20
•
Corrected saturation current for some of the recommended inductors in the table "Recommended Inductors" ................ 22
•
Added recommendation for CVCC: use of X7R component is highly recommended ......................................................... 22
•
Added Cboot recommended rating of 10V in the CBOOT section ...................................................................................... 22
•
added power dissipation curve for 5Vout and 3.3Vout ........................................................................................................ 23
•
added layout recommendation for CVCC and CBIAS ......................................................................................................... 30
Changes from Original (June 2015) to Revision A
Page
•
Changed - Thermal Information, Board drawing on Page 1, Power Dissipation curves, RESET thresholds, maximum
recommended distances for VCC and Bias capacitors and added in a table for Cff. ........................................................... 1
•
Changed product preview to full data sheet .......................................................................................................................... 1
2
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SNVSA42B – JUNE 2015 – REVISED MAY 2016
5 Device Comparison Table
PART NUMBER
PACKAGE
MAXIMUM OUTPUT CURRENT
LM53603-Q1
HTSSOP (16)
3A
LM53602-Q1
HTSSOP (16)
2A
6 Pin Configuration and Functions
PWP Package
16-Lead HTSSOP
Top View
SW
1
16
PGND
SW
2
15
PGND
CBOOT
3
14
N/C
VCC
4
13
VIN
BIAS
5
12
VIN
SYNC
6
11
EN
FPWM
7
10
AGND
RESET
8
9
EP
(17)
FB
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
SW
1,2
P
Regulator switch node. Connect to power inductor. Connect pins 1 and 2 directly together at the PCB.
CBOOT
3
P
Bootstrap supply input for gate drivers. Connect a high quality 470 nF capacitor from this pin to SW.
VCC
4
O
Internal 3.15 V regulator output. Used as supply to internal control circuits. Do not connect to any
external loads. Can be used as logic supply for control inputs. Connect a high quality 3.3 µF capacitor
from this pin to GND.
BIAS
5
P
Input to internal voltage regulator. Connect to output voltage point. Do not ground. Connect a high
quality 0.1 µF capacitor from this pin to GND.
SYNC
6
I
Synchronization input to regulator. Used to synchronize the regulator switching frequency to the system
clock. When not used connect to GND; do not float.
FPWM
7
I
Mode control input to regulator. High = forced PWM (FPWM). Low = auto mode; automatic transition
between PFM and PWM. Do not float.
RESET
8
O
Open drain reset output. Connect to suitable voltage supply through a current limiting resistor. High =
power OK. Low = fault. RESET will go low when EN = low.
FB
9
I
Feedback input to regulator. Connect to output voltage sense point for fixed 5 V and 3.3 V output.
Connect to feedback divider tap point for ADJ option. Do not float or ground.
AGND
10
G
Analog ground for regulator and system. All electrical parameters are measured with respect to this pin.
Connect to EP and PGND on PCB.
EN
11
I
Enable input to the regulator. High = ON. Low = OFF. Can be connected directly to VIN. Do not float.
VIN
12, 13
P
Input supply to the regulator. Connect a high quality bypass capacitor(s) from this pin to PGND.
Connect pins 12 and 13 directly together at the PCB.
N/C
14
-
This pin has no connection to the device.
15, 16
G
Power ground to internal low side MOSFET. Connect to AGND and system ground. Connect pins 15
and 16 directly together at the PCB.
17
G
Exposed die attach paddle. Connect to ground plane for adequate heat sinking and noise reduction.
PGND
EP
(1)
O = Output, I = Input, G = Ground, P = Power
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SNVSA42B – JUNE 2015 – REVISED MAY 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN to AGND, PGND (2)
PARAMETER
–0.3
40
V
(3)
SW to AGND, PGND
–0.3
VIN + 0.3
V
CBOOT to SW
–0.3
3.6
V
EN to AGND, PGND (2)
–0.3
40
V
BIAS to AGND, PGND
–0.3
16
V
FB to AGND, PGND : fixed 5 V and 3.3 V
–0.3
16
V
FB to AGND, PGND : ADJ
–0.3
5.5
V
RESET to AGND, PGND
–0.3
8
V
SYNC, FPWM, to AGND, PGND
–0.3
5.5
V
VCC to AGND, PGND
–0.3
4.2
V
RESET Pin Current (4)
–0.1
1.2
mA
AGND to PGND (5)
–0.3
0.3
V
Storage temperature, Tstg
–40
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Values given
are D.C.
A maximum of 42 V can be sustained at this pin for a duration of ≤ 500 ms at a duty cycle of ≤ 0.01%.
Transients on this pin, not exceeding –3 V or +40 V, can be tolerated for a duration of ≤ 100 ns. For transients between 40 V and 42 V,
see note (2).
Positive current flows into this pin.
A transient voltage of ±2 V can be sustained for ≤1 µs.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
4
Electrostatic discharge
VIN, SW, CBOOT
±1500
EN, BIAS, RESET, FB,
SYNC, PWM, VCC
±2500
CBOOT, VCC, BIAS, SYNC,
Charged-device model (CDM), per AEC Q100-011 FPWM, EN, VIN
SW, RESET, FB, PGND
UNIT
V
±750
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SNVSA42B – JUNE 2015 – REVISED MAY 2016
7.3 Recommended Operating Conditions
over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) (1)
MIN
Input voltage
(2)
NOM
MAX
3.9
36
Output voltage : Fixed 5 V (3)
0
5
Output voltage : Fixed 3.3 V (3)
0
3.3
Output voltage adjustment range: ADJ (3) (4)
UNIT
V
V
V
3.3
6
V
Output current for LM53603-Q1
0
3
A
Output current for LM53602-Q1
0
2
A
RESET pin current
0
1
mA
–40
150
°C
Operating junction temperature (5)
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See System Characteristics for details of input voltage range.
Under no conditions should the output voltage be allowed to fall below zero volts.
The maximum recommended output voltage is 6 V. An extended output voltage range to 10 V is possible with changes to the typical
application schematic. Also, some system specifications will not be achieved for output voltages greater than 6 V. Consult the factory for
further information.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.4 Thermal Information
THERMAL METRIC
(1)
LM53603-Q1,
LM63602-Q1
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
42.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.6
°C/W
RθJB
Junction-to-board thermal resistance
16.2
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
16.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
The values given in this table are only valid for comparison with other packages and cannot be used for design purposes. These values
were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance
obtained in an actual application. For design information please see the Maximum Ambient Temperature section. For more information
about traditional and new thermal metrics, see the "Semiconductor and IC Package Thermal Metrics application report, SPRA953, and
the Using New Thermal Metrics applications report, SB VA025.
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SNVSA42B – JUNE 2015 – REVISED MAY 2016
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7.5 Electrical Characteristics
Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: VIN = 13.5 V.
PARAMETER
Initial reference voltage accuracy
for 5 V and 3.3 V options
VFB
VREF
Reference voltage for ADJ option
VIN-operate
MIN (1)
TEST CONDITIONS
Minimum input voltage to
operate (2)
TYP
MAX (1)
VIN = 3.8 V to 36 V, FPWM,
TJ = 25°C
–1%
1%
VIN = 3.8 V to 36 V, FPWM
–1.25%
1.25%
VIN = 3.8 V to 36 V, FPWM,
TJ = 25°C
0.993
1
1.007
VIN = 3.8 V to 36 V, FPWM,
TJ = -40°C to 125°C
0.99
1
1.01
UNIT
V
Rising
3.2
3.95
Falling
2.9
3.55
V
13
µA
2.8
µA
Hysteresis, below
0.34
IQ
Operating quiescent current;
measured at VIN pin. (3) (4)
VBIAS = 5 V,
TJ = -40°C to 125°C
ISD
Shutdown quiescent current;
measured at VIN pin.
IB
Current into the BIAS pin (4)
VBIAS = 5 V, FPWM = 3.3 V
47
IEN
Current into EN pin
VIN = VEN = 13.5 V
2.3
µA
Resistance from FB to AGND
5 V option
1.5
MΩ
Resistance from FB to AGND
3.3 V option
1
MΩ
Bias current into FB pin
ADJ option
10
nA
RESET upper threshold voltage
Rising, % of nominal Vout
105%
107%
110%
RESET lower threshold voltage
Falling, % of nominal Vout
92%
94%
96.5%
RESET lower threshold voltage
with respect to output voltage
Falling, % actual Vout
94.5%
95.7%
8
EN ≤ 0.4 V, TJ = 25°C
1.7
EN ≤ 0.4 V, TJ = 85°C
EN ≤ 0.4 V, TJ = 125°C
RFB
IFB
VRESET
VRESETHyst
VMIN
RESET hysteresis as a percent of
output voltage set point
Minimum input voltage for proper
RESET function
Low level RESET pin output
voltage
VOL
3.5
50 µA pull-up to RESET pin, VEN = 0 V,
TJ = 25°C
1.5
50 µA pull-up to RESET pin, Vin = 1.5
V, EN = 0 V
0.4
0.5 mA pull-up to RESET pin, Vin = 13.5
V, EN = 0 V
0.4
1 mA pull-up to RESET pin, Vin = 13.5
V, EN = 3.3 V
0.4
Rising
1.7
2
0.45
0.55
Enable input threshold voltage
VEN-off
Enable input threshold for full
shutdown (5)
EN input voltage required for complete
shutdown of the regulator, falling.
0.8
VLOGIC
Logic input levels on FPWM and
SYNC pins
VIH
1.5
IHS
High side switch current limit
(2)
(3)
(4)
(5)
6
µA
1.5%
VEN
(1)
78
Hysteresis, below
VIL
V
V
V
V
0.4
LM53603-Q1
4.5
6.2
LM53602-Q1
2.4
4.4
V
A
MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
This is the input voltage at which the device will start to operate ("rising"). The device will shutdown when the input voltage goes below
this value minus the hysteresis.
This is the current used by the device, open loop. It does not represent the total input current of the system when in regulation. See
"Isupply" in System Characteristics
The FB pin is set to 5.5 V for this test.
Below this voltage on the EN input, the device will shut down completely.
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SNVSA42B – JUNE 2015 – REVISED MAY 2016
Electrical Characteristics (continued)
Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: VIN = 13.5 V.
MIN (1)
TYP
MAX (1)
LM53603-Q1
3
3.6
4.3
LM53602-Q1
2
2.4
2.8
PARAMETER
TEST CONDITIONS
ILS
Low side switch current limit (6)
IZC
Zero-cross current limit
FPWM = 0 V
INEG
Negative current limit
FPWM = 3.3 V
-1.5
High side MOSFET resistance
135
290
Low side MOSFET resistance
60
125
2.1
2.35
Rdson
Power switch on-resistance
FSW
Switching frequency
FSYNC
Synchronizing frequency range
VCC
Internal VCC voltage
TSD
(6)
VIN = 3.8 V to 18 V
1.85
A
A
1.2
1.9
VBIAS = 3.3 V
Thermal shutdown thresholds
2.1
2.3
mΩ
MHz
MHz
3.15
V
162
Hysteresis, below
A
-0.02
VIN = 36 V
Rising
UNIT
178
18
°C
See the Current Limit section for an explanation of valley current limit.
7.6 System Characteristics
The following specifications apply only to the typical application circuit, shown in Figure 15 with nominal component values.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. The
parameters in this table are not guaranteed.
PARAMETER
VIN-MIN
TEST CONDITIONS
Minimum input voltage for Vout to
stay within ±2% of regulation. (1)
Line Regulation
Regulation
Load Regulation : Auto Mode
Load Regulation : FPWM Mode
ISUPPLY
VDROP
(1)
(2)
Input supply current when in
regulation. (2)
Dropout voltage (VIN – VOUT)
MIN
TYP
VOUT = 3.3 V, IOUT = 3 A
3.9
VOUT = 3.3 V, IOUT = 1 A
3.55
VOUT = 5 V, VIN = 8 V to 36 V, IOUT = 3 A
7
VOUT = 3.3 V, VIN = 6 V to 36 V, IOUT = 3
A
5
VOUT = 5 V, VIN = 12 V, IOUT = 10 µA to 3
A
77
VOUT = 3.3 V, VIN = 12 V, IOUT = 10 µA to
3A
53
VOUT = 5 V, VIN = 12 V, IOUT = 10 µA to 3
A
12
VOUT = 3.3 V, VIN = 12 V, IOUT = 10 µA to
3A
9
MAX
UNIT
V
mV
mV
mV
VIN = 13.5 V, VOUT = 3.3 V, IOUT = 0 A
24
VIN = 13.5 V, VOUT = 5 V, IOUT = 0 A
34
5 V Option:
VOUT = 4.95 V, IOUT = 3 A, FSW < 1.85
MHz
0.7
5 V Option:
VOUT = 5 V, IOUT = 3 A, FSW = 1.85 MHz
1.8
µA
V
3.3 V Option:
VOUT = 3.27 V, IOUT = 3 A, FSW < 1.85
MHz
0.65
3.3 V Option:
VOUT = 3.3 V, IOUT = 3 A, FSW = 1.85
MHz
1.8
This parameter is valid once the input voltage has risen above VIN-operate and the device has started up.
Includes current into the EN pin. See Input Supply Current section.
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7.7 Timing Requirements
Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: VIN = 13.5 V.
MIN
NOM
MAX
UNIT
TON
Minimum switch on-time, VIN = 20 V
50
80
TOFF
Minimum switch off-time, VIN = 3.8 V
125
200
ns
TRESET-act
Delay time to RESET high signal
2
3
4
ms
TRESET-filter
Glitch filter time for RESET function
12
25
45
µs
TSS
Soft-start time
1
2
3
ms
TEN
Turn-on delay, CVCC = 1 µF, Tj=25 °C (1)
0.7
0.8
ms
TW
Short circuit wait time. ("Hiccup" time)
5.5
(1)
8
ns
ms
This is the time from the rising edge of EN to the time that the soft-start ramp begins.
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7.8 Typical Characteristics
1.02
2.2
1.015
2.15
1.01
2.1
Frequency (MHz)
Refrence Voltage (V)
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. Specified temperatures are ambient.
1.005
1
0.995
2.05
2
1.95
0.99
1.9
0.985
1.85
0.98
-60
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
1.8
-60
140
-40
-20
Figure 1. Reference Voltage for ADJ Device
20
40
60
Temperature (°C)
80
100
120
140
D002
Figure 2. Switching Frequency
3.5
7
-40°C
27°C
125°C
-40°C
27°C
125°C
3.45
3.4
Valley Current Limit (A)
6
Peak Current Limit (A)
0
D001
5
4
3
2
3.35
3.3
3.25
3.2
3.15
3.1
1
3.05
0
3
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
Figure 3. High Side Peak Current Limit for LM53603-Q1
10
15
20
25
Input Voltage (V)
30
35
40
D005
Figure 4. Low Side Valley Current Limit for LM53603-Q1
25
0.4
-40°C
27°C
125°C
0.35
-40°C
25°C
125°C
20
0.3
Shutdown Current (µA)
Short Circuit Current (A)
5
D004
0.25
0.2
0.15
0.1
15
10
5
0.05
0
0
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
5
10
D006
Figure 5. Short Circuit Output Current for LM53603-Q1
15
20
25
Input Voltage (V)
30
35
40
D003
Figure 6. Shutdown Current
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8 Detailed Description
8.1 Overview
The LM5360x family of devices are synchronous current mode buck regulators designed specifically for the
automotive market. The regulator automatically switches between PWM and PFM depending on load. At heavy
loads the device operates in PWM at a switching frequency of 2.1 MHz. The regulator's oscillator can also be
synchronized to an external system clock. At input voltages above about 20 V, the switching frequency reduces
to maintain regulation during conditions of abnormally high battery voltage. At light loads the mode changes to
PFM, with diode emulation allowing DCM. This reduces input supply current and keeps the efficiency high. The
user can also choose to lock the mode in PWM (FPWM) so that the switching frequency remains constant
regardless of load.
A RESET flag is provided to indicate when the output voltage is near its regulation point. This feature includes
filtering and a delay before asserting. This helps to prevent false flag operation during output voltage transients.
Please note that, throughout this data sheet, references to the LM53603-Q1 apply equally to the LM53602-Q1.
The difference between the two devices is the maximum output current and specified MOSFET current limits.
8.2 Functional Block Diagram
SYNC
VCC BIAS
VIN
* = Not used in -ADJ
INT. REG.
BIAS
OSCILLATOR
ENABLE
LOGIC
EN
CBOOT
HS CURRENT
SENSE
1.0V
Reference
FB
ERROR
AMPLIFIER
*
+
-
+
-
PWM
COMP.
CONTROL
LOGIC
SW
DRIVER
*
LS CURRENT
SENSE
RESET
RESET
CONTROL
MODE
LOGIC
FPWM
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AGND
PGND
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8.3 Feature Description
8.3.1 RESET Flag Output
The RESET function, built-in to the LM53603-Q1, has special features not found in the ordinary power-good
function. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line
and load transients. Furthermore, there is a delay between the point at which the output voltage is within
specified limits and the flag asserts "power-good". Since the RESET comparator and the regulation loop share
the same reference, the thresholds will track with the output voltage. This allows the LM53603-Q1 to be specified
with a 96.5% maximum threshold, while at the same time specifying a 95% threshold with respect to the actual
output voltage for that device. This allows tighter tolerance than is possible with an external supervisor device.
The net result is a more accurate power-good function while expanding the system allowance for transients, etc.
RESET operation can best be understood by reference to Figure 7 and Figure 8. The values for the various filter
and delay times can be found in the Timing Requirements table. Output voltage excursions lasting less than
TRESET-filter, will not trip RESET. Once the output voltage is within the prescribed limits, a delay of TRESET-act is
imposed before RESET goes high.
This output consists of an open drain NMOS; requiring an external pull-up resistor to a suitable logic supply. It
can also be pulled-up to either VCC or VOUT, through an appropriate resistor, as desired. If this function is not
needed, the pin should be left floating or grounded. When EN is pulled low, the flag output will also be forced
low. With EN low, RESET will remain valid as long as the input voltage is ≥ 1.5 V. The maximum current into this
pin should be limited to 1 mA, while the maximum voltage should be less than 8 V.
VOUT
107%
106%
94%
93%
RESET
High = Power Good
Low = Fault
Figure 7. Static RESET Operation
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Feature Description (continued)
Glitches do not cause false operation nor reset timer
VOUT
94%
93%
< Treset_filter
RESET
Treset_act
Treset_filter
Treset_act
Figure 8. RESET Timing Behavior
8.3.2 Enable and Start-up
Start-up and shutdown of the LM53603-Q1 are controlled by the EN input. Applying a voltage of ≥ 2V will activate
the device, while a voltage of ≤ 0.8V is required to shut it down. The EN input may also be connected directly to
the input voltage supply, if this feature is not needed. This input must not be left floating. The LM53603-Q1
utilizes a reference based soft-start, that prevents output voltage overshoots and large inrush currents as the
regulator is starting-up. A typical start-up waveform is shown in Figure 9 along with typical timings.
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Feature Description (continued)
ENInductor Current
500mA/div
RESET
Treset_act
TSS
VOUT
TEN
21ms/div
ms/div
Figure 9. Typical Start-up Waveform
8.3.3 Current Limit
The LM53603-Q1 incorporates valley current limit for normal overloads and for short circuit protection. In
addition, the low side switch is also protected from excessive negative current when the device is in FPWM
mode. Finally, a high side peak current limit is employed for protection of the top NMOS FET.
During overloads the low side current limit, ILS (see Electrical Characteristics), determines the maximum load
current that the LM53603-Q1 can supply. When the low side switch turns on, the inductor current begins to ramp
down. If the current does not fall below ILS , before the next turn-on cycle, then that cycle is skipped and the low
side FET is left on until the current falls below ILS. This is somewhat different than the more typical peak current
limit, and results in Equation 1 for the maximum load current.
IOUT
max
ILS
VIN VOUT VOUT
˜
2 ˜ FS ˜ L
VIN
(1)
If the above situation persists for more than about 64 clock cycles, the device turns off both high and low side
switches for approximately 5.5 ms (see TW in Timing Requirements). If the overload is still present after the
"hiccup" time, another 64 cycles is counted and the process is repeated. If the current limit is not tripped for two
consecutive clock cycles, the counter is reset. Figure 10 shows the inductor current with a hard short on the
output. The "hiccup" time allows the inductor current to fall to zero, resetting the inductor volt-second balance.
This is the method used for short circuit protection and keeps the power dissipation low during a fault. Of course
the output current is greatly reduced in this condition (see Typical Characteristics). A typical short circuit transient
and recovery is shown in Figure 11.
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Feature Description (continued)
Short Removed
Short Applied
VOUT, 2V/div
Iinductor, 500mA/div
Iinductor, 2A/div
5ms/div
21ms/div
ms/div
2 ms/div
Figure 10. Inductor Current Bursts in Short Circuit
Figure 11. Short Circuit Transient and Recovery
The high side current limit trips when the peak inductor current reaches IHS (see Electrical Characteristics). This
is a cycle-by-cycle current limit and does not produce any frequency or current fold-back. It is meant to protect
the high side MOSFET from excessive current. Under some conditions, such as high input voltage, this current
limit may trip before the low side protection. The peak value of this current limit will vary with duty-cycle.
In FPWM mode, the inductor current is allowed to go negative. Should this current exceed INEG, the low side
switch is turned off until the next clock cycle. This is used to protect the low side switch from excessive negative
current. When the device is in AUTO mode, the negative current limit is increased to about 0 A; IZC. This allows
the device to operate in DCM.
8.3.4 Synchronizing Input
The internal clock of the LM53603-Q1 can be synchronized to a system clock through the SYNC input. This input
recognizes a valid high level as that ≥ 1.5 V, and a valid low as that ≤ 0.4 V. The frequency synchronization
signal should be in the range of 1.9 MHz to 2.3 MHz with a duty cycle of from 10% to 90%. The internal clock is
synced to the rising edge of the external clock. If this input is not used, it should be grounded. The maximum
voltage on this input is 5.5 V; and should not be allowed to float. See the Device Functional Modes section to
determine which modes are valid for synchronizing the clock.
8.3.5 Input Supply Current
The LM53603-Q1 is designed to have very low input supply current when regulating light loads. One way this is
achieved is by powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that
powers the majority of the control circuits. By connecting the BIAS input to the output of the regulator, this current
acts as a small load on the output. This current is reduced by the ratio of VOUT/VIN, just like any other load.
Another advantage of the LM53603-Q1 is that the feed-back divider is integrated into the device. This allows the
use of much larger resistors than can be used externally; >> 100 kΩ. This results in much lower divider current
than is possible with external resistors. Equation 2 can be used to estimate the total input supply current when
the device is regulating with no external loads. The terms of the equation are as follows:
• IIN: Input supply current with no load.
• IQ: Device quiescent current, see Electrical Characteristics.
• IEN: Current into EN pin; see Electrical Characteristics.
• IB: Current into BIAS pin; see Electrical Characteristics.
• K: ≈ 0.9
IIN
14
IQ
IEN
VOUT
VIN ˜ K
§
˜ ¨¨ IB
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VOUT ·
¸
RFB ¸¹
(2)
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Feature Description (continued)
Equation 2 can be used as a guide to indicate how the various terms affect the input supply current. The
Application Curves show measured values for the input supply current for both 3.3 V and 5 V output voltage
versions.
8.3.6 UVLO and TSD
The LM53603-Q1 incorporates an input undervoltage lockout (UVLO) function. The device will accept an EN
command when the input voltage rises above about 3.64 V and shuts down when the input falls below about 3.3
V. See the Electrical Characteristics table under "VIN-operate" for detailed specifications.
Thermal shutdown is provided to protect the device from excessive temperature. When the junction temperature
reaches about 162°C, the device will shut down; re-start occurs at a temperature of about 144ºC.
8.4 Device Functional Modes
Please refer to Table 1 and the following paragraphs for a detailed description of the functional modes for the
LM53603-Q1. These modes are controlled by the FPWM input as shown in Table 1. This input can be controlled
by any compatible logic, and the mode changed while the regulator is operating. If it is desired to lock the mode
for a given application, the input can be either connected to ground, a logic supply, or the VCC pin, as desired.
The maximum input voltage on this pin is 5.5 V; and it should not be allowed to float.
Table 1. Mode Selection
FPWM INPUT VOLTAGE
OPERATING MODE
> 1.5 V
Forced PWM: The regulator operates as a constant frequency, current mode, fullsynchronous converter for all loads; without diode emulation.
< 0.4 V
AUTO: The regulator will move between PFM and PWM as the load current changes,
utilizing diode-emulation-mode to allow DCM (see the Glossary).
8.4.1 AUTO Mode
In AUTO mode the device moves between PWM and PFM as the load changes. At light loads the regulator
operates in PFM . At higher loads the mode changes to PWM. The load currents for which the devices moves
from PWM to PFM can be found in the Application Curves.
In PWM , the converter operates as a constant frequency, current mode, full synchronous converter using PWM
to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple. When in PWM the converter will synchronize to any valid clock
signal on the SYNC input (see Drop-Out and Input Voltage Frequency Fold-Back).
In PFM the high side FET is turned on in a burst of one or more cycles to provide energy to the load. The
frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency
(see the ). This mode provides high light load efficiency by reducing the amount of input supply current required
to regulate the output voltage at small loadsGlossary. This trades off very good light load efficiency for larger
output voltage ripple and variable switching frequency. Also, a small increase in the output voltage will occur in
PFM. The actual switching frequency and output voltage ripple will depend on the input voltage, output voltage,
and load. Typical switching waveforms for PFM are shown in Figure 12 . See the Application Curves for output
voltage variation in AUTO mode. The SYNC input is ignored during PFM operation.
A unique feature of this device, is that a minimum input voltage is required for the regulator to switch from PWM
to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high
efficiency at light loads. Figure 13 indicates typical values of input voltage required to switch modes at no-load.
Also, once the regulator switches to PFM, at light load, it will remain in that mode if the input voltage is reduced.
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SW, 5V/div
VOUT, 50mV/div
Iinductor, 500mA/div
10µs/div
2 ms/div
Figure 12. Typical PFM Switching Waveforms
8
3.3 V
5V
7.5
Input Voltage (V)
7
6.5
6
5.5
5
4.5
4
3.5
3
-60
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
140
D023
Figure 13. Input Voltage for Mode Change
8.4.2 FPWM Mode
With a logic high on the FPWM input, the device is locked in PWM mode. This operation is maintained, even at
no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load
efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this
mode, a negative current limit of INEG is imposed to prevent damage to the regulators low side FET. When in
FPWM the converter will synchronize to any valid clock signal on the SYNC input (see Drop-Out and Input
Voltage Frequency Fold-Back).
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8.4.3 Drop-Out
One of the parameters that influences the drop-out performance of a buck regulator is the minimum off-time. As
the input voltage is reduced, to near the output voltage, the off-time of the high side switch starts to approach the
minimum value (see Timing Requirements). Beyond this point the switching may become erratic and/or the
output voltage will fall out of regulation. To avoid this problem, the LM53603-Q1 automatically reduces the
switching frequency to increase the effective duty cycle. This results in two specifications regarding drop-out
voltage, as shown in the System Characteristics table. One specification indicates when the switching frequency
drops to 1.85 MHz; avoiding the A.M. radio band. The other specification indicates when the output voltage has
fallen to 1% of nominal. See the Application Curves for typical values of drop-out. The overall drop-out
characteristic for the 5 V option, can be seen in Figure 14. The SYNC input is ignored during frequency fold-back
in drop-out.
5.2
Output Voltage (V)
5
4.8
4.6
4.4
1A
2A
3A
4.2
4
4
4.5
5
5.5
6
6.5
7
Input Voltage (V)
C003
Figure 14. Overall Drop-out Characteristic
VOUT = 5V
8.4.4 Input Voltage Frequency Fold-Back
At higher input voltages the on-time of the high side switch becomes small. When the minimum is reached (see
Timing Requirements), the switching may become erratic and/or the output voltage will fall out of regulation. To
avoid this behavior, the LM53603-Q1 automatically reduces the switching frequency at input voltages above
about 20 V (see Application Curves). In this way the device avoids the minimum on-time restriction and maintains
regulation at abnormally high battery voltages. The SYNC input is ignored during frequency fold-back at high
input voltages.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining the suitability of components for their purposes. Customers
should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM53603-Q1 and LM53602-Q1 are step-down DC-DC converters, typically used to convert a higher DC
voltage to a lower DC voltage with a maximum output current of either 3 A or 2 A. The following design
procedure can be used to select components for the LM53603-Q1 or LM53602-Q1. Alternately, the WEBENCH®
Design Tool may be used to generate a complete design. This tool utilizes an iterative design procedure and has
access to a comprehensive database of components. This allows the tool to create an optimized design and
allows the user to experiment with various design options.
9.2 Typical Applications
Figure 15 shows the minimum required application circuit for the fixed output voltage versions, while Figure 16
shows the connections for complete processor control of the LM53603-Q1. Please refer to these figures while
following the design procedures. Table 2 provides an example of typical design requirements.
L
VIN
6V to 36V
VIN
CIN
3x 10µF
10nF
LM53603
2.2 µH
EN
RESET
CBOOT
5V or 3.3V
3A
0.47 µF
3x 22µF
CBOOT
COUT
VCC
SYNC
VOUT
SW
FB
FPWM
CVCC
AGND
3.3 µF
PGND
RBIAS
BIAS
3Ÿ
CBIAS
0.1 µF
Figure 15. Typical Automotive Power Supply Schematic
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Typical Applications (continued)
VIN
6V to 36V
CIN
10nF
3x 10µF
L
VIN
LM53603
SW
2.2 µH
EN
FPWM
µC
CBOOT
3.3V or 5V
3A
0.47 µF
3x 22µF
CBOOT
COUT
SYNC
RESET
VOUT
FB
VCC
100 kŸ
AGND
CVCC
PGND
RBIAS
BIAS
3.3 µF
3Ÿ
CBIAS
0.1 µF
Figure 16. Full Featured Automotive Power Supply Schematic
9.2.1 Design Parameters
There are a few design parameters to take into account. Most of those choices will decide which version of the
device to use. The desired output current will steer the designer toward a LM53602 type or LM53603 type part. If
the output voltage is 3.3 V or 5 V, a fixed output version of the device can be used. Any other voltage level within
the tolerance of the part can be achieved by using an adjustable version of the device. Most but not all
parameters are independent of the of the IC choice. The output filter components (inductor and output
capacitors) might vary with the choice of output voltage, especially for output voltages higher than 5 V. Please
refer to Detailed Design Procedure for help in choosing these components
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V
Output voltage
5V
Maximum output current
3A
9.2.2 Detailed Design Procedure
The following detailed design procedure applies to Figure 15, Figure 16, and Figure 45.
9.2.2.1 Setting the Output Voltage
For the fixed output voltage versions, the FB input is connected directly to the output voltage node. Preferably,
near the top of the output capacitor. If the feed-back point is located further away from the output capacitors (that
is, remote sensing), then a small 100 nF capacitor may be needed at the sensing point.
For output voltages other than 5 V or 3.3 V, a feed-back divider is required. For the ADJ version of the device,
the regulator holds the FB pin at 1.0 V. The range of adjustable output voltage can be found in the
Recommended Operating Conditions. Equation 3 can be used to determine RFBB for a desired output voltage
and a given RFBT. Usually RFBT is limited to a maximum value of 100 kΩ.
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ª
º
1V
RFBT ˜ «
»
¬ VOUT 1V ¼
(3)
In addition a feed-forward capacitor CFF may be required to optimize the transient response. For output voltages
greater than 6 V, the WEBENCH Design Tool can be used to optimize the design. Recommended CFF values for
some cases are given in the table below. It is important to note that these values provide a first approximation
only and need to be verified for each application by the designer.
Table 3. Recommended CFFcapacitors
VOUT
(1)
COUT (nominal)
(1)
L
RFBT
RFBB
3.2V
44µF
2.2µH
69.8kΩ
31.6kΩ
CFF
33pF
3.2V
110µF
2.2µH
69.8kΩ
31.6kΩ
120pF
5.1V
44µF
2.2µH
80.6kΩ
19.6kΩ
33pF
5.1V
110µF
2.2µH
80.6kΩ
19.6kΩ
220pF
8V
66µF
4.7µH
86.6kΩ
12.4kΩ
120pF
8V
100µF
4.7µH
86.6kΩ
12.4kΩ
220pF
10V
66µF
4.7µH
90.9kΩ
10.0kΩ
120pF
16V X7R capacitors used : C3225X7R1C226M250AC (TDK)
9.2.2.2 Output Capacitors
The LM53603-Q1 is designed to work with low ESR ceramic capacitors. The effective value of these capacitors
is defined as the actual capacitance under voltage bias and temperature. All ceramic capacitors have a large
voltage coefficient, in addition to normal tolerances and temperature coefficients. Under D.C. bias, the
capacitance value drops considerably. Larger case sizes and/or higher voltage capacitors are better in this
regard. To help mitigate these effects, multiple small capacitors can be used in parallel to bring the minimum
effective capacitance up to the desired value. This can also ease the RMS current requirements on a single
capacitor. Table 4 shows the nominal and minimum values of total output capacitance recommended for the
LM53603-Q1. The values shown also provide a starting point for other output voltages, when using the ADJ
option. Also shown are the measured values of effective capacitance for the indicated capacitor. More output
capacitance can be used to improve transient performance and reduce output voltage ripple.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design, and should always be completed
before the application goes into production. A careful study of temperature and bias voltage variation of any
candidate ceramic capacitor should be made in order to ensure that the minimum value of effective capacitance
is provided. The best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.
In ADJ applications the feed-forward capacitor, CFF, provides another degree of freedom when stabilizing and
optimizing the design. Application report Optimizing Transient Response of Internally Compensated dc-dc
Converters With Feedforward Capacitor (SLVA289) should prove helpful when adjusting the feed-forward
capacitor.
In addition to the capacitance shown in Table 4, a small ceramic capacitor placed on the output can help to
reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF to 100 nF can be very
helpful in reducing spikes on the output caused by inductor parasitics.
The maximum value of total output capacitance should be limited to between 300 µF and 400 µF. Large values
of output capacitance can prevent the regulator from starting-up correctly and adversely effect the loop stability. If
values in the range given above, or greater, are to be used, then a careful study of start-up at full load and loop
stability must be performed.
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Table 4. Recommended Output Capacitors
OUTPUT
VOLTAGE
(1)
(2)
NOMINAL OUTPUT CAPACITANCE
MINIMUM OUTPUT CAPACITANCE
PART NUMBER
(MANUFACTURER)
RATED
CAPACITANCE
MEASURED
CAPACITANCE (1)
RATED
CAPACITANCE
MEASURED
CAPACITANCE (1)
3.3 V
3 x 22 µF
63 µF
2 x 22 µF
42 µF
C3225X7R1C226M250AC (TDK)
5V
3 x 22 µF
60 µF
2 x 22 µF
40 µF
C3225X7R1C226M250AC (TDK)
6V
3 x 22 µF
59 µF
2 x 22 µF
39 µF
C3225X7R1C226M250AC (TDK)
10 V (2)
3 x 22 µF
48 µF
2 x 22 µF
32 µF
C3225X7R1C226M250AC (TDK)
Measured at indicated VOUT at 25°C.
The following components were used: CFF = 47 pF, RFBT = 100 kΩ, RFBB = 11 kΩ, L = 4. 7 µH.
9.2.2.3 Input Capacitors
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying ripple
current and isolating switching noise from other circuits. Table 5 shows the nominal and minimum values of total
input capacitance recommenced for the LM53603-Q1. Also shown are the measured values of effective
capacitance for the indicated capacitor. In addition, small high frequency bypass capacitors connected directly
between the VIN and PGND pins are very helpful in reducing noise spikes and aid in reducing conducted EMI. It
is recommenced that a small case size 10 nF ceramic capacitor be placed across the input, as close as possible
to the device (see Figure 47). Additional high frequency capacitors can be used to help manage conducted EMI
or voltage spike issues that may be encountered.
Table 5. Recommended Input Capacitors
NOMINAL INPUT CAPACITANCE
RATED
CAPACITANCE
3 x 10 µF
(1)
MEASURED
CAPACITANCE
MINIMUM INPUT CAPACITANCE
(1)
22.5 µF
RATED
CAPACITANCE
MEASURED
CAPACITANCE (1)
2 x 10 µF
15 µF
PART NUMBER (MANUFACTURER)
CL32B106KBJNNNE (Samsung)
Measured at 14V and 25°C.
Many times it is desirable to use an electrolytic capacitor on the input, in parallel with the ceramics. This is
especially true if longs leads/traces are used to connect the input supply to the regulator. The moderate ESR of
this capacitor can help damp any ringing on the input supply caused by long power leads. The use of this
additional capacitor will also help with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor(s). The approximate RMS value of
this current can be calculated from Equation 4 and should be checked against the manufacturers' maximum
ratings.
IRMS #
IOUT
2
(4)
9.2.2.4 Inductor
The LM53603-Q1 and LM53602-Q1 are optimized for a nominal inductance of 2.2 µH for the 5 V and 3.3 V
versions. This gives a ripple current that is approximately 20% to 30% of the full load current of 3 A. For output
voltages greater than 5 V, a proportionally larger inductor can be used. This will keep the ratio of inductor current
slope to internal compensating slope constant.
The most important inductor parameters are saturation current and parasitic resistance. Inductors with a
saturation current of between 5 A and 6 A are appropriate for most applications, when using the LM53603-Q1.
For the LM53602-Q1, inductors with a saturation current of between 4 A and 5 A are appropriate. Of course the
inductor parasitic resistance should be as low as possible to reduce losses at heavy loads. Table 6 gives a list of
several possible inductors that can be used with the LM53603-Q1.
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: LM53602-Q1 LM53603-Q1
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LM53602-Q1, LM53603-Q1
SNVSA42B – JUNE 2015 – REVISED MAY 2016
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Table 6. Recommenced Inductors
MANUFACTURER
PART NUMBER
SATURATION
CURRENT
D.C. RESISTANCE
Würth
7440650022
6A
15 mΩ
Coilcraft
DO3316T-222MLB
7.8 A
11 mΩ
Coiltronics
MPI4040R3-2R2-R
7.9 A
48 mΩ
Vishay
IHLP2525CZER2R2M01
14 A
18 mΩ
Vishay
IHLP2525BDER2R2M01
14 A
28 mΩ
Coilcraft
XAL6030-222ME
16 A
13 mΩ
9.2.2.5 VCC
The VCC pin is the output of the internal LDO, used to supply the control circuits of the LM53603-Q1. This output
requires a 3.3 µF to 4.7µF, ceramic capacitor connected from VCC to GND for proper operation. An X7R device
with a rating of 10 V is highly recommended. In general this output should not be loaded with any external
circuitry. However, it can be used to supply a logic level to the FPWM input, or for the pull-up resistor used with
the RESET output (see Figure 16 ). The nominal output of the LDO is 3.15 V.
9.2.2.6 BIAS
The BIAS pin is the input to the internal LDO. As mentioned in Input Supply Current, this input is connected to
VOUT in order to provide the lowest possible supply current at light loads. Since this input is connected directly to
the output, it should be protected from negative voltage transients. Such transients may occur when the output is
shorted at the end of a long PCB trace or cable. If this is likely, in a given application, then a small resistor
should be placed in series between the BIAS input and VOUT, as shown in Figure 15. The resistor should be
sized to limit the current out of the BIAS pin to
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