LVDS001EVK

LVDS – LVDS Buffer Evaluation Board LVDS001EVK Revision 1.0 April 2001 LVDS001EVK.DOC The LVDS – LVDS Buffer Evaluation Board The LVDS – LVDS Buffer Evaluation Board is used to demonstrate the use and performance of the DS90LV001 device. Input LVDS or LVPECL signals or complementary signals from a signal generator can be probed differentially and output LVDS channels can be probed single-ended or differentially. The DS90LV001 can be used as a “stub-hider.” In many systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the “stub length” or the distance between the transmission line and the unterminated receivers on the individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns and PCB designs often make it difficult to make the stubs as short as the engineer would like. The DS90LV001, available in the LLP (Leadless Leadframe Package) package, can improve system performance by allowing the receiver to be placed very close to the main transmission line either on the backplane itself or very close to the connector on the card. Longer traces to the LVDS receiver may be placed after the DS90LV001. This very small LLP package is a 75% space savings over the SOIC package. Shown below in Figure 1 and Figure 2 are two typical applications for the DS90LV001, the cable repeater application and the backplane stub-hider application. Figure 1: Cable Repeater Application Figure 2: Backplane Stub-Hider Application 2 Purpose The purpose of the Low Voltage Differential Signaling (LVDS) Evaluation Printed Circuit Board (PCB) is to allow the user to evaluate the performance of the device. The part number for the Evaluation Kit is LVDS001EVK. Board Description The simplified block diagram of this board is shown in Figure 3 below. 453Ω RS1 EN L H OUTIN- J2 _ + IN+ 50Ω 0Ω RT1 RT3 50Ω RT2 _ U1 DS90LV001 + J3 _ + 50Ω RT1 50Ω RT2 V_BIAS +13V 1620Ω RVT 453Ω RS3 OUT+ 50Ω RT5 0.1µF C2 453Ω RS2 Figure 3: PCB Block Diagram Termination options on the buffer inputs (IN- and IN+) accommodate either two separate 50 Ohm terminations (RT1 and RT2) (each line to ground when RT3 of 0 Ohms is in place) on the bottom of the board or a 100 Ohm resistor connected across the inputs (differential) when RT3 is removed. The first option allows for a standard signal generator interface. The second option allows for the DS90LV001 to be driven by an LVDS driver. Input signals are connected at test points IN- and IN+. A direct probe connection is possible with a TEK P6247 differential probe high impedance probe (>1GHz bandwidth) on the LVDS signals at test point J2. The termination load of a standard 100 Ohm differential termination along with series 453 Ohm resistors (RS1 and RS2) are implemented since 50 Ohm probes are employed on the buffer output signal through the SMA connectors OUT- and OUT+. The LVDS driver cannot drive the 50 Ohm load to ground, so a V_BIAS voltage of +13V is used with additional resistor network circuitry to minimize this additional load. Note that the scope th waveform is an attenuated signal (50 Ohm/(450 Ohm = 50 Ohm) or 1/10 of the output signal. A direct differential probe connection is possible with a TEK P6247 differential high impedance probe (>1GHz bandwidth) on the output LVDS signals at test point J3. The series 453 Ohm resistors (RS1 and RS2) must be removed to allow a clean test point. PCB Design Due to the high speed switching rates obtainable by LVDS a minimum of a four layer PCB construction and FR-4 material is recommended. This allows for 2 signal layers and full power and ground planes. The stack is: signal (LVDS), ground, power, signal. The DS90LV001 demo board is a six layer board of FR-4 material with the following stack: signal (LVDS), ground, power, ground, ground, signal. This stack sandwiches the power plane with two ground planes creating good decoupling capacitance. Although differential traces are highly recommended for LVDS signals, due to the short distance on this demo board, 50 Ohm single-ended microstrip lines are used. Equations for calculating impedance are contained in National application note AN-905 for both microstrip and stripline PCB traces. 3 For the microstrip line, the microstrip impedance, ZO, is: ZO ≅ 6 ln 0.475εr + 0.67 4h Ohm 0.67 (0.8w + t) s t W S h εr W For the new evaluation board h = 9 mils, w =15mils and t = 2.1mils. Calculating the impedance, ZO, is: ZO ≅ ≅ 6 ln 0.475εr + 0.67 4h Ohm 0.67 (0.8w + t) s 6 0.475εr (4.3) + 0.67 ln 4(9) Ohm 0.67 (0.8(15) + 2.1) s ≅ 48.7 Ohms Bypassing capacitors are recommended for each package. A 0.1 µF is sufficient on the buffer device (CB1) however, additional smaller value capacitors may be added (i.e. 0.001 µF at CB21) if desired. Traces connecting VCC and ground should be wide (low impedance, not 50 Ohm dimensions) and employ multiple vias to reduce inductance. Bulk bypassing is provided (C1, close by) at the main power connection as well. Additional power supply high frequency bypassing can be added at CB2, CB12, and CB22 if desired. Sample Waveforms from the LVDS Evaluation PCB Single-ended signals are measured from each signal (true and inverting signals) with respect to ground. The buffer ideally switches at the crossing point of the two signals. LVDS signals have a VOD specification of 250mV to 450mV with a typical VOS of 1.2V. Our device has a typical VOD of 325mV, but for the example below, we will use a signal between 1.0 V (VOL) and 1.4 V (VOH) for a 400 mV VOD. The differential waveform is constructed by subtracting the OUT- (inverting) signal from the OUT+ (true) signal. VOD = (OUT+) – (OUT-). The VOD magnitude is either positive or negative, so the differential swing (VSS) is twice the VOD magnitude. Drawn singleended waveforms and the corresponding differential waveforms are shown in Figure 5. Single-Ended Waveforms A = 1.4V VOH ±VOD VOS = +1.2V B = 1.0V VOL Ground Differential Waveform +400mV +VOD A – B = 0V VSS -VOD -400mV Figure 5: Single-ended and Differential Waveforms 4 Probing of High Speed LVDS Signals Probe specifications for measuring LVDS signals are unique due to the low drive level of LVDS (3 mA typical). For this board design, either a 50 Ohm scope module (SD-22) or the TEK P6247 differential probe (>1 GHz bandwidth) must be used. The capacitive loading of the probe should be kept in the low pF range, and the bandwidth of the probe should be at least 1 GHz (4 GHz preferred) to accurately acquire the waveform under measurement. National’s Interface Applications group employs a wide range of probes and oscilloscopes. One system that meets the requirements of LVDS particularly well is an Agilent 86100A Wide-Bandwidth Oscilloscope (>20GHz bandwidth), Agilent 86112 20GHz module and TEK P6247 differential probe heads. The probe offers 200kΩ, 1pF loading and a bandwidth of 1GHz. This test equipment was used to acquire the waveforms shown in Figure 6. VCC VCC IN+ EN EN J2 DS90LV047A 10 meter CAT5 cable 100Ω + _ DS90LV001 J3 100Ω 50Ω IN- Signal 1 DIFF OUT± DS90LV047A Signal 2 DIFF IN± J2 Signal 3 DIFF OUT± J3 Figure 6: Input and Output LVDS Signals in Cable Repeater Application 5 In this figure, a DS90LV047A quad LVDS driver was used to drive the DS90LV001 buffer through a 10 meter CAT5 cable. Signal 1 is the differential signal at the output of the DS90LV047A driver. Signal 2 is the differential signal entering the DS90LV001 buffer at the end of the 10 meter cable and signal 3 is the differential output of the DS90LV001 buffer. Note the clean re-driven signal (signal 3), this is the role of a repeater. Demo PCB Option Option 1: Disabling the LVDS Buffer The DS90LV001 buffer features an enable pin. On the evaluation PCB, the active high input (EN) is routed to a jumper (EN). The jumper provides a connection to the VCC plane (“H”) or to the Ground plane (“L”). To enable the buffer, connect the jumper to the power plane (“H”), to disable (TRI-STATE) the buffer, connect the jumper to ground (“L”). Note that RT4 is saved for a future use. Plug & Play The following simple steps should be taken to begin testing on your completed evaluation board: 1) Connect signal common (ground) to the header marked GND 2) Connect the power supply lead to the header marked VCC (3.3V) 3) Connect +13V to the circuit bias V_BIAS (depending on the resistor tolerances, this voltage should be adjusted to ensure that the output VOS is +1.25V…monitor the voltage at the voltage node before the 1620 Ohm resistor on top of the board…this should be +1.25V) 4) Set EN jumper to the power plane (“H”) to enable the buffer 5) Connect a complementary signal by a signal generator to the buffer input (IN- and IN+) with: a) frequency = 100 MHz (200 Mbps) b) VIL = 1.0V & VIH = 1.4V c) tr & tf = 2ns d) duty cycle = 50% (square wave) 6) Connect a differential probe to test point J2 and either a differential probe to test point J3 or RG142B cables to an SD-22 module to OUT- and OUT+. Do not attempt to connect only one output as the +13V bias voltage assumes that both outputs are loaded with 50 Ohms. 7) View LVDS signals using the same voltage offset and volts/div settings on the scope with the TEK P6247 differential probes and/or SD-22 module and RG142B cables Summary This evaluation PCB provides a simple tool to evaluate how the DS90LV001 LVDS – LVDS buffer can be used to regenerate an LVDS signal and to determine signal quality for high speed data transmission applications. Reference Material • DS90LV001 datasheet • LVDS Owner’s Manual • AN-905 Transmission Line RAPIDESIGNER Operation and Application Guide • AN-1187 Leadless Leadframe Package (LLP) Additional Information available on the Internet: http://www.national.com/appinfo/lvds 6 Appendix Typical test equipment used for LVDS measurements: Signal Generator HP 8133A Pulse Generator Oscilloscope Agilent 86100A Wide-Bandwidth Oscilloscope, 86112A 20GHz module Probes TEK P6247 differential probe, Tek 1103 TEKPROBE Power Supply Attenuators Pasternack 6dB attenuators Bill of Materials Type IC SMA Jack Resistor Resistor Resistor Resistor Resistor Capacitor Capacitor Capacitor Capacitor Headers Headers Jumpers Headers PCB Label Value/Tolerance Qty Footprint U1 IN-, IN+, OUT-, OUT+ RT3 RT1, RT2, RT5, RL1, RL3 RS1, RS2, RS3 RVT RT4 CB1, CB2, C2 CB12 CB21, CB22 C1 EN J2, J3 (Buffer) 1 4 1 5 3 1 1 3 1 2 1 1 2 1 3 1 8-L SOIC SMA Connector RC0805 RC0805 RC0805 RC0805 RC0805 CC0805 CC0805 CC0805 D VCC, GND, VBIAS 0Ω 50Ω 453Ω 1620Ω open 0.1µF 0.01µF 0.001µF 10µF, 35V 3 lead header 2 lead header 0.1" jumper post shunts 1 lead header Part Number DS90LV001TM Johnson P/N 142-0801-811 not loaded Solid Tantalum Chip Capacitor 100 mil spacing (single row header) 100 mil spacing (single row header) LVDS001PCB 7 Schematic 8 Demo Board Layers 9 10 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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