OPA655U

® OPA 655 OPA655 OPA 655 Wideband, Unity Gain Stable, FET-Input OPERATIONAL AMPLIFIER FEATURES q 400MHz UNITY GAIN BANDWIDTH q LOW INPUT BIAS CURRENT: 5pA q HIGH INPUT IMPEDANCE: 1012Ω || 1.0pF q ULTRA-LOW dG/dP: 0.006%/0.009° q LOW DISTORTION: 90dB SFDR at 5MHz q FAST SETTLING: 17ns (0.01%) q HIGH OUTPUT CURRENT: 60mA q FAST OVERDRIVE RECOVERY DESCRIPTION The OPA655 combines a very wideband, unity gain stable, voltage feedback op amp with a FET input stage to offer an ultra high dynamic range amplifier for ADC buffering and transimpedance applications. Extremely low harmonic distortion along with excellent pulse settling characteristics will support even the most demanding ADC input buffer requirements. The broad unity gain stable bandwidth and FET input allows exceptional performance in high speed, low noise integrators. The high input impedance and low bias current provided by the FET input is further supported by the ultra-low 6nV/√Hz input voltage noise to achieve a very low integrated noise in wideband photodiode transimpedance applications. Broad transimpedance bandwidths are achievable given the OPA655’s high 240MHz gain bandwidth product. As shown below, a –3dB bandwidth of 1MHz is provided even for a high 1MΩ transimpedance gain from a 47pF source capacitance. 1MΩ TRANSIMPEDANCE BANDWIDTH 130 APPLICATIONS q WIDEBAND PHOTODIODE AMPLIFIER q PEAK DETECTOR q CCD OUTPUT BUFFER q ADC INPUT BUFFER q HIGH SPEED INTEGRATOR q TEST AND MEASUREMENT FRONT END 1pF 499kΩ 499kΩ Transimpedance Gain (dB) 1MHz Bandwidth 120 110 λ (47pF) OPA655 100Ω VO 100 90 –Vb 80 10kHz 100kHz Frequency 1MHz 5MHz Wideband Photodiode Transimpedance Amplifier International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1994 Burr-Brown Corporation PDS-1271D Printed in U.S.A. May, 1997 SPECIFICATIONS At TA = +25°C, VS = ±5V, RFB = 100Ω, and RL = 100Ω, unless otherwise noted. RFB = 0 for G = +1. OPA655P, U PARAMETER FREQUENCY RESPONSE Closed-Loop Response CONDITIONS Gain = +1V/V, VO = 200mVp-p Gain = +2V/V, VO = 200mVp-p Gain = +5V/V, VO = 200mVp-p Gain = +10V/V, VO = 200mVp-p G = +1, 1V Step 0.2V Step 0.2V Step G = +1, 1V Step G = +1, 1V Step G = +1, 1V Step G = +1, f = 5MHz VO = ±1V, RL = 100Ω 3.58MHz, 0 to 1.4V, RL = 150Ω 3.58MHz, 0 to 1.4V, RL = 150Ω G = +2, 2Vp-p 210 200 MIN TYP 400 185 57 24 240 290 1 1 17 8 6 90 0.006 0.009 30 ±1 ±10 70 65 –5 ±2 ±2 MAX UNITS MHz MHz MHz MHz MHz V/µs V/µs ns ns ns ns ns dBc % degrees MHz mV µV/°C dB dB pA nA pA nA Gain-Bandwidth Product Slew Rate Over Temperature Rise Time Fall Time Settling Time: 0.01% 0.1% 1% Spurious-Free Dynamic Range Differential Gain Differential Phase Bandwidth for 0.1dB flatness OFFSET VOLTAGE Input Offset Voltage Over Temperature Power Supply Rejection (+VS) (–VS) INPUT BIAS CURRENT(1) Input Bias Current Over Temperature Input Offset Current Over Temperature NOISE Input Voltage Noise Noise Density: f = 100Hz f = 1kHz f = 10kHz f = 0.1MHz to 100MHz Integrated Voltage Noise, BW = 1MHz to 100MHz Input Bias Current Noise Current Noise Density, f = 10Hz to 10kHz INPUT VOLTAGE RANGE Common-Mode Input Range Over Temperature Common-Mode Rejection INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain Over Temperature OUTPUT Voltage Output Over Temperature Current Output Over Temperature Short-Circuit Output Current Output Resistance POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Temperature TEMPERATURE RANGE Specification: P, U Thermal Resistance, θJA P U 75 |VS| = 4.50V to 5.50V 55 50 VCM VCM VCM VCM = = = = 0V 0V 0V 0V –125 –8.0 ±125 ±8 20 8 6 6 60 nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms fA/√Hz V V dB Ω || pF Ω || pF dB dB V V mA mA mA Ω V V mA mA °C °C/W °C/W 1.3 ±2.75 70 1012 || 1.2 1012 || 1.0 VO = ±2V, RL = 100Ω VO = ±2V, RL = 100Ω RL = 100Ω, G = +1 53 50 ±3.0 ±2.8 ±35 ±28 58 4 VCM = ±0.5V ±2.5 55 ±3.4 ±60 ±140 0.04 ±5 ±25 0.1MHz, G = +1 TMIN to TMAX TMIN to TMAX ±4.75 ±21 ±5.25 ±29 ±31 +85 –40 100 125 NOTE: (1) Junction temperature ≈ +25°C for room temperature tested input bias and offset current. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA655 2 ABSOLUTE MAXIMUM RATINGS Total Supply Voltage Across Device (VS (TOTAL)) ................................ 11V Internal Power Dissipation ........................... See Thermal Considerations Differential Input Voltage ............................................................ VS (TOTAL) Common-Mode Input Voltage Range .................................................. ±VS Storage Temperature Range: P, U ............................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C (soldering, SO-8, 3s) ...................................... +260°C Junction Temperature (TJ ) ............................................................ +175°C PACKAGE INFORMATION PRODUCT OPA655P OPA655U PACKAGE 8-Pin Plastic DIP SO-8 PACKAGE DRAWING NUMBER(1) 006 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PIN CONFIGURATION Top View DIP/SO-8 PRODUCT OPA655P OPA655U PACKAGE 8-Pin Plastic DIP SO-8 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C NC Inverting Input Non-Inverting Input –VS1 1 2 3 4 8 7 6 5 +VS2(1) +VS1 Output –VS2(1) ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. NOTE: (1) Making use of all four power supply pins is highly recommended, although not required. Using these four pins, instead of pins 4 and 7 only, will reduce the effective pin impedance and substantially improve distortion. ® 3 OPA655 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±5V, RFB = 100Ω, and RL = 100Ω, unless otherwise noted. RFB = 0 for G = +1. INPUT VOLTAGE AND CURRENT NOISE 100 Input Voltage Noise (nV/√Hz) Input Current Noise (fA/√Hz) 1000 INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE Offset Current (pA) Input Bias Current (pA) 100 IOS 10 IB 10 Voltage Noise Current Noise 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) 1 –50 0 50 Temperature (°C) 100 CLOSED-LOOP BANDWIDTH 6 G = +1 3 0 Gain (dB) CLOSED-LOOP BANDWIDTH 12 G = +2 9 6 Gain (dB) DIP SO-8 Bandwidth = 400MHz DIP, SO-8 Bandwidth = 185MHz 3 0 –3 –6 –3 –6 –9 –12 1M 10M 100M Frequency (Hz) 1G 3G –9 –12 100k 1M 10M Frequency (Hz) 100M 1G CLOSED-LOOP BANDWIDTH 20 G = +5 17 14 DIP, SO-8 Bandwidth = 57MHz CLOSED-LOOP BANDWIDTH 26 G = +10 23 20 Gain (dB) DIP, SO-8 Bandwidth = 24MHz Gain (dB) 11 8 5 –2 –1 –4 100k 17 14 11 8 5 2 100k 1M 10M Frequency (Hz) 100M 1G 1M 10M Frequency (Hz) 100M 1G ® OPA655 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RFB = 100Ω, and RL = 100Ω, unless otherwise noted. RFB = 0 for G = +1. HARMONIC DISTORTION vs FREQUENCY (VO = 2Vp-p, G = +1) –40 –50 –60 2fO –70 –80 –90 –100 1M 10M Frequency (Hz) 100M 3fO –40 –50 –60 –70 –80 –90 –100 1M HARMONIC DISTORTION vs FREQUENCY (VO = 2Vp-p, G = +2) Harmonic Distortion (dBc) Harmonic Distortion (dBc) 2fO 3fO 10M Frequency (Hz) 100M HARMONIC DISTORTION vs FREQUENCY (VO = 2Vp-p, G = +5) –40 –50 –60 –70 –80 –90 –100 1M 10M Frequency (Hz) 100M 3fO –85 5MHz HARMONIC DISTORTION vs OUTPUT SWING G = +1 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –90 –95 –100 –105 –110 –115 0.1 1 Output Swing (Vp-p) 10 3fO 2fO 2fO 10MHz HARMONIC DISTORTION vs OUTPUT SWING –60 G = +1 –65 –85 HARMONIC DISTORTION vs TEMPERATURE (VO = 2Vp-p, G = +1, fO = 5MHz) Harmonic Distortion (dBc) –70 2fO –75 –80 –85 –90 –95 0.1 1 Output Swing (Vp-p) 10 3fO Harmonic Distortion (dBc) –90 2fO –95 3fO –100 –50 –25 0 25 50 75 100 Temperature (°C) ® 5 OPA655 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RFB = 100Ω, and RL = 100Ω, unless otherwise noted. RFB = 0 for G = +1. OPEN-LOOP GAIN AND PHASE vs FREQUENCY 80 60 Gain 40 Gain (dB) OVERDRIVE RECOVERY, G = +3 90 Input and Output Voltage (V) 45 0 Phase (°) 4 3 Output 20 0 –20 –40 10 100 Phase –45 –90 –135 –180 1G Input 2 1 0 –1 1k 10k 100k 1M 10M 100M Frequency (Hz) Time (50ns/div) SMALL-SIGNAL TRANSIENT RESPONSE LARGE-SIGNAL TRANSIENT RESPONSE 60 Output Voltage (mV) Output Voltage (V) Time (5ns/div) 40 20 0 –20 –40 –60 3 2 1 0 –1 –2 –3 Time (20ns/div) SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 28 80 AOL, PSR AND CMRR vs TEMPERATURE 90 85 AOL, PSR AND CMRR (dB) Supply Current IQ (±mA) Output Current IO (±mA) 27 70 80 75 70 65 60 55 AOL CMRR PSR+ 26 IO 25 IQ 24 60 50 PSR– 40 23 –50 30 –25 0 25 50 75 100 Temperature (°C) 50 –50 –25 0 25 50 75 100 Temperature (°C) ® OPA655 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RFB = 100Ω, and RL = 100Ω, unless otherwise noted. RFB = 0 for G = +1. INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE 20 10 35 RECOMMENDED RESISTANCE vs CAPACITIVE LOAD G = +1 30 25 VIN CL RS RISO Input Bias Current IB (pA) 0 –10 RISO (Ω) –20 –30 –40 –50 –60 –70 –80 –3.0 –2.4 –1.8 –1.2 –0.6 20 15 10 5 0 VCM (V) 0.6 1.2 1.8 2.4 3.0 0 10 20 30 40 50 60 70 80 90 100 Capacitive Load (pF) COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 80 Common-Mode Rejection (dB) 75 70 65 60 55 –3 –2 –1 0 1 2 3 Common-Mode Voltage (V) ® 7 OPA655 DISCUSSION OF PERFORMANCE Amplifiers using FET input transistors operate in a similar manner to those using bipolar transistors, with some important advantages. In standard op amp applications, the very low input bias currents reduce the DC error voltage due to a high or possibly unknown source impedance. In most OPA655 applications, the output DC error will be due only to the low 1mV input offset voltage. Similarly, input noise currents will contribute very little to the total output noise in most applications. Wideband transimpedance applications (e.g., photodiode amplifiers) will particularly benefit from the low current noise combined with the OPA655’s very low 6nV/√Hz input voltage noise. The OPA655’s high gain bandwidth and very linear output stage hold the harmonic distortion below –90dBc through 5MHz for a 2Vp-p swing into 100Ω. Significantly less distortion is observed at lower frequencies and/or higher load impedance. The voltage feedback architecture supports this level of accuracy with greater than 65dB power supply and common mode rejection ratios. This very high dynamic range, along with the low DC errors and noise of the FET input stage, can provide an exceptional buffering capability for ADC’s, PMT’s and other applications requiring high impedance sensing of a high speed signal. For similar distortion performance with a bipolar input stage, refer to the OPA642. OPERATING CONSIDERATIONS Careful attention to PC board layout will deliver the exceptional performance shown in the Typical Performance Curves. Generally, very low impedance paths to the power supplies, along with low parasitic connections to the signal I/O pins are required for best performance (See Layout and Interconnect Considerations). Use of a guard ring around the noninverting input can reduce the leakage current due to common mode input signals. However, driving the guard from the inverting node, can increase the differential input capacitance, possibly leading to instability or increased broadband noise. Non-inverting buffer applications require a very low inductance short to be connected between the output and inverting input to minimize peaking in the frequency response. Use a wide trace (0.1") directly between the output and inverting input pins on the component side of the board for this connection. The OPA655 is nominally designed to operate from ±5V supplies. The maximum voltage between the supply pins should be limited to less than 11V. Since a supply independent bias is used, very little change in AC performance is observed as the supply voltage is changed. BASIC OP AMP CONNECTIONS Figures 2 through 4 illustrate the basic op amp connections suitable for the OPA655. The non-inverting buffer (voltage follower) application (Figure 2) will benefit from the very +VS1 7 5Ω 8 +VS2 –In 2 +In 3 Output Stage 6 Output Supply Independent Bias Current Mirror CC 5Ω 4 –VS1 5 –VS2 FIGURE 1. Simplified Internal Schematic. ® OPA655 8 high FET input impedance and low closed loop output impedance. Remember that a DC path to the input is still necessary; even with the ultra low FET input bias current (5pA), open or capacitively coupled sources will cause the input to saturate. For best frequency response, a direct short between the output and inverting inputs is suggested. Since the input bias currents are not necessarily correlated, matching the non-inverting source resistance with a resistor in the feedback network is not recommended. RF RS VIN R1 V– 2 6 3 VO VIN = VO –RF R1 VSOURCE RT 2 ZI VIN 3 OPA655 6 ZO VO RL = 100Ω VO VIN =1 FIGURE 4. Inverting Op Amp. β = V–/VO Non-Inverting Gain = Noise Gain = NG = 1/β Taking the inverting amplifier as an example, β is found by setting VSOURCE to zero and calculating the voltage divider ratio from VO to V–: R1 + RT || RS = total resistance to ground on the inverting input NOTE: Power supplies and de-coupling not shown. FIGURE 2. Non-Inverting Unity Gain Buffer. The non-inverting amplifier configuration (Figure 3) will again present a very high input impedance to the input signal and a low output impedance drive with signal gain. The 100Ω shown for RF will give the frequency response shown in the Typical Performance Curves. Higher values for RF and R1 are possible but for high frequency non-inverting op amp applications, should be limited to less than 1.0kΩ. The amplifier will be loaded by (RF + R1) in parallel with the load impedance. β= R1 + R T || R S V– = V O R F + R1 + R T || R S RF 1 = 1+ R1 + R T || R S β NG = RF = 100Ω The resulting bandwidth is approximately the amplifier’s gain bandwidth product divided by the calculated noise gain: R1 2 3 OPA655 6 VO VIN VO =1+ RF R1 BW ≈ GBW/NG In practice, low noise gains (< 5) will produce a wider bandwidth than predicted due to the peaking effect of second order poles. For example, at an inverting gain of –1 from a zero ohm source impedance, this yields a non-inverting gain of 2 and an approximate signal bandwidth of 185MHz. VIN FIGURE 3. Non-Inverting Op Amp. The inverting amplifier configuration (Figure 4) offers a broadband, low DC error amplifier with a controlled input impedance. The input impedance may be set by adjusting R1 to the desired value and then adjusting RF to the desired gain, or by setting RF and R1 to the desired values then controlling the input impedance independently as the parallel combination of R1 and an optional RT resistor to ground. To estimate the bandwidth in any configuration, first calculate the gain as a non-inverting amplifier. This is often referred to as “noise gain” or NG, and is simply the inverse of the feedback factor β. TYPICAL APPLICATIONS WIDEBAND TRANSIMPEDANCE AMPLIFIER The high gain bandwidth product and low noise of the OPA655 make it particularly suitable for wideband transimpedance applications. The front page of the data sheet shows measured results for a 1MΩ transimpedance gain from a relatively large diode having 47pF parasitic capacitance. The key to broadband transimpedance applications is to set the compensation capacitance across the feedback resistor to achieve a flat, or bandlimited, frequency ® 9 OPA655 response. Figure 5 shows the analysis circuit for setting the feedback compensation capacitor, CF, while Figure 6 shows the Bode analysis. to set the high frequency pole for the noise gain at its intersection with the open loop gain response. If the 1/2πRFCF pole for the noise gain were set exactly at the intersection with the amplifier’s open loop gain rolloff, the circuit would be operating with a 45° phase margin yielding a highly peaked frequency response. To reduce broadband noise and pulse response ringing, it is preferable to set this pole at a slightly lower frequency than the simplified analysis shown above. A second order analysis for the transimpedance configuration yields the following results to achieve a maximally flat Butterworth characteristic for the transimpedance frequency response. Using the OPA655’s gain bandwidth product (GBW) in Hz, define a variable: α = RF • CS • GBW • 2π (where CS = CD + CCM + CDIFF) Then, the required CF to produce a maximally flat frequency response is: C F = CS • 2 2α – 1 ≈ CS α α CDIFF OPA655 CCM RF CF IDIODE CD FIGURE 5. Transimpedance Analysis Circuit. CS = CD + CDIFF + CCM AOL Open Loop Gain Noise Gain and the resulting –3dB bandwidth for the transimpedance gain will be: F –3dB = GBW • 2 α + 2α – 1 0 f (Hz) 1 2π RF (CS + CF) 1 2π RF CF Gain Bandwidth Product FIGURE 6. Bode Analysis for Transimpedance Circuit. The total capacitance to ground on the inverting input of the OPA655 will set the source capacitance (CS) for analysis purposes. CS is the sum of the diode capacitance (CD), the common mode input capacitance CCM and the differential input capacitance (CDIFF). Looking at the Bode analysis for the transimpedance configuration, at low frequencies the noise gain is 1 (0dB) but will increase for frequencies above 1/2π(RF • (CS + CF)) due to the zero formed by the capacitance on the inverting node. It is important to note that the gain for the op amp input noise voltage will increase similarly. To get maximum bandwidth, CF is often set to form a high frequency pole at the intersection of this increasing noise gain and the open loop gain rolloff. This is accomplished by setting 1/2π(RF • CF) equal to the geometric mean of the zero frequency and the gain bandwidth product of the op amp. If the gain bandwidth product is in Hz, and assuming that CF 40dB through 100MHz was achieved. CD =50pF DIFFERENTIAL INPUT 1 CD = 100pF CD = 200pF 0.3 10 100 Transimpedance Gain, RF (kΩ) 1000 3.5dB 2.5 1.5 .5 136MHz FIGURE 8. Maximally Flat Bandwidth. HIGH SPEED INSTRUMENTATION DIFFERENTIAL AMPLIFIER Very high speed differential amplifiers can be implemented using the OPA655. The very low input bias currents allow relatively high resistor values to be used in a standard single op amp differential configuration. Alternatively, a very high input impedance differential amplifier can be implemented using a three op amp instrumentation amplifier topology as shown in Figure 9. 1M 10M 100M 1G FIGURE 10. Measured Frequency Response for INA. OPTIMIZING PERFORMANCE DC ACCURACY The OPA655 is laser trimmed for low input offset voltage, limiting the need for external trim circuits. In most cases, the low bias current of the FET input will not contribute significantly to the output DC error. For example, at minimum gain (G = +1) and maximum temperature (85°C), the error contribution due to the inverting input bias current would only exceed the input offset voltage for feedback resistors > (1mV/3.2nA) = 312kΩ. Only for relatively high source and/ or feedback resistor values will the input bias current contribute significantly to the output DC error. Similarly, since the two input bias currents are very low, but not tightly matched, input bias current cancellation through source impedance matching is not recommended. Changes in the power supply voltages contribute to shifts in the input offset voltage. This can be calculated using the PSR specifications. For example, a 0.5V change in the negative power supply will show up typically as a 0.5V • 10(–65/20) = 0.28mV change in the input offset voltage. Negative common mode voltage inputs can cause an increase in the input bias currents as shown in the Typical Performance Curves. This can have an effect on DC accuracy when the source and/or feedback resistors are large and the common mode input voltage approaches the negative limit of –2.5V. Positive input biases are therefore preferred for diode transimpedance applications requiring a bias voltage on the non-inverting op amp input. V– OPA655 RF 100Ω 300Ω CT 300Ω 1.5 to 6pF 50Ω OPA651 50Ω Load RG 100Ω RF 100Ω 300Ω OPA655 V+ 300Ω FIGURE 9. High Input Impedance, Broadband INA. In this example, the OPA655’s provide a differential gain of:  2R F  1 +  =3 RG   and a common mode gain of 1 to the input of the OPA651 differential stage. The OPA651, a gain of 2 stable, broadband voltage feedback op amp, rejects the common mode signal and provides a differential gain of 1/2 the matched 50Ω load. This circuit delivers a 136MHz bandwidth at a ® 11 OPA655 FREQUENCY RESPONSE COMPENSATION The OPA655 is internally compensated to be stable at unity gain into a 100Ω load with a nominal phase margin of 58°. This unity gain phase margin shows a slight peaking in the frequency response and requires a very low inductance shorting connection from the output pin to the inverting input pin for minimal peaking. This stable broadband performance at unity gain lends itself well to integrator and buffer applications. Phase margin and flatness will improve at higher gains. Since phase margin is slightly load dependent, flatness in a gain of +2 can be modified by changing the loading. Very flat performance is shown in the Typical Performance Curves using a 100Ω feedback and 100Ω load. This may be peaked up by increasing the load or feedback resistors or rolled off by decreasing them. Recall that an inverting gain of –1 is equivalent to a gain of +2 for bandwidth purposes, i.e. noise gain equal to 2. The external compensation techniques developed for voltage feedback op amps can be applied to this device. For example, in the non-inverting configuration, placing a capacitor across the feedback resistor will reduce the gain to +1 starting at f = 1/(2π RF CF) Hz. Alternatively, in the inverting configuration, the bandwidth may be limited without modifying the low frequency inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at higher frequencies, thereby limiting the bandwidth for the inverting input signal through the gain-bandwidth product. At higher gains, the gain-bandwidth product (240MHz) of this voltage feedback topology will limit the achievable signal bandwidth. If FET input is not required and higher bandwidths at higher gains are needed, consider the broad bandwidth available from a current feedback op amp such as the OPA658. DRIVING CAPACITIVE LOADS The high open loop gain and Class AB output stage of the OPA655 are optimized for driving the low impedance of doubly terminated cables. Capacitive loads directly on the output pin can decrease phase margin leading to frequency response peaking and possibly sustained oscillations. This effect is particularly pronounced at unity gain and becomes less significant at higher gains. Frequency response flatness can be maintained into a capacitive load by isolating it with a resistor as shown in Figure 11. The Typical Performance Curves show a plot of the minimum value for RISO to hold a flat frequency response as CL is increased. The 1kΩ shunt load across CL shown in Figure 11 was the probe load for this measurement and should be considered optional. PULSE AND OVERDRIVE PERFORMANCE High speed amplifiers like the OPA655 can provide an extremely fast settling time for a pulse input. Excellent frequency response flatness and phase linearity are required RISO OPA655 VIN RIN 1kΩ CL FIGURE 11. Driving a Capacitive Load. to get the best settling times. As shown in the specifications table, settling time for a 1V step at a gain of +1 for the OPA655 is an extremely fast 8ns to 0.1%. This specification is defined as the time required, after the input transition, for the output to settle within a specified error band around its final value. For a 1V step, 0.1% settling corresponds to an error band of ±1mV. For the best settling times, little or no peaking in the frequency response can be allowed. Using the recommended RISO for capacitive loads will limit this peaking and reduce the settling times. Fast, extremely fine scale settling (0.01%) requires close attention to the ground return currents in the supply de-coupling capacitors. De-coupling the output stage power supply connections (+VS2 + (–VS2)) separately from the main supply inputs will improve both settling and harmonic distortion performance. As can be observed in the typical performance curves, the OPA655 recovers very quickly from an input overdrive. For non-inverting operation, recovery is immediate for negative overdrives and < 10ns for a positive going overdrive signal. For inverting mode operation, such as transimpedance amplifiers, recovery is immediate to input overdrives that do not build up input voltages that exceeds the common mode input range. Unlike older FET input amplifiers, overdriving the inputs does not cause the output to invert phase and/or latch. Inputs that exceed the positive supply voltage will, however, cause the output to reverse and swing negative— but no latching will occur. HARMONIC DISTORTION The Typical Performance Curves show the very low harmonic distortion that OPA655 can deliver into a 100Ω load over a wide range of operating conditions. Generally, distortion improves at lower gains, lower signal swings, lower frequencies, and higher loads. Figure 12 shows significant improvement in second harmonic distortion as the load is increased, and relative insensitivity of the third harmonic to load conditions. For measurement purposes, these distortion levels were increased from those listed in the specification table by increasing the gain to +5. Narrowband communications systems will benefit from the very low third order distortion vs load which will provide very low intermodulation spurs. ® OPA655 12 –50 VO = 2Vp-p, G = +5, fO = 5MHz Harmonic Distortion (dBc) –60 –70 2fO –80 THERMAL CONSIDERATIONS The OPA655 will not require heatsinking under most operating conditions. Maximum desired junction temperature will limit the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +175°C. Operating junction temperature (T J ) is given by TA + PD • θJA. The total internal power dissipation (PD) is a combination of the quiescent power plus the power dissipated in the output stage to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is a fixed DC voltage equal to 1/2 of either supply voltage (assuming equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. Note that it is the power dissipated in the output stage and not in the load that determines internal power dissipation. As an example, compute the maximum TJ for the OPA655U at G = +2, RL = 100Ω, RF = 100Ω, ±VS = ±5V, and at the specified maximum TA = 85°C. PD = 10V • 31mA + (52)/[4 • (100 || 200)] = 404mW. Maximum TJ = 85°C + 0.404W • 125°C/W = 136°C. LAYOUT AND INTERCONNECT CONSIDERATIONS Achieving optimum performance with a high frequency amplifier like the OPA655 requires careful attention to layout parasitics and selection of external components. Suggestions include: • Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes. Otherwise, ground and power planes should be unbroken elsewhere on the board. • Minimize the distance (< 0.25") from the four power pins to high frequency 0.1µF decoupling capacitors. At the pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. The OPA655 may be operated with only pins 4 and 7 connected as supply pins allowing a direct replacement into existing 8 pin op amp pinouts. Connecting the output stage power pins separately, and decoupling them, will give the best distortion and settling performance. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. –90 3fO –100 10 100 Load Resistance (Ω) 1000 FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance. DIFFERENTIAL GAIN AND DIFFERENTIAL PHASE The OPA655 provides one of the lowest dG/dP errors of any op amp. This specification is the change in the small signal gain and phase for a composite video color carrier frequency when the output voltage is slowly ramped over the luminance range. The specifications show less than 0.01%/0.01° for positive NTSC into a single video load. This level of performance challenges the accuracy of commercially available video test equipment. Measurements were taken using an HP9480 IC parametric test system. OUTPUT DRIVE CAPABILITY The guaranteed output current of ±28mA will drive a 100Ω load over the full guaranteed output voltage range of ±2.8V. These minimum performance levels are only applicable at cold temperatures, with higher output voltage and current available in most applications. Many demanding high speed applications, such as driving ADC’s, require amplifiers with low, broadband, output impedance. As shown in Figure 13, the OPA655 maintains a very low closed loop output impedance over frequency. Closed loop output impedance increases with frequency as the loop gain rolls off. 10 G = +1 Output Impedance (Ω) 1 0.1 0.01 0.001 10k 100k 1M Frequency (Hz) 10M 100M FIGURE 13. Small-Signal Output Impedance vs Frequency. ® 13 OPA655 • Careful selection and placement of external components will preserve the high frequency performance of the OPA655. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axiallyleaded resistors can also provide good high frequency performance. Again, keep their leads as short as possible. Never use wirewound type resistors in the signal path for a high frequency application. For the lowest parasitic capacitance, consider the PR8351 style resistor from Precision Resistive Products (Phone No. 319-394-9131). These precision buffed resistors typically have less than 0.02pF shunt parasitic capacitance. Since the output pin and inverting input pin are most sensitive to parasitic capacitance, always place the feedback, gain setting, and series output resistor (if any) as close as possible to the package pins. For a voltage follower buffer application, a wide trace (0.1") on the component side of the board between pins 6 and 2 will reduce frequency response peaking. Be sure to open up ground and power planes around this trace to limit parasitic capacitance to an AC ground on the output pin. • Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic loads may not need an RISO since the OPA655 is nominally compensated to operate with a 5pF parasitic load. If a long trace is required and the 6dB signal loss intrinsic to doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the distortion vs load plot. With a characteristic impedance defined based on board material and desired trace dimensions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device; the total effective impedance should match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. • Socketing a high speed part like the OPA655 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it impossible to achieve a smooth, stable response. Best results are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush mount pins (e.g. McKenzie Technology No. 710C) can give good results. SPICE MODEL AND EVALUATION BOARDS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE models are available on a disk from the Burr-Brown Applications Department. The OPA655 is similar in distortion performance and identical in pinout to the OPA642. The demonstration boards developed for the OPA642 are recommended for the OPA655. The six boards available are: Contact your local Burr-Brown sales office or distributor to order demonstration boards. DEM-OPA64XP-F DEM-OPA64XP-N DEM-OPA64XP-I DEM-OPA64XU-F DEM-OPA64XU-N DEM-OPA64XU-I 8-pin DIP, unity gain follower configuration 8-pin DIP, non-inverting gain configuration 8-pin DIP, inverting gain configuration SO-8 Surface Mount, unity gain follower configuration SO-8 Surface Mount, non-inverting gain configuration SO-8 Surface Mount, inverting gain configuration ® OPA655 14