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SN65HVD233-Q1, SN65HVD234-Q1, SN65HVD235-Q1
SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
SN65HVD23x-Q1 3.3-V Automotive CAN Bus Transceivers
1 Features
3 Description
•
•
•
The SN65HVD233-Q1, SN65HVD234-Q1, and
SN65HVD235-Q1 devices are fault-protected 3.3-V
CAN transceivers that are qualified for use in
automotive applications. These transceivers work
from a 3.3-V supply and are ideal for systems that
also leverage a 3.3-V microcontroller, thereby
reducing the need for additional components or a
separate supply to power the controller and the CAN
transceiver. The SN65HVD23x-Q1 transceivers are
compatible with the ISO 11898-2 standard and thus
are interoperable in mixed networks that employ 5-V
CAN and/or 3.3-V CAN transceivers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compatible With ISO 11898-2
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Levels
– Bus Pins: ±12 000 V
– Other Pins: ±3 000 V
– Device CDM ESD Classification Level
±1 000 V
Single 3.3-V Supply Voltage
Bit Rates up to 1 Mbps
Bus Pins Fault Protection up to ±36 V
–7-V to 12-V Common-Mode Range
High Input Impedance Allows for 120 Nodes
LVTTL I/Os are 5-V Tolerant
GIFT/ICT Compliant
Adjustable Driver Slew Rates for Improved
Emissions Performance
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode, 200-μA (Typical)
Average Power Dissipation: 36.4 mW
SN65HVD233-Q1: Loopback Mode
SN65HVD234-Q1: Ultralow-Current Sleep Mode
– 50-nA Typical Current Consumption
SN65HVD235-Q1: Autobaud Loopback Mode
Thermal Shutdown Protection
Power Up and Down With Glitch-Free Bus Inputs
and Outputs
– High Input Impedance With Low VCC
– Monotonic Output During Power Cycling
2 Applications
•
•
•
•
•
•
In-Vehicle Networking
Advanced Driver-Assistance Systems (ADAS)
Body Electronics and Lighting
Infotainment and Cluster
Hybrid, Electric, and Powertrain Systems
Applications in Accordance With CAN Bus
Standards Such as NMEA 2000 and SAE J1939
Designed for operation in especially harsh
environments, the devices feature crosswire
protection, overvoltage protection on the CANH and
CANL pins up to ±36 V, loss-of-ground protection,
overtemperature (thermal shutdown) protection, and
common-mode transient protection of ±100 V. These
devices operate over a wide –7-V to 12-V commonmode range. These transceivers are the interface
between the host CAN controller on the
microprocessor and the differential CAN bus used in
transportation and automotive applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65HVD233-Q1
SN65HVD234-Q1
SOIC (8)
4.90 mm × 3.91 mm
SN65HVD235-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VCC
VCC
VCC
Bias Unit
1
TXD
VCC
RS
AB, EN,
or LBK
Slope Control
and
Mode Logic
RXD
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD233-Q1, SN65HVD234-Q1, SN65HVD235-Q1
SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
5
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
5
5
5
6
6
7
7
8
8
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: Driver ...............................
Electrical Characteristics: Receiver ..........................
Switching Characteristics: Driver ..............................
Switching Characteristics: Receiver..........................
Switching Characteristics: Device .............................
Typical Characteristics ............................................
9 Parameter Measurement Information ................ 11
10 Detailed Description ........................................... 18
10.1
10.2
10.3
10.4
Overview ...............................................................
Functional Block Diagrams ...................................
Feature Description...............................................
Device Functional Modes......................................
18
18
18
20
11 Application and Implementation........................ 22
11.1 Application Information.......................................... 22
11.2 Typical Application ................................................ 23
11.3 System Example ................................................... 25
12 Power Supply Recommendations ..................... 26
13 Layout................................................................... 26
13.1 Layout Guidelines ................................................. 26
13.2 Layout Example .................................................... 27
14 Device and Documentation Support ................. 28
14.1
14.2
14.3
14.4
14.5
14.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
15 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2016) to Revision A
Page
•
Deleted extra words "all pins except" in the test condition for CANH, CANL pins to GND ................................................... 5
•
Added ESD performance information between CANH and CANL pins ................................................................................ 5
2
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
5 Description (continued)
Modes: The RS pin (pin 8) of the SN65HVD233-Q1, SN65HVD234-Q1, and SN65HVD235-Q1 devices provides
three modes of operation: high-speed, slope control, and low-power standby mode. The high-speed mode of
operation is selected by connecting pin 8 directly to ground, allowing the driver output transistors to switch on
and off as fast as possible with no limitation on the rise and fall slope. The rise and fall slope can be adjusted by
connecting a resistor between the RS pin and ground. The slope is proportional to the output current of the pin.
With a resistor value of 10 kΩ the device driver has a slew rate of approximately 15 V/μs, and with a value of
100 kΩ the device has a slew rate of approximately 2 V/μs. For more information about slope control, see
Feature Description.
The SN65HVD233-Q1, SN65HVD234-Q1, and SN65HVD235-Q1 devices enter a low-current standby (listenonly) mode during which the driver is switched off and the receiver remains active if a high logic level is applied
to the RS pin. If the local protocol controller must transmit a message to the bus, it must return also the device to
either high-speed mode or slope-control mode via the RS pin.
Loopback (SN65HVD233-Q1): A logic high on the loopback (LBK) pin (pin 5) of the SN65HVD233-Q1 device
places the bus output and bus input in a high-impedance state. Internally, the TXD-to-RS path of the device
remains active and available for driver-to-receiver loopback that can be used for self-diagnostic node functions
without disturbing the bus. For more information on the loopback mode, see Feature Description.
Ultralow-Current Sleep (SN65HVD234-Q1): The SN65HVD234-Q1 device enters an ultralow-current sleep
mode in which both the driver and receiver circuits are deactivated if a low logic level is applied to EN pin (pin 5).
The device remains in this sleep mode until the circuit is reactivated by applying a high logic level to pin 5.
Autobaud Loopback (SN65HVD235-Q1): The AB pin (pin 5) of the SN65HVD235-Q1 device implements a bus
listen-only loopback feature which allows the local node controller to synchronize its baud rate with that of the
CAN bus. In autobaud mode, the bus output of the driver is placed in a high-impedance state while the bus input
of the receiver remains active. There is an internal TXD pin to RS pin loopback to assist the controller in baud
rate detection, or the autobaud function. For more information on the autobaud mode, see Feature Description.
6 Device Comparison Table
LOW-POWER MODE
SLOPE
CONTROL
DIAGNOSTIC
LOOPBACK
AUTOBAUD
LOOPBACK
SN65HVD233-Q1
200-μA standby mode
Adjustable
Yes
No
SN65HVD234-Q1
200-μA standby mode or 50-nA sleep mode
Adjustable
No
No
SN65HVD235-Q1
200-μA standby mode
Adjustable
No
Yes
PART NUMBER (1)
(1)
For the most-current package and ordering information, see the orderable addendum at the end of the data sheet, or see the TI Web
site at www.ti.com.
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
www.ti.com
7 Pin Configuration and Functions
D Package
8-Pin SOIC
SN65HVD233-Q1 Top View
D Package
8-Pin SOIC
SN65HVD234-Q1 Top View
TXD
1
8
RS
TXD
1
8
RS
GND
2
7
CANH
GND
2
7
CANH
VCC
3
6
CANL
VCC
3
6
CANL
RXD
4
5
LBK
RXD
4
5
EN
Not to scale
Not to scale
D Package
8-Pin SOIC
SN65HVD235-Q1 Top View
TXD
1
8
RS
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
AB
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
'233-Q1
'234-Q1
'235-Q1
AB
—
—
5
I
CANH
7
7
7
I/O
High-level CAN bus line
CANL
6
6
6
I/O
Low-level CAN bus line
EN
—
5
—
I
GND
2
2
2
—
LBK
5
—
—
I
SN65HVD233-Q1 device: Loopback-mode input pin (LBK). Can be tied to ground if
not used. Can also be left open if unused because the internal pulldown biases this
toward ground.
RS
8
8
8
I
Mode-select pin: strong pulldown to GND = high-speed mode, strong pullup to VCC
= low-power mode, 10-kΩ to 100-kΩ pulldown to GND = slope-control mode
RXD
4
4
4
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
TXD
1
1
1
I
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
VCC
3
3
3
I
Transceiver 3.3-V supply voltage
4
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SN65HVD235-Q1 device: Autobaud loopback mode-input pin (AB). Can be tied to
ground if not used. Can also be left open if unused because the internal pulldown
biases this toward ground.
SN65HVD234-Q1 device: Enable input pin. Logic high for enabling a normal mode
(high-speed or slope-control mode). Logic low for sleep mode. (EN)
Ground connection
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Product Folder Links: SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1
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www.ti.com
SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
8 Specifications
8.1 Absolute Maximum Ratings
over operating ambient temperature range unless otherwise noted (1) (2)
MIN
MAX
UNIT
Supply voltage
–0.3
7
V
Voltage at any bus terminal (CANH or CANL)
–36
36
V
Voltage input, transient pulse, CANH and CANL, through 100 Ω (see
Figure 18)
–100
100
V
VI
Input voltage, (AB, EN, LBK, RS, TXD)
–0.5
7
V
VO
Output voltage (RXD)
–0.5
7
V
IO
Receiver output current
–10
10
mA
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
125
°C
VCC
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to the network ground pin.
8.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002 (1)
CANH, CANL to GND
±12 000
Between CANH and
CANL
±16 000
All pins
±3 000
Charged-device model (CDM), per AEC Q100-011
(1)
UNIT
V
±1 000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
VCC
MIN
MAX
Supply voltage
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
EN, AB, LBK, TXD
VIL
Low-level input voltage
EN, AB, LBK, TXD
VID
Differential input voltage between CANH and CANL
3
3.6
V
–7
12
V
2
5.5
V
V
0
0.8
–6
6
0
100
kΩ
0.75 VCC
5.5
V
Resistance from RS to ground
VI(Rs)
Input voltage at RS for standby
IOH
High-level output current
IOL
Low-level output current
TA
Operating ambient temperature (1)
(1)
UNIT
Driver
–50
Receiver
–10
mA
Driver
50
Receiver
10
–40
V
125
mA
°C
Maximum ambient temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
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8.4 Thermal Information
SN65HVD23x-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
102.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.1
°C/W
RθJB
Junction-to-board thermal resistance
43.8
°C/W
ψJT
Junction-to-top characterization parameter
7.3
°C/W
ψJB
Junction-to-board characterization parameter
43.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics: Driver
over operating ambient temperature range (unless otherwise noted)
PARAMETER
VO(D)
Bus output voltage
(dominant)
CANH
VO
Bus output voltage
(recessive)
CANH
VOD(D)
MIN TYP (1)
TEST CONDITIONS
CANL
CANL
Differential output voltage (dominant)
VOD
Differential output voltage (recessive)
VOC(pp)
Peak-to-peak common-mode output voltage
IIH
High-level input current
AB, EN, LBK,
TXD
IIL
Low-level input current
AB, EN, LBK,
TXD
TXD at 0 V, RS at 0 V, see Figure 12 and
Figure 13
Short-circuit output current
VCC
0.5
1.25
2.3
TXD at 3 V, RS at 0 V, see Figure 12 and
Figure 13
1.5
2
3
TXD at 0 V, RS at 0 V, see Figure 13 and
Figure 14
1.2
2
3
TXD at 3 V, RS at 0 V, see Figure 12 and
Figure 13
–120
TXD at 3 V, RS at 0 V, no load
–0.5
See Figure 21
12
0.05
1
μA
TXD = 0.8 V or EN = 0.8 V or LBK = 0.8 V or
AB = 0.8 V
–30
30
μA
–250
VCANH = 12 V, CANL open, see Figure 26
VCANL = –7 V, CANH open, see Figure 26
IIRs(s)
RS input current for standby
RS at 0.75 VCC
(1)
6
V
30
See CI, Input capacitance in Electrical
Characteristics: Receiver
1
–1
–10
μA
EN at 0 V, TXD at VCC, RS at 0 V or VCC
0.05
2
Standby
RS at VCC, TXD at VCC, AB at 0 V, LBK at 0 V,
EN at VCC
200
600
Dominant
TXD at 0 V, no load, AB at 0 V, LBK at 0 V,
RS at 0 V, EN at VCC
6
Recessive
TXD at VCC, no load, AB at 0 V, LBK at 0 V,
RS at 0 V, EN at VCC
6
RL = 60 Ω, RS at 0 V, input to D a 1-MHz 50%
duty
cycle square wave VCC at 3.3 V, TA = 25°C
mA
250
Sleep
Average power dissipation
V
–30
Output capacitance
P(AVG)
mV
TXD = 2 V or EN = 2 V or LBK = 2 V or AB =
2V
CO
Supply current
V
V
VCANL = 12 V, CANH open, see Figure 26
ICC
UNIT
V
2.3
TXD at 0 V, RS at 0 V, see Figure 12 and
Figure 13
VCANH = –7 V, CANL open, see Figure 26
IOS
MAX
2.45
μA
mA
36.4
mW
All typical values are at 25°C and with a 3.3-V supply.
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
8.6 Electrical Characteristics: Receiver
over operating ambient temperature range (unless otherwise noted)
PARAMETER
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
TEST CONDITIONS
AB at 0 V, LBK at 0 V, EN at VCC, see Table 1
VOH
High-level output voltage
IO = –4 mA, See Figure 17
VOL
Low-level output voltage
IO = 4 mA, See Figure 17
CANH or CANL at 12 V,
VCC at 0 V
Bus input current
CANH or CANL at –7 V
CANH or CANL at –7 V,
VCC at 0 V
MAX
UNIT
750
900
mV
500
650
mV
100
mV
0.8 ×
VCC
V
0.4
CANH or CANL at 12 V
II
MIN TYP (1)
Other bus pin at 0 V,
TXD at 3 V, AB at 0 V,
LBK at 0 V, RS at 0 V,
EN at VCC
150
500
200
600
–610
–150
–450
–130
V
μA
CI
Input capacitance (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V, TXD at 3 V,
AB at 0 V, LBK at 0 V, EN at VCC
40
pF
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, TXD at 3 V,
AB at 0 V, LBK at 0 V, EN at VCC
20
pF
RID
Differential input resistance
RIN
Input resistance (CANH or CANL) to
ground
ICC
(1)
Supply current
TXD at 3 V, AB at 0 V, LBK at 0 V, EN at VCC
40
100
kΩ
20
50
kΩ
Sleep
EN at 0 V, TXD at VCC, RS at 0 V or VCC
0.05
2
Standby
RS at VCC, TXD at VCC, AB at 0 V, LBK at 0 V, EN at
VCC
200
600
Dominant
TXD at 0 V, no load, RS at 0 V, LBK at 0 V, AB at 0 V,
EN at VCC
6
Recessive
TXD at VCC, no load, RS at 0 V, LBK at 0 V, AB at 0 V,
EN at VCC
6
μA
mA
All typical values are at 25°C and with a 3.3-V supply.
8.7 Switching Characteristics: Driver
over operating ambient temperature range (unless otherwise noted)
PARAMETER
Propagation delay time,
low-to-high-level output
tPLH
TEST CONDITIONS
MIN
35
85
RS with 10 kΩ to ground, see Figure 15
70
125
RS with 100 kΩ to ground, see Figure 15
500
870
70
120
RS with 10 kΩ to ground, see Figure 15
130
180
RS with 100 kΩ to ground, see Figure 15
870
1200
RS at 0 V, see Figure 15
tsk(p)
Pulse skew (|tPHL – tPLH|)
Differential output signal rise time
RS with 10 kΩ to ground, see Figure 15
60
RS with 100 kΩ to ground, see Figure 15
370
20
Differential output signal fall time
ten(s)
Enable time from standby to dominant
ten(z)
Enable time from sleep to dominant
(1)
ns
ns
ns
70
RS with 10 kΩ to ground, see Figure 15
30
135
RS with 100 kΩ to ground, see Figure 15
350
1400
20
70
RS at 0 V, see Figure 15
tf
UNIT
35
RS at 0 V, see Figure 15
tr
MAX
RS at 0 V, see Figure 15
RS at 0 V, see Figure 15
Propagation delay time,
high-to-low-level output
tPHL
TYP (1)
RS with 10 kΩ to ground, see Figure 15
30
135
RS with 100 kΩ to ground, see Figure 15
350
1400
See Figure 19 and Figure 20
ns
ns
0.6
1.5
μs
1
5
μs
All typical values are at 25°C and with a 3.3-V supply.
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8.8 Switching Characteristics: Receiver
over operating ambient temperature range (unless otherwise noted)
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
UNIT
tPLH
Propagation delay time, CANH input low to RXD output high
35
60
ns
tPHL
Propagation delay time, CANH input high to RXD output low
35
60
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Output signal rise time
2
5
ns
tf
Output signal fall time
2
5
ns
(1)
See Figure 17
7
ns
All typical values are at 25°C and with a 3.3-V supply.
8.9 Switching Characteristics: Device
over operating ambient temperature range (unless otherwise noted)
PARAMETER
t(LBK)
Loopback delay, driver input to
receiver output
t(AB1)
Loopback delay, driver input to
receiver output
MIN TYP (1)
MAX
See Figure 23
7.5
12
ns
See Figure 24
10
20
ns
See Figure 25
35
60
ns
TEST CONDITIONS
'HVD233-Q1
'HVD235-Q1
t(AB2)
Loopback delay, bus input to
receiver output
t(loop1)
Total loop delay, driver input to receiver output,
recessive to dominant
RS at 0 V, see Figure 22
70
135
RS with 10 kΩ to ground, see Figure 22
105
190
RS with 100 kΩ to ground, see Figure 22
535
1000
70
135
RS at 0 V, see Figure 22
t(loop2)
(1)
8
UNIT
Total loop delay, driver input to receiver output,
dominant to recessive
RS with 10 kΩ to ground, see Figure 22
105
190
RS with 100 kΩ to ground, see Figure 22
535
1000
ns
ns
All typical values are at 25°C and with a 3.3-V supply.
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
8.10 Typical Characteristics
RS = LBK = AB = 0 V; EN = VCC
95
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
85
Dominant-to-Recessive Loop Time (ns)
Recessive-to-Dominant Loop Time (ns)
90
80
75
70
65
60
-40
0
40
80
Ambient Temperature (qC)
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
90
85
80
75
70
65
-40
120
0
D001
Figure 1. Recessive-to-Dominant Loop Time vs Ambient
Temperature
40
80
Ambient Temperature (qC)
120
D002
Figure 2. Dominant-to-Recessive Loop Time vs Ambient
Temperature
160
20
140
Driver Output Current (mA)
Supply Current (mA)
19
18
17
16
120
100
80
60
40
20
15
200
0
300
400
VCC = 3.3 V
500
600
700
Frequency (kbps)
800
TA = 25°C
900
0
1000
RL = 60-Ω Load
VCC = 3.3 V
0.12
2.2
0.1
2
0.08
0.06
0.04
0.02
0
0.5
VCC = 3.3 V
1
1.5
2
2.5
High Level Output Voltage (V)
3
3.5
D004
TA = 25°C
1.8
1.6
1.4
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
1.2
1
-40
D005
TA = 25°C
Figure 5. Driver High-Level Output Current vs High-Level
Output Voltage
Copyright © 2016, Texas Instruments Incorporated
4
Figure 4. Driver Low-Level Output Current vs Low-Level
Output Voltage
Differential Output Voltege (V)
Driver High-Level Output Current (mA)
Figure 3. Supply Current vs Frequency
0
1
2
3
Low-Level Output Voltage (V)
D003
0
40
80
Ambient Temperature (qC)
120
D006
RL = 60 Ω
Figure 6. Differential Output Voltage vs Ambient
Temperature
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Typical Characteristics (continued)
RS = LBK = AB = 0 V; EN = VCC
Receiver Low-to-High Propagation Delay (ns)
Reciever Low-to-High Propagation Delay (ns)
45
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
44
43
42
41
40
39
38
37
36
35
-40
0
40
80
Ambient Temperature (qC)
120
38
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
37
36
35
34
33
32
-40
See Figure 3
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
45
40
35
30
0
120
D008
Figure 8. Receiver High-to-Low Propagation Delay vs
Ambient Temperature
Driver Low-to-High Propagation Delay (ns)
Driver Low-to-High Propagation Delay (ns)
55
25
-40
40
80
Ambient Temperature (qC)
See Figure 3
Figure 7. Receiver Low-to-High Propagation Delay vs
Ambient Temperature
50
0
D007
40
80
Ambient Temperatrue (qC)
120
65
60
55
50
45
40
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
35
30
-40
0
D009
See Figure 1
40
80
Ambient Temperatrue (qC)
120
D001
D010
See Figure 1
Figure 9. Driver Low-to-High Propagation Delay vs Ambient
Temperature
Figure 10. Driver High-to-Low Propagation Delay vs
Ambient Temperature
35
Driver Output Current (mA)
30
25
20
15
10
5
0
-5
0
0.6
TA = 25°C
1.2
1.8
2.4
Supply Voltage (V)
3
3.6
D011
RL = 60 Ω
Figure 11. Driver Output Current vs Supply Voltage
10
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
9 Parameter Measurement Information
IO(CANH)
II TXD
60 W ±1%
VO(CANH)
VOD
VO(CANH) + VO(CANL)
II(RS)
RS
VI
VI(RS)
–
2
VOC
IO(CANL)
+
VO(CANL)
Figure 12. Driver Voltage, Current, and Test Definition
Dominant
Recessive
≈3V
VO(CANH)
≈ 2.3 V
≈1V
VO(CANL)
Figure 13. Bus Logic State Voltage Definitions
TXD
VI
CANH
330 W ±1%
VOD
60 W ±1%
+
_
RS
CANL
–7 V ≤ VTEST ≤ 12 V
330 W ±1%
Figure 14. Driver VOD
CANH
VCC
CL = 50 pF ±20%
(see Note B)
TXD
VI
RL = 60 W ±1%
RS +
(see Note A)
VI(RS)
–
VCC / 2
VI
VO
0V
tPLH
VO
VCC / 2
tPHL
VO(D)
90%
0.9 V
0.5 V
10%
CANL
tr
VO(R)
tf
A.
The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
CANH
RXD
VIC =
VI(CANH) + VI(CANL)
IO
VID
VI(CANH)
2
VO
CANL
VI(CANL)
Figure 16. Receiver Voltage and Current Definitions
2.9 V
CANH
2.2 V
VI
RXD
1.5 V
IO
VI
(see Note A)
1.5 V
tPLH
CL = 15 pF ±20%
(see Note B)
CANL
2.2 V
tPHL
VO
VO
50%
10%
90%
90%
tr
VOH
50%
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
–6.1 V
–7 V
L
12 V
11.1 V
L
–1 V
–7 V
L
MEASURED
RXD
|VID|
900 mV
900 mV
VOL
6V
12 V
6V
L
6V
–6.5 V
–7 V
H
500 mV
12 V
11.5 V
H
500 mV
–7 V
–1 V
H
6V
12 V
H
6V
Open
Open
H
X
VOH
6V
CANH
RXD
100 W
Pulse Generator
15 µs Duration
1% Duty Cycle
tr, tf ≤100 ns
CANL
TXD at 0 V or VCC
RS, AB, EN, LBK, at 0 V or VCC
NOTE: This test is conducted to test survivability only. Data stability at the RXD output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test
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’HVD234-Q1
’HVD233-Q1 or ’HVD235-Q1
RS
VI
CANH
TXD
0V
AB or LBK
VI
60 W ±1%
0V
VCC
CANL
VO
CANH
TXD
60 W ±1%
EN
CANL
VO
RXD
+
RS
+
15 pF ±20%
15 pF ±20%
–
–
VCC
50%
VI
0V
VOH
50%
VO
VOL
ten(s)
Copyright © 2016, Texas Instruments Incorporated
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate
(PRR) = 125 kHz, 50% duty cycle.
Figure 19. ten(s) Test Circuit and Voltage Waveforms
’HVD234-Q1
RS
0V
VI
VCC
CANH
TXD
60 W ±1%
+
VI
0V
EN
VOH
CANL
50%
VO
RXD
VO
50%
VOL
ten(z)
15 pF ±20%
–
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤6 ns, pulse repetition rate (PRR) = 50 kHz, 50% duty cycle.
Copyright © 2016, Texas Instruments Incorporated
Figure 20. ten(z) Test Circuit and Voltage Waveforms
CANH
VI
27 W ±1%
VOC(PP)
TXD
VOC
RS
CANL
27 W ±1%
VOC
50 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 21. VOC(pp) Test Circuit and Voltage Waveforms
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0 W, 10 kW,
or 100 kW ±5%
DUT
RS
CANH
TXD
VI
+
VCC
50%
VI
60 W ±1%
LBK or AB
’HVD233-Q1, -235-Q1
EN
VCC
’HVD234-Q1
RXD
VO
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50%
0V
t(loop2)
CANL
t(loop1)
50%
VO
VOH
50%
VOL
15 pF ±20%
–
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Copyright © 2016, Texas Instruments Incorporated
Figure 22. t(loop) Test Circuit and Voltage Waveforms
RS
’HVD233-Q1
+
VOD
–
D
VI
LBK
VCC
VCC
CANH
50%
VI
50%
0V
60 W ±1%
t(LBK1)
CANL
t(LBK2)
50%
VO
R
VO
VOL
t(LBK) = t(LBK1) = t(LBK2)
VOD
+
VOH
50%
≈2.3 V
15 pF ±20%
–
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Copyright © 2016, Texas Instruments Incorporated
Figure 23. t(LBK) Test Circuit and Voltage Waveforms
RS
VI
’HVD235-Q1
+
VOD
–
TXD
VOD
CANH
VCC
60 W ±1%
50%
VI
t(ABH)
AB
VO
RXD
50%
0V
CANL
VCC
≈2.3 V
t(ABL)
50%
VOH
50%
VOL
t(AB1) = t(ABH) = t(ABL)
VO
+
15 pF ±20%
–
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
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Figure 24. t(AB1) Test Circuit and Voltage Waveforms
14
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
RS
’HVD235-Q1
CANH
TXD
VCC
VI
AB
VCC
2.9 V
60 W ±1%
CANL
2.2 V
2.2 V
VI
1.5 V
t(ABH)
1.5 V
t(ABL)
50%
VO
VOH
50%
RXD
VOL
t(AB2) = t(ABH) = t(ABL)
VO
+
15 pF ±20%
–
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Copyright © 2016, Texas Instruments Incorporated
Figure 25. t(AB2) Test Circuit and Voltage Waveforms
ú| IOS |
IOS
TXD
0 V or VCC
15 s
CANH
+
_
IOS
0V
VI
12 V
CANL
0V
0V
VI
and
10 µs
VI
–7 V
Figure 26. IOS Test Circuit and Waveforms
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3.3 V
TA = 25°C
VCC = 3.3 V
R2 ±1%
CANH
RXD
CANL
R1 ±1%
+
VID
–
R2 ±1%
Vac
R1 ±1%
VI
The RXD Output State Does Not Change During
Application of the Input Waveform.
VID
R1
R2
500 mV
50 W
280 W
900 mV
50 W
130 W
12 V
VI
–7 V
NOTE: All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 27. Common-Mode Voltage Rejection
16
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
TXD INPUT
RS INPUT
CANH INPUT
VCC
VCC
VCC
110 kW
100 kW
INPUT
1 kW
9 kW
45 kW
INPUT
9V
+
_
INPUT
CANH and CANL OUTPUTS
CANL INPUT
VCC
9 kW
40 V
VCC
RXD OUTPUT
VCC
9 kW
110 kW
5W
45 kW
INPUT
OUTPUT
OUTPUT
9 kW
40 V
9V
40 V
EN INPUT
LBK or AB INPUT
VCC
INPUT
1 kW
9V
VCC
INPUT
100 kW
1 kW
9V
100 kW
Figure 28. Equivalent Input and Output Schematic Diagrams
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10 Detailed Description
10.1 Overview
This family of CAN transceivers is compatible with the ISO 11898-2 high-speed controller-area-network (CAN)
physical layer standard. These devices are designed to interface between the differential bus lines in CAN and
the CAN protocol controller at data rates up to 1 Mpbs.
10.2 Functional Block Diagrams
RS
CANH
TXD
CANL
LBK
RXD
LBK
Figure 29. SN65HVD233-Q1 Functional Block Diagram
RS
CANH
TXD
CANL
EN
RXD
Figure 30. SN65HVD234-Q1 Functional Block Diagram
RS
CANH
TXD
CANL
AB
RXD
Figure 31. SN65HVD235-Q1 Functional Block Diagram
10.3 Feature Description
10.3.1 Diagnostic Loopback (SN65HVD233-Q1)
The diagnostic loopback or internal loopback function of the SN65HVD233-Q1 device is enabled with a high-level
input on pin 5, LBK. This mode disables the driver output while keeping the bus pins biased to the recessive
state. This mode also redirects the TXD data input (transmit data) through logic to the received data output pin,
thus creating an internal loopback of the transmit-to-receive data path. This mimics the loopback that occurs
normally with a CAN transceiver, because the receiver loops back the driven output to the RXD (receive data)
pin. This mode allows the host protocol controller to input and read back a bit sequence or CAN messages to
perform diagnostic routines without disturbing the CAN bus. A typical CAN bus application is displayed in
Figure 37.
18
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Feature Description (continued)
If the LBK pin is not used, it may be tied to ground (GND). However, it is pulled low internally (defaults to a lowlevel input) and may be left open if not in use.
10.3.2 Autobaud Loopback (SN65HVD235-Q1)
The autobaud loopback mode of the SN65HVD235-Q1 device is enabled by placing a high-level input on pin 5,
AB. In autobaud mode, the driver output is disabled, thus blocking the TXD pin-to-bus path and the bus transmit
function of the transceiver. The bus pins remain biased to recessive. The receiver-to-RXD pin path of the device
remains operational, allowing bus activity to be monitored. In addition, the autobaud mode includes an internal
logic loopback path from the TXD pin to the RXD pin so the local node can transmit to itself in sync with bus
traffic while not disturbing messages on the bus. Thus if the CAN controller of the local node generates an error
frame, it is not transmitted to the bus, but is detected only by the local CAN controller. This is especially helpful to
determine if the local node is set to the same baud rate as the network, and if not, to adjust it to the network
baud rate (autobaud detection).
Autobaud detection is best suited to applications that have a known selection of baud rates. For example, if an
application has optional settings of 125 kbps, 250 kbps, or 500 kbps. Once the SN65HVD235-Q1 device is
placed into autobaud loopback mode, the application software could assume the first baud rate of 125 kbps. It
then waits for a message to be transmitted by another node on the bus. If the wrong baud rate has been
selected, an error message is generated by the local CAN controller because the sample times will not be at the
correct time. However, because the bus-transmit function of the device has been disabled, no other nodes
receive the error frame generated by the local CAN controller of this node.
The application would then make use of the status register indications of the local CAN controller for messagereceived and error-warning status to determine if the set baud rate is correct or not. The warning status indicates
that the CAN controller error counters have been incremented. A message received status indicates that a good
message has been received. If an error is generated, the application then sets the CAN controller to the next
possibly valid baud rate, and waits to receive another message. This pattern is repeated until an error-free
message has been received, thus the correct baud rate has been selected. At this point, the application places
the SN65HVD235-Q1 device in a normal transmitting mode by setting pin 5 to a low level, thus enabling bustransmit and bus-receive functions to normal operating states for the transceiver.
If the AB pin is not used, it may be tied to ground (GND). However, it is pulled low internally (defaults to a lowlevel input) and may be left open if not in use.
10.3.3 Slope Control
The rise and fall slope of the SN65HVD233-Q1, SN65HVD234-Q1, and SN65HVD235-Q1 driver output can be
adjusted by connecting a resistor from RS (pin 8) to ground (GND) as shown in Figure 32, or to a low level input
voltage as shown in Figure 33.
The slope of the driver output signal is proportional to the output current of the pin. This slope control is
implemented with an external resistor value of 10 kΩ to achieve an approximately 15-V/µs slew rate, and up to
100 kΩ to achieve an approximately 2-V/μs slew rate. A typical slew-rate versus pulldown-resistance graph is
shown in Figure 34. Typical driver output waveforms with slope control are displayed in Figure 40.
RS
TXD
GND
VCC
RXD
1
2
3
4
8
7
6
5
CANH
CANL
LBK
10 kW
to
100 kW
Figure 32. Ground Connection for Selecting Slope-Control or Standby Mode
RS
TXD
GND
VCC
RXD
1
2
3
4
8
7
6
5
CANH
CANL
LBK
10 kW
to
100 kW
TI Controller
Figure 33. DSP Connection for Selecting Slope-Control or Standby Mode
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Feature Description (continued)
25
Slope (V / Ps)
20
15
10
5
0
0
10
20
30
40
50
60
70
80
Slope Control Resistance (k:)
90
100
D012
Figure 34. SN65HVD233-Q1 Driver Output-Signal Slope vs Slope-Control Resistance Value
10.3.4 Standby
If a high-level input (> 0.75 VCC) is applied to RS (pin 8), the circuit enters a low-current, listen only standby
mode during which the driver is switched off and the receiver remains active. If using this mode to save system
power while waiting for bus traffic, the local controller can monitor the RXD output pin for a falling edge which
indicates that a dominant signal was driven onto the CAN bus. The local controller can then drive the RS pin low
to return to slope-control mode or high-speed mode.
10.3.5 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shutdown threshold, the device turns off the CAN
driver circuits, thus blocking the TXD pin-to-bus transmission path. The shutdown condition is cleared when the
junction temperature drops sufficiently below the thermal shutdown temperature of the device. The CAN bus pins
are high-impedance and biased to the recessive level during a thermal shutdown, and the receiver-to-RXD pin
path remains operational.
10.4 Device Functional Modes
Table 2. Driver (SN65HVD233-Q1 or SN65HVD235-Q1)
INPUTS
OUTPUTS
TXD
LBK or AB
RS
CANH
CANL
BUS STATE
X
X
> 0.75 VCC
Z
Z
Recessive
L
L or open
H or open
X
X
H
≤ 0.33 VCC
≤ 0.33 VCC
H
L
Dominant
Z
Z
Recessive
Z
Z
Recessive
Table 3. Driver (SN65HVD234-Q1)
INPUTS
20
OUTPUTS
TXD
EN
RS
CANH
CANL
L
H
≤ 0.33 VCC
H
L
Dominant
H
X
≤ 0.33 VCC
Z
Z
Recessive
Open
X
X
Z
Z
Recessive
X
X
> 0.75 VCC
Z
Z
Recessive
X
L or open
X
Z
Z
Recessive
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BUS STATE
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SLLSES4A – SEPTEMBER 2016 – REVISED NOVEMBER 2016
Table 4. Receiver (SN65HVD233-Q1) (1)
INPUTS
BUS STATE
(1)
OUTPUT
VID = V(CANH) – V(CANL)
LBK
TXD
RXD
Dominant
VID ≥ 0.9 V
L or open
X
L
Recessive
VID ≤ 0.5 V or open
L or open
H or open
H
?
0.5 V < VID < 0.9 V
L or open
H or open
?
X
X
H
L
L
X
X
H
H
H
H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
Table 5. Receiver (SN65HVD235-Q1) (1)
INPUTS
(1)
OUTPUT
BUS STATE
VID = V(CANH)–V(CANL)
AB
TXD
Dominant
VID ≥ 0.9 V
L or open
X
RXD
L
Recessive
VID ≤ 0.5 V or open
L or open
H or open
H
?
0.5 V < VID
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