SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642 – MARCH 2009
INDUSTRIAL 8-DIGITAL-INPUT SERIALIZER WITH DIAGNOSTICS
FEATURES
1
• Eight Inputs
– High Input Voltage – up to 34 V
– Selectable Debounce Filters – 0 ms to 3 ms
– Flexible Input Current Limit: 0.2 to 5.2 mA
– Field Pins Protected to 15-kV HBM ESD
• Diagnostics:
– Parity Check
– Undervoltage Indication
– Overtemperature Indication
• Output Drivers for External Status LEDs
2
•
•
•
Cascadable in Multiples of Eight Inputs
SPI-Compatible Interface
Regulated 5-V Output for External Isolator
APPLICATIONS
•
•
•
•
Sensor Inputs for Industrial Automation and
Process Control
High Channel Count Digital Input Modules for
PC and PLC Systems
Decentralized I/O Modules
Motion Control Systems
DESCRIPTION
The SN65HVS881 is an eight channel, digital-input serializer for high-channel density digital input modules in
industrial automation. In combination with galvanic isolators the device completes the interface between the high
voltage signals on the field-side and the low-voltage signals on the controller side. Input signals are
current-limited and then validated by internal debounce filters.
With the addition of a few external components, the input switching characteristics can be configured in
accordance with IEC61131-2 for Type 1, 2 and 3 sensor switches.
Upon the application of load and clock signals, input data is latched in parallel into the shift register and
afterwards clocked out serially.
Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial
input of the following device, enabling the design of high-channel count input modules. Multiple devices can be
cascaded through a single serial port, reducing both the isolation channels and controller inputs required.
Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a
single external precision resistor. An integrated voltage regulator provides a 5V output to supply low-power
isolators. An on-chip temperature sensor provides diagnostic information for graceful shutdown and system
safety. An internal parity check for odd parity ensures trustworthy transmission of serial data to the system
controller.
The SN65HVS881 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The
device is characterized for operation at temperatures from –40°C to 125°C
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN65HVS881
SLAS642 – MARCH 2009................................................................................................................................................................................................... www.ti.com
Voltage
Regulator
VCC
Debounce Select
DB0 : DB1
Serial Input
5V
8
8
3
8
SERIALIZER
LED Outputs
RE0 : RE7
2
Signal
Conditioning
Field Inputs
IP0 : IP7
5V out
IREF Adj: RLIM
Field Ground
Control Inputs
LD, CE, CLK
Serial Output
DB0
DB1
IP0
RE0
IP1
RE1
IP2
RE2
IP3
RE3
IP4
RE4
RLIM
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
SIP
LD
CLK
CE
SOP
IP7
RE7
IP6
RE6
IP5
RE5
HOT
5VOP
FUNCTIONAL BLOCK DIAGRAM
Voltage
Regulator
VCC
5V
Thermal
Sensor
HOT
Debounce
Select
DB0
DB1
Supply
Monitor
GND
RLIM
5VOP
Adj. Current
Thresholds
SIP
Current
Sense
&
Voltage
Sense
Debounce
Filter
Channel 0
Parity
Generator
RE7
IP7
SERIALIZER
RE0
IP0
LD
CE
CLK
Channel 7
SOP
2
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Product Folder Link(s): SN65HVS881
SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642 – MARCH 2009
TERMINAL FUNCTIONS
TERMINAL
PIN NO.
NAME
DESCRIPTION
1, 2
DB0, DB1
3, 5, 7, 9,
11, 18, 20, 22
Debounce select inputs
IPx
Input channel x
4, 6, 8, 10,
12, 17, 19, 21
REx
Return path x (LED drive)
13
RLIM
Current limiting resistor
14
VCC
15
5VOP
5-V output to supply low-power isolators
16
HOT
Active low over-temperature indication
23
SOP
Serial data output
24
CE
Clock enable input
25
CLK
Serial clock input
26
LD
Load pulse input
27
SIP
Serial data input
28
GND
Field ground
Field supply voltage
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3
SN65HVS881
SLAS642 – MARCH 2009................................................................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 36
V
IPx
–0.5 to 36
V
Voltage at any logic input
DB0, DB1, CLK, SIP, CE, LD
–0.5 to 6
V
Output current
HOT, SOP
±8
mA
All pins
±4
IPx, VCC
±15
VCC
Field power input
VIPx
Field digital inputs
VID
IO
Human-Body Model (2)
VESD
Electrostatic discharge
PTOT
Continuous total power dissipation
TJ
Junction temperature
(1)
(2)
(3)
(4)
kV
Charged-Device Model (3)
All pins
±1
kV
Machine Model (4)
All pins
±100
V
170
°C
See Thermal Characteristics Table
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
JEDEC Standard 22, Method A114-A.
JEDEC Standard 22, Method C101
JEDEC Standard 22, Method A115-A
THERMAL CHARACTERISTICS
PARAMETER
θJA
Junction-to-air thermal resistance
θJB
Junction-to-board thermal
resistance
θJC
Junction-to-case thermal
resistance
PD
Device power dissipation
TEST CONDITIONS
MIN
High-K JEDEC thermal resistance model
IP0-IP7 =
ICC and IIP-LIM = worst case with
IP0-IP7 =
RLIM = 25 kΩ, ILOAD = 50 mA on 5VOP,
IP0-IP7 =
RE0-RE7 = GND, fIP = 100 MHz
IP0-IP7 =
TYP MAX
UNIT
35
°C/W
15
°C/W
4.27
°C/W
VCC = 34 V
2970
VCC = 30 V
2600
VCC = 24 V
2020
VCC = 12 V
890
mW
RECOMMENDED OPERATING CONDITIONS
MIN
NOM MAX
10
34
V
VCC
Field supply voltage
VIPL
Field input low-state input voltage
VIPH
Field input high-state input voltage
VIL
Logic low-state input voltage
VIH
Logic high-state input voltage
2.0
RLIM
Current limiter resistor
17
fIP (1)
Input data rate (each field input)
TA
TJ
(1)
4
Free-air temperature, see Thermal Characteristics
0
4
V
5.5
34
V
0
0.8
V
25
5.5
V
500
kΩ
0
1
VCC ≤ 34 V
–40
85
VCC ≤ 27 V
–40
105
VCC ≤ 18 V
–40
125
Junction temperature
UNIT
150
Mbps
°C
°C
Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω
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Product Folder Link(s): SN65HVS881
SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642 – MARCH 2009
ELECTRICAL CHARACTERISTICS
Over full-range of recommended operating conditions, unless otherwise noted
PARAMETER
TERMINAL
TEST CONDITIONS
MIN
TYP MAX
UNIT
FIELD INPUTS
VTH–(IP)
Low-level device input threshold
voltage
VTH+(IP)
High-level device input threshold
voltage
VHYS(IP)
Device input hysteresis
VTH–(IN)
Low-level field input threshold
voltage
VTH+(IN)
High-level field input threshold
voltage
VHYS(IN)
Field input hysteresis
VTH– (VCC)
Low-level VCC-monitor threshold
voltage
VTH+
(VCC)
High-level VCC-monitor threshold
voltage
VHYS
(VCC)
VCC-monitor hysteresis
4.0
IP0–IP7
RLIM = 25 kΩ
5.2
6
Measured at
field side of
RIN
18 V < VCC
1 µF
CL
Temperature Sensor
An on-chip temperature sensor monitors the device temperature and signals a fault condition if the internal
temperature reaches 150°C. If the internal temperature exceeds this trip point, the HOT output switches to an
active low state. If the internal temperature continues to rise, passing a second trip point at 170°C, all device
outputs are put in a high-impedance state.
A special condition occurs, however, when the chip temperature exceeds the second temperature trip point due
to an output short. Then the output buffer becomes 3-state, thus separating the buffer from the external circuitry.
An internal 100-kΩ pull-down resistor, connecting the HOT pin to ground, is used as a cooling down resistor,
which continues to provide a logic low level to the external circuitry.
Parity Generator
A
•
•
•
parity bit is generated when one or more of the following conditions occur:
a change in input status
a change in Undervoltage status
a change in Overtemperature status
Upon the application of a load pulse the input status (IP0–IP7) and the diagnostic bits (HOT, UVO, and PAR) are
loaded parallel into the serializer assuming the following format:
Bit 11
PAR
Bit 1
UVO
HOT
PIP0
PIP1
PIP2
PIP3
PIP4
PIP5
PIP6
PIP7
Figure 16. Sequence of Status Bits in Serializer
12
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SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642 – MARCH 2009
APPLICATION INFORMATION
System-Level EMC
The SN65HVS881 is designed to operate reliably in harsh industrial environments. At a system level, the device
is tested according to several international electromagnetic compatibility (EMC) standards. In addition to the
device internal ESD structures, external protection circuitry, as shown in Figure 17, can be used to absorb as
much energy from burst- and surge-transients as possible.
R1
VSUP = 24V
V24
CS
R1
56 W, 1/3 W MELF Resistor
D1
33 V – 36 V fast Zener Diode, Z2SMB36
C1
10 µF, 60 V Ceramic Capacitor
RIN
1.2 kW, 1/4 W MELF Resistor
CIN
22 nF, 60 V Ceramic Capacitor
CS
4.7 nF, 2 kV Polypropylene Capacitor
DS
39V Transient Voltage Suppressor: SM15T39CA
D2
Super Rectifier: BYM10-1000, or
General Purpose rectifier: 1N4007
D1
DS
C1
SN65HVS881
FE
0V
FGND
R IN
IPx
IP0 – IP7
CIN
0V
FGND
D2
CS
FE
Figure 17. Typical EMC Protection Circuitry for Supply and Signal Inputs
Input Channel Switching for IEC61131-2 PLC Applications
The input stage of the SN65HVS881 is designed so that with a 24-V supply on VCC and an input resistor RIN =
1.2 kΩ, the trip point for signaling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching
requirements of IEC61131-2 type-1 and type-3 switches.
Type 2
Type 1
30
25
25
30
25
VIN / V
VIN / V
ON
20
15
15
10
10
5
5
0
-3
OFF
5
10
IIN / mA
ON
20
20
ON
15
10
5
OFF
0
-3
15
VIN / V
30
Type 3
5
10
15
IIN / mA
0
-3
20
25
30
OFF
5
10
IIN / mA
15
Figure 18. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a type-2 switch application two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (GND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
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SN65HVS881
SLAS642 – MARCH 2009................................................................................................................................................................................................... www.ti.com
RIN
R IN
IP 0
C IN
IP0
C IN
RE 0
R IN
RE0
R IN
IP 1
C IN
IP1
C IN
RE1
RE1
Figure 19. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
Digital Interface Timing
The digital interface of the SN65HVS881 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard microcontrollers.
SN65HVS881
SIP
IP7
SERIALIZER
IP0
HOST
CONTROLLER
ISO7241
LD
OUTA
INA
CE
OUTB
INB
CLK
OUTC
INC
SOP
IND
OUTD
LOAD
STE
SCLK
SOMI
Figure 20. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, /LD, the information of the field inputs and the diagnostic bits are latched into
the shift register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A
low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial
output, SOP. Data is clocked at the rising edge of CLK. Thus after eleven consecutive clock cycles all data have
been clocked out of the shift register and the information of the serial input, SIP, appears at the serial output,
SOP.
14
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SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642 – MARCH 2009
CLK
CE
SIP
high
LD
PAR - PIP 6
PIP 7
SOP don’t care
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
HOT
UVO
PAR
SIP
Serial shift
inhibit
Figure 21. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Cascading for High Channel Count Input Modules
Designing high-channel count modules requires cascading multiple SN65HVS881 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
HOST
CONTROLLER
ISO7241
4 x SN65HVS881
OUTA
INA
OUTB
INB
OUTC
INC
SCLK
SOMI
SOP
/CE
CLK
/LD
IP7
SIP
SOP
/CE
OUTD
STE
SERIALIZER
IP0
IP7
SERIALIZER
IP0
IP7
CLK
/LD
SIP
CLK
SOP
/LD
SERIALIZER
IP0
IP7
IP0
SERIALIZER
/CE
SIP
CLK
SOP
/LD
/CE
SIP
IND
LOAD
Figure 22. Cascading Four SN65HVS881 for a 32-Channel Input Module
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15
SN65HVS881
SLAS642 – MARCH 2009................................................................................................................................................................................................... www.ti.com
Typical Digital Input Module Application
SM15T39CA
24 V
(Logic) 24V1
5V
5 V-ISO
SM15T39A
(Sensors) 24V2
Isolated
DC / DC
4.7 nF
2 kV
4.7 nF
2 kV
GND2
0V
Power
Supply
GND1
0 V-ISO
4.7 nF
2 kV
56 W MELF
FE
Z2SMB36
10 mF
60 V
Screw Terminals
1N4007
1 mF
0.1 mF
SN65 HVS 881
1.2 kW
MELF
22 nF
S0
V24
5VOP
IP0
CHOK
RE0
1.2 kW
MELF
S7
VCC1
HOST
CONTROLLER
EN2
EN1
VCC
LD
OUTA
INA
LOAD
CLK
OUTB
INB
SCLK
SIP
CE
INC
OUTC
INT
RE7
SOP
IND
OUTD
SOMI
RLIM
DB0
GND2
GND1
DGND
FGND
DB1
IP7
22 nF
ISO7242
VCC2
24.9 kW
Figure 23. Typical Digital Input Module Application
16
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PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVS881PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVS881PWPR
HTSSOP
PWP
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
SN65HVS881PWP
PWP
HTSSOP
28
50
530
10.2
3600
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
TM
PWP 28
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.65 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
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