SN65HVS885PWPR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 SN65HVS885 34-V Digital-Input Serializer for 5-V Systems • • • • • Eight Digital Sensor Inputs – High Input Voltage up to 34 V – Selectable Debounce Filters From 0 ms to 3 ms – Flexible Input Current-Limited – 0.2 mA to 5.2 mA – Field Inputs Protected to 15-kV ESD Single 5-V Supply Output Drivers for External Status LEDs Cascadable for More Inputs in Multiples of Eight SPI-Compatible Interface Overtemperature Indicator 2 Applications • • • • Industrial PCs Digital I/O Cards High Channel Count Digital Input Modules Decentralized I/O Modules Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial input of the following device, enabling the design of high-channel count input modules. Multiple devices can be cascaded through a single serial port, reducing both the isolation channels and controller inputs required. Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a single, external, precision resistor. An onchip temperature sensor provides diagnostic information for graceful shutdown and system safety. The SN65HVS885 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The device is specified for operation at temperatures from –40°C to 125°C. Device Information(1) PART NUMBER PACKAGE SN65HVS885 3 Description The SN65HVS885 is an eight channel, digital-input serializer for high-channel density digital input modules in industrial and building automation. Operating from a 5-V supply the device accepts field input voltages of up to 34 V. In combination with galvanic isolators the device completes the interface between the high voltage signals on the field-side and the low-voltage signals on the controller side. Inputs signals are current limited and then validated by internal debounce filters. With the addition of few external components, the input switching characteristic can be configured in accordance with IEC61131-2 for Type 1, 2 and 3 sensor switches. HTSSOP (28) BODY SIZE (NOM) 9.70 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified I/O Structure Debounce Select DB 0:1 Field Inputs IP 0:7 2 8 GND LED Outputs RE 0:7 IREF Adjust: RLIM 8 Serial Input 3 8 SERIALIZER • 1 Upon the application of load and clock signals, input data is latched in parallel into the shift register and afterwards clocked out serially. Signal Conditioning 1 Features Control Inp[uts LD, CE, CLK VCC Serial Output 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 7.1 Waveforms ................................................................ 8 7.2 Signal Conventions ................................................... 8 8 Detailed Description .............................................. 9 8.1 8.2 8.3 8.4 9 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................. 10 Device Functional Modes........................................ 12 Application and Implementation ........................ 13 9.1 Application Information............................................ 13 9.2 Typical Application ................................................. 16 10 Power Supply Recommendations ..................... 19 11 Layout................................................................... 19 11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (January 2009) to Revision A • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP With Exposed Thermal Pad Top View DB0 DB1 IP0 RE0 IP1 RE1 IP2 RE2 IP3 RE3 IP4 RE4 RLIM NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND SIP LD CLK CE SOP IP7 RE7 IP6 RE6 IP5 RE5 HOT VCC Pin Functions PIN NAME DESCRIPTION NO. CE 24 Clock Enable Input CLK 25 Serial Clock Input DB0 1 DB1 2 GND 28 Device Ground 16 Over-Temperature Flag HOT Debounce select inputs IPx 3, 5, 7, 9, 11, 18, 20, 22 Input Channel x LD 26 Load Pulse Input NC 14 Not Connected REx 4, 6, 8, 10, 12, 17, 19, 21 Return Path x (LED drive) RLIM 13 Current Limiting Resistor SIP 27 Serial Data Input SOP 23 Serial Data Output VCC 15 5 V Device Supply Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 3 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Device power input VCC –0.5 6 V VIPx Field digital inputs IPx –0.3 36 V VID Voltage at any logic input DB0, DB1, CLK, SIP, CE, LD –0.5 6 V IO Output current HOT, SOP –8 8 mA PTOT Continuous total power dissipation TJ Junction temperature 170 °C Tstg Storage temperature 150 °C (1) See Thermal Information Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1) All pins ±4000 IPx ±15000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 Machine model (MM) (3) ±100 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. JEDEC Standard 22, Method A115-A 6.3 Recommended Operating Conditions MIN NOM MAX 4.5 5 5.5 V 4 V 5.5 34 V 0 0.8 V Logic high-state input voltage 2.0 5.5 V Current limiter resistor 17 VCC Device supply voltage VIPL Field input low-state input voltage VIPH Field input high-state input voltage VIL Logic low-state input voltage VIH RLIM fIP (1) Input data rate TA Device TJ Junction Temperature (1) 0 25 500 UNIT kΩ 0 1 Mbps –40 125 °C 150 °C Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω 6.4 Thermal Information SN65HVS88 5 THERMAL METRIC (1) PWP (HTSSOP) UNIT 28 PINS RθJA Junction-to-ambient thermal resistance High-K thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 35 °C/W 4.27 °C/W RθJB Junction-to-board thermal resistance 15 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 15.9 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 Thermal Information (continued) SN65HVS88 5 THERMAL METRIC (1) PWP (HTSSOP) UNIT 28 PINS RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 °C/W 6.5 Electrical Characteristics over full-range of recommended operating conditions (unless otherwise noted) all voltages measured against device ground, see Figure 9 PARAMETER TERMINAL TEST CONDITIONS MIN TYP MAX UNIT FIELD INPUTS VTH–(IP) Low-level device input threshold voltage VTH+(IP) High-level device input threshold voltage 4 IP0–IP7 RLIM = 25 kΩ 5.2 VHYS(IP) Device input hysteresis VTH–(IN) VTH+(IN) Low-level field input threshold voltage High-level field input threshold voltage 6 Measured at field side of RIN 4.5 V < VCC < 5.5 V, RIN = 1.2 kΩ ± 5%, RLIM = 25 kΩ, TA ≤ 125°C V 5.5 V 8.4 V 10 1 RIP Input resistance IP0–IP7 3 V < VIPx < 6 V, RLIM = 25 kΩ IIP-LIM Input current limit IP0–IP7 RLIM = 25 kΩ tDB Debounce times of input channels IP0–IP7 RE on-state current RE0–RE7 V V 0.2 0.63 1.1 kΩ 3.15 3.6 4 mA DB0 = open, DB1 = GND 0 DB0 = GND, DB1 = open 1 DB0 = DB1 = open 3 RLIM = 25 kΩ, REX = GND V 0.9 9.4 VHYS(IN) Field input hysteresis IRE-on 4.3 2.8 ms 3.15 3.5 mA 6.5 10 mA 0.4 V DEVICE SUPPLY ICC(VCC) Supply current VCC IP0 to IP7 = 24V, REX = GND, All logic inputs open LOGIC INPUTS AND OUTPUTS IOL = 20 μA VOL Logic low-level output voltage VOH Logic high-level output voltage IIL Logic input leakage current TOVER Over-temperature indication 150 °C TSHDN Shutdown temperature 170 °C 1100 mW SOP, HOT IOH = –20 μA 4 DB0, DB1, SIP, LD, CE, CLK V –50 50 μA POWER DISSIPATION PD Power Dissipation VCC = 5 V, RIN = 0Ω, RLIM = 25 kΩ, RE0 – RE7 = GND, fCLK = 100 MHz IP0-IP7 = 34 V IP0-IP7 = 24 V IP0-IP7 = 20 V IP0-IP7 = 12 V 6.6 Timing Requirements over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT tW1 CLK pulse width See Figure 6 4 ns tW2 LD pulse width See Figure 4 6 ns Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 5 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com Timing Requirements (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT tSU1 SIP to CLK setup time See Figure 7 4 ns tH1 SIP to CLK hold time See Figure 7 2 ns tSU2 Falling edge to rising edge (CE to CLK) setup time See Figure 8 4 ns tREC LD to CLK recovery time See Figure 5 2 fCLK Clock pulse frequency See Figure 6 DC ns 100 MHz 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1, tPHL1 CLK to SOP CL = 15 pF, see Figure 6 10 ns tPLH2, tPHL2 LD to SOP CL = 15 pF, see Figure 4 14 ns tr, tf Rise and fall times CL = 15 pF, see Figure 6 6 ns 6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 6.8 Typical Characteristics 30 RIN = 1.2 kW 25 VIN / V 20 a) IIP-LIM = 2.5mA (RLIM = 36.1 kW) c) b) a) b) IIP-LIM = 3.0mA (RLIM = 30.1 kW) c) IIP-LIM = 3.6mA (RLIM = 24.9 kW) 15 10 Off On 5 Field Input Thresholds 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I IN / mA Figure 1. Typical Input Characteristics 9.6 VCC = 5 V, 101.5 VIN = 24 V, RIN = 1.2 kW, 101.0 RLIM = 24.9 kW 100.5 9.4 VTH+(IN) 9.2 VIN – V IIP–LIM/IIP–LIM –25°C - % 102.0 100.0 9.0 8.8 VCC = 5 V, RIN = 1.2 kW, RLIM = 24.9 kW 99.5 8.6 99.0 8.4 98.5 8.2 98.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 TA - Ambient Temperature - °C 8.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 TA - Ambient Temperature - °C VTH–(IN) Figure 2. Typical Current Limiter Variation vs Ambient Temperature Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 7 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com 7 Parameter Measurement Information 7.1 Waveforms For the complete serial interface timing, refer to Figure 17. tW2 LD LD tREC tLPH2 tPLH2 CLK SOP Figure 4. Parallel – Load Mode Figure 5. Serial – Shift Mode 1/fCLK valid tW1 SIP CLK tPLH1 tSU1 tPHL1 tH1 CLK SOP tr tf Figure 6. Serial – Shift Mode Figure 7. Serial – Shift Mode CLK tSU2 CLK inhibited CE Figure 8. Serial – Shift Mode 7.2 Signal Conventions R IN IPx IIN VTH(IN) VTH(IP) SN65HVS885 GND Figure 9. On/Off Threshold Voltage Measurements 8 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 8 Detailed Description 8.1 Overview The SN65HVS885 is an 8 channel, digital input serializer which operates from a 5 V supply and accepts digital inputs of up to 34 V on the 8 channels (IP0-IP7). The device provides a serially shifted digital output with reduced voltage ranges of 0-5 V for applications in industrial and building automation systems. The SN65HVS885 meets JEDEC standards for ESD protection (refer to ESD Ratings), and is SPI compatible for interfacing with standard microcontrollers. The serializer operates in 2 fundamental modes: Load Mode and Shift mode. In Load mode, information from the field inputs is allowed to latch into the shift register. In Shift mode, the information stored in the parallel shift register can be serially shifted to the serial output (SOP). A detailed description of the functional modes is available in the Device Functional Modes section. 8.2 Functional Block Diagram Vcc HOT RLIM Adj. Current Thresholds RE0 IP0 Current Sense Thermal Protection SIP Debounce Filter Channel 0 GND RE7 IP7 SERIALIZER & Voltage Sense DB0 DB1 Debounce Select LD CE CLK Channel 7 SOP Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 9 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com 8.3 Feature Description 8.3.1 Digital Inputs 1.25 VREF 5V ILIM Mirror n = 72 IIN IPx ILIM Limiter IINmax = ILIM IREF RLIM Figure 10. Digital Input Stage Each digital input operates as a controlled current sink limiting the input current to a maximum value of ILIM. The current limit is derived from the reference current via ILIM = n × IREF, and IREF is determined by IREF = VREF/RLIM. Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/ILIM. Inserting the actual values for n and VREF gives: RLIM = 90 V / ILIM. While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ), it is easy to lower the current limit to further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate: 90 V 90 V RLIM = = = 36 kΩ ILIM 2.5 mA (1) 8.3.2 Debounce Filter The HVS885 applies a simple analog/digital filtering technique to remove unintended signal transitions due to contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration of the selected debounce time to be latched into the shift register as a valid state. The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the different debounce times listed in the following truth table. Table 1. Debounce Times 10 DB1 DB0 FUNCTION Open Open 3 ms delay Open GND 1 ms delay GND Open 0 ms delay (Filter bypassed) GND GND Reserved Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 5V IPx REF REx RLIM GND Figure 11. Equivalent Input Diagram 8.3.3 Shift Register The conversion from parallel input to serial output data is performed by an eight-channel, parallel-in serial-out shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7, that are enabled by a low level at the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register also provides a clock-enable function. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock enable (CE) input is held low. Parallel loading is inhibited when LD is held high. The parallel inputs to the register are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs. SIP D CLK Logic Q D CP CE R Q D CP S R Q CP S R D Q D CP S R Q CP S D Q CP R S R D Q CP S R D Q SOP CP S R S LD PIP 0 PIP 1 PIP 2 PIP 3 PIP 4 PIP 5 PIP 6 PIP 7 Figure 12. Shift Register Logic Structure Table 2. Function Table INPUTS (1) FUNCTION LD CLK CE L X X Parallel load H X H No change H ↑ L Shift (1) Shift = content of each internal register shifts towards serial outputs. Data at SIP is shifted into first register. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 11 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com 8.3.4 Temperature Sensor An on-chip temperature sensor monitors the device temperature and signals a fault condition if the temperature exceeds a first trip point at 150°C by pulling the HOT output low. If the junction temperature continues to rise, passing a second trip point at 170 °C, all device outputs assume high impedance state. A special condition occurs when the chip temperature exceeds the second temperature trip point due to an output short; the HOT output buffer becomes high impedance, thus separating the buffer from the external circuitry. An internal 100-kΩ pulldown resistor, connecting the HOT-pin to ground, is used as a "cooling down" resistor, which continues to provide a logic low level to the external circuitry. 8.4 Device Functional Modes The 2 functional modes of operation are Load mode and Shift mode. Load mode enables information from the field inputs to latch into the shift register. To enter load mode, the LD pin must be held low, and the device will remain in load mode regardless of the CLK, CE, or serial (SIP) input levels. A high level at the LD pin switches the device into Shift mode. When the device is in Shift mode, a low level at the CE pin will cause the data stored in the parallel shift register to be serially shifted to the serial output (SOP) on the rising edge of CLK. A high level at the CE pin inhibits the serial shifting, which is demonstrated in Figure 17. After 8 consecutive CLK pulses, the serial output (SOP) will remain at the level of the serial input (SIP) which is internally pulled to logic high. A logic high at the CE pin is required to signify the end of the serial data output. In the case of a daisy chained configuration, the serial output (SOP) of the SN65HVS885 can be connected to the serial input (SIP) of a following device, and additional clock pulses are required to shift the additional data out of the chain. The number of consecutive clock pulses will equal 8 times the number of devices in the chain. See Figure 18 for an example of a cascaded chain of 4x SN65HVS885. 12 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 System-Level EMC The SN65HVS885 is designed to operate reliably in harsh industrial environments. At a system level, the device is tested according to several international electromagnetic compatibility (EMC) standards. In addition to the device internal ESD structures, external protection circuitry shown in Figure 13, can be used to absorb as much energy from burst- and surge-transients as possible. R IN INx RIN 1.2 kW, 1/4 W MELF Resistor CIN 220 nF, 60 V Ceramic Capacitor CS 4.7 nF, 2 kV Ceramic Capacitor IP0 – IP7 V CC 5V 1mF C IN SN65HVS885 0V GND CS FE Figure 13. Typical EMC Protection Circuitry for Supply and Signal Inputs 9.1.2 Input Channel Switching Characteristics The input stage of the HVS885 is so designed, that for an input resistor RIN = 1.2 kΩ the trip point for signaling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching requirements of IEC61131-2 Type 1 and Type 3 switches. Type 2 Type 3 30 30 30 25 25 25 15 10 5 ON 20 VIN (V) ON 20 VIN (V) VIN (V) Type 1 15 10 5 OFF 0 –30 5 10 IIN (mA) 10 5 OFF 0 –3 15 ON 20 15 0 5 10 15 OFF 0 –3 20 25 IIN (mA) 30 0 5 10 IIN (mA) 15 Figure 14. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches For a Type 2 switch application, two inputs are connected in parallel. The current limiters then add to a total maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator LED, the RE-pin of the other input channel should be connected to ground (GND). Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 13 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com Application Information (continued) Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by two shift register bits. RIN RIN IN0 IN0 IP0 IP0 CIN CIN RE0 RE0 RIN RIN IN1 IP1 IP1 CIN CIN RE1 RE1 Figure 15. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input 9.1.3 Digital Interface Timing The digital interface of the SN65HVS885 is SPI compatible and interfaces, isolated or non-isolated, to a wide variety of standard micro controllers. SN65HVS885 SIP IP7 SERIALIZER IP0 HOST CONTROLLER ISO7241 LD OUTA INA CE OUTB INB CLK OUTC INC SOP IND OUTD LOAD STE SCLK SOMI Figure 16. Simple Isolation of the Shift Register Interface Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift register. Taking /LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data is clocked at the rising edge of CLK. Thus after eight consecutive clock cycles all field input data have been clocked out of the shift register and the information of the serial input, SIP, appears at the serial output, SOP. 14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 Application Information (continued) CLK CE SIP high LD PIP0–PIP6 PIP7 IP 6 IP7 SOP don’t care IP 5 IP4 inhibit IP3 IP2 IP1 IP 0 SIP Serial shift Figure 17. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register 9.1.4 Cascading for High Channel Count Input Modules Designing high-channel count modules require cascading multiple SN65HVS885 devices. Simply connect the serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the processor interface. HOST CONTROLLER ISO7241 4 x SN65HVS885 OUTA INA OUTB INB OUTC INC SCLK SOMI SOP CE OUTD STE IP7 SERIALIZER IP0 IP7 IP0 SERIALIZER CLK LD SIP SOP CE CLK LD SIP CE SOP IP7 SERIALIZER IP0 IP7 IP0 SERIALIZER CLK LD SIP SOP CE CLK LD SIP IND LOAD Figure 18. Cascading Four SN65HVS885 for a 32-Channel Input Module Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 15 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com 9.2 Typical Application Isolated DC-DC SM15T39A 24V 5VO 3VIN 3V-ISO 0VO 0VIN 0V-ISO 4.7nF 2kV Power 0V Supply 4.7nF 2kV FE SN65HVS885 1.2k MELF NC VCC IP0 HOT RE0 SIP 0.1 mF ISO7242 VCC2 VCC1 HOST CONTROLLER 22nF S0 1.2k MELF EN2 EN1 VCC LD OUTA INA LOAD CLK OUTB INB SCLK CE INC OUTC INT RE7 SOP IND OUTD SOMI RLIM DB0 GND2 GND1 DGND GND DB1 IP7 22nF S7 24.9k Figure 19. Typical Digital Input Module Application 9.2.1 Design Requirements The simplified schematic in Figure 19 demonstrates a typical application of the SN65HVS885 for sensing the state of digital switches with 24-V high logic levels. In this application, a 3.3-V host controller must receive the state of 8 switches as a serial input, while remaining isolated from the high voltage power supply. 9.2.2 Detailed Design Procedure 9.2.2.1 Input Stage Selection of the current limiting resistor RLIM sets the input current limit ILIM for the device. Digital Inputs includes necessary equations for choosing the limiting resistor. The On/Off voltage thresholds at the device pin VTH(IP+) and VTH(IP-) are fixed to 5.2 V and 4.3 V respectively, however the On/Off voltage thresholds of the field input VTH(IN+) and VTH(IN-) are determined by the value of the series resistor RIN placed between the field input and the device. The threshold voltage VTH(IN+) is determined with the following equation: VTH(IN + ) = I IN ´ R IN + VTH(IP + ) (2) Substituting Equation 1 from section 8.3.1, and solving for RIN produces an equation for RIN given a desired onthreshold. R IN = (VTH(IN + ) - 5.2V) ´ R LIM 90V (3) The following equation can be used to calculate the off-threshold voltage given a value for RIN VTH(IN - ) = 90V ´ R IN + VTH(IP - ) R LIM (4) Figure 20 contains an example input characteristic: 16 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 Typical Application (continued) 30 25 VIN (V) 20 15 10 ON = 8. 2 V OFF = 7.3V 5 0 0 0.5 1 1.5 2 2.5 3 I IN (mA) Figure 20. SN65HVS885 Example Input Characteristic 9.2.2.2 Setting Debounce Time The logic signals at the DB0 and DB1 pins determine the denounce times for the device according to the table in section 6.5. The DB0 and DB1 pins are internally pulled high. Connecting the pins to GND in different configurations allows for selection of 0, 1, or 3ms debounce times. In noisy environments, it is recommended that unused DB pins should be connected externally to a 5 V supply. 9.2.2.3 Using the HOT Indicator The HOT pin can be used as a visual health indicator for the device. To use the HOT pin as a health indicator, a green LED can be connected (with a series resistor) between the HOT pin and ground. If the device exceeds recommended operating temperature, the LED will turn off. Alternatively, the HOT pin can be connected to the MCU to trigger an interrupt if temperature limits are exceeded. 9.2.2.4 Example: High-Voltage Sensing Application For the high-voltage sensing application in Figure 19, inputs from each switch (S0-S7) are connected to the 8 parallel inputs (IP0-IP7) of the SN65HVS885 through 1.2kΩ MELF resistors. Small capacitors (22nF) are tied to ground at each input to provide noise protection for the signals. A resistor is added between the RLIM pin and GND to provide a device current limit according to the equation ILIM = 90 V / RLIM. In this example, with a 24.9kΩ resistor, the current limit for the device is set to 3.6mA. LEDs are placed between pins RE0-RE7 to allow for external status observation of the parallel inputs. Finally the SN65HVS885 is connected through a digital isolation device to the host controller to provide galvanic isolation to the external interfaces and to allow for communication between the 5 V SN65HVS885 logic and the 3.3-V host controller. The host controller manages mode switching and clocking of the SN65HVS885 through the digital isolation device. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 17 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com Typical Application (continued) 9.2.3 Application Curve The application traces acquired in Figure 21 demonstrate typical behavior for the SN65HVD885. The trace names in descending order are: Clock Signal (CE), Clock Enable Input (CE), Load Pulse Input (LD), and Serial Data Output (SOP). Figure 21. SN65HVD885 Application Measurements 18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 SN65HVS885 www.ti.com SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 10 Power Supply Recommendations The SN65HVD885 operates within a recommended supply voltage range from 4.5 V to 5.5 V. A 0.1 µF or larger capacitor should be placed between VCC and ground to improve power supply noise immunity. A current limiting resistor can be used to reduce overall power consumption as described in Digital Inputs. The high voltage parallel field inputs can accept voltages ranging from 0 V to 34 V, however all other inputs must remain between 0 V to 5 V. Refer to the Recommended Operating Conditions table for more detailed voltage suggestions. High voltage field inputs should be buffered as shown in Figure 19 to improve input noise immunity. 11 Layout 11.1 Layout Guidelines 1. Place series MELF resistors between the field inputs and the device input pins. 2. Place small ~22 nF capacitors close to the field input pins to reduce noise. 3. Place a supply buffering 0.1-µF capacitor around as close to the VCC pin as possible. 11.2 Layout Example High Voltage Parallel Inputs 1 2 R C R C R C R C R C R C R C R C Isolator R MCU SN65HVD885 3 C Isolated DC-DC Via to ground Via to VCC 5V Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 19 SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65HVS885PWP ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HVS885 SN65HVS885PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HVS885 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of