SN65LVPE501RGER

SN65LVPE501 www.ti.com SLLSE30A – MAY 2010 – REVISED MAY 2012 Dual Channel x1 PCIe Redriver/Equalizer Check for Samples: SN65LVPE501 FEATURES 1 • • • • • • • • Single Lane PCIe Equalizer/Redriver Support for Both PCIe Gen I (2.5Gbps) and Gen II (5.0 Gbps) Speed Selectable Equalization, De-emphasis and Output Swing Control Integrated Termination Hot-Plug Capable Receiver Detect Low Power: – 330mW(TYP), VCC = 3.3V Auto Low Power Modes: – 5mW (TYP) When no Connection Detected – 70mW (TYP) When in Auto-Low Power Mode • • • Excellent Jitter and Loss Compensation Capability: – 30" of 6 mil Stripline on FR4 Small Foot Print – 24 Pin 4 × 4 QFN Package High Protection Against ESD Transient – HBM: 3,000 V – CDM: 1,500 V – MM: 200 V APPLICATIONS • PC MB, Docking Stations, Backplane and Cabled Application DESCRIPTION The SN65LVPE501 is a dual channel, single lane PCIe redriver and signal conditioner supporting data rates of up to 5.0Gbps. The device complies with PCIe spec revision 2.1. Programmable EQ, De-Emphasis and Amplitude Swing The SN65LVPE501 is designed to minimize the signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion PCIe signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. Both equalization and deemphasis levels are controlled by the setting of signal control pins EQ1, EQ2 and DE1, DE2. To provide additional control of signal integrity in extended backplane applications LVPE501 provides independent output amplitude control for each channel. See Table 2 for setting details. Device PowerOn Device initiates internal power-on reset after VCC has stabilized. External reset can also be applied at anytime by toggling RST pin. External reset is recommended after every device power-up. When RST is driven high, the device samples the state of EN_RXD, if it is set H device enters Rx.Detect state where each channel will perform Rx.Detect function (as described in PCIe spec). If EN_RXD is set L, automatic RX detect function is disabled and both channels are enabled with their termination set to ZDC_RX. Receiver Detection While EN_RXD pin is H and device is not in sleep mode (RST is H), SN65LVPE501 performs RX.Detect on both channels indefinitely until remote termination is detected on both channels. Automatic Rx detection feature can be forced off by driving EN_RXD low. In this state both channels input termination are set to ZDC_RX. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated SN65LVPE501 SLLSE30A – MAY 2010 – REVISED MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED Sleep (Shut_Down) Mode This is low power state triggered by RST = L. In sleep mode receiver termination resistor for each of the two channels is switched to ZRX-HIGH_IMP of >50 KΩ and transmitters are pulled to Hi-Z state. Device power is reduced to 1µs (TYP), the associated CH will enter auto low power (ALP) mode where power/CH will be reduced to