SN65LVPE502RGER

SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Dual Channel USB3.0 Redriver/Equalizer Check for Samples: SN65LVPE502 FEATURES 1 • • • • • • • Single Lane USB 3.0 Equalizer/Redriver Selectable Equalization, De-emphasis and Output Swing Control Integrated Termination Hot-Plug Capable Receiver Detect Low Power: – 315mW(TYP), VCC = 3.3V Auto Low Power Modes: – 5mW (TYP) When no Connection Detected – 70mW (TYP) When in U2/U3 Mode • • • Excellent Jitter and Loss Compensation Capability: to 24" – 24" of 6 mil Stripline on FR4 – 12" on Input and 4m, 26AWG USB 3.0 Cable on Output Small foot print – 24 Pin (4mm × 4mm) QFN Package High Protection Against ESD Transient – HBM: 5,000 V – CDM: 1,500 V – MM: 200 V APPLICATIONS • Notebooks, Desktops, Docking Stations, Backplane and Cabled Application DESCRIPTION The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes. Programmable EQ, De-Emphasis and Amplitude Swing The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in Table 2. Low Power Modes The device supports three low power modes as described below. 1. Sleep Mode Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max. 2. RX Detect Mode – When no remote device is connected Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is 200kΩ pull-up/pull-down. When pins are left as NC board leakage at this pin pad must be < 1 µA otherwise drive to VCC/2 to assert mid-level state. Table 2. Signal Control Pin Setting OSx (1) TRANSITION BIT AMPLITUDE (TYP mVpp) NC (default) 1000 0 870 1 1085 EQx (1) EQUALIZATION dB NC (default) 0 0 7 1 DEx (1) (1) 15 OSx (1) = NC OSx (1) =0 OSx (1) = 1 NC –3.5 dB –2.2 dB –4.4 dB 0 –6.0 dB –5.2 dB –6.0 dB 1 –8.5 dB –8.9 dB –7.6 dB EN_RXD DEVICE FUNCTION 1 (default) Normal operating mode 0 Sleep mode CM DEVICE FUNCTION 0 (default) Normal Mode 1 Compliance mode Applies to Channel 1 and Channel 2 at 2.5 GHz. USB Device USB Host Device PCB 8"-20" 2"-6" Up to 3m (30AWG) 1"-6" Figure 4. Redriver Placement Example Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 5 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PCAKAGE SN65LVPE502RGER LVPE502 24-pin RGE Reel (large) SN65LVPE502RGET LVPE502 24-pin RGE Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNITS / VALUES Supply Voltage Range (2) –0.5 V to 4 V VCC –0.5 V to 4 V Differential I/O Voltage Range –0.5 V to VCC + 0.5V Control I/O Human Body Model (3) Electrostatic discharge Charged Device Model ±5000V (4) ±1500V Machine Model (5) ±200V Continuous power dissipation (1) (2) (3) (4) (5) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. PACKAGE CHARACTERIZATION over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Device power dissipation CM, EN_RXD, EQ cntrl pins = NC, K28.5 pattern at 5 Gbps, VID = 1000 mVpp 330 450 mW PSD Device power dissipation under low power mode EN_RXD= GND 0.3 1 mW THERMAL INFORMATION SN65LVPE502 THERMAL METRIC (1) RGE UNITS 24 PINS θJA Junction-to-ambient thermal resistance 46 θJC(TOP) Junction-to-case(top) thermal resistance 42 θJB Junction-to-board thermal resistance 13 ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 9 θJC(BOTTOM) Junction-to-case(bottom) thermal resistance 4 (1) 6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC Supply Voltage CCOUPLING AC Coupling Capacitor Operating free-air temperature MIN TYP 3 3.3 MAX UNIT 3.6 V 75 200 nF 0 85 °C DEVICE POWER The SN65LVPE502 is designed to operate from a single 3.3 V supply. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 100 120 2 5 UNIT DEVICE PARAMETERS EN_RXD, CM, EQ cntrl = NC, K28.5 pattern at 5 Gbps, VID = 1000 mVpp ICC ICCRx.Detect In Rx.Detect mode Supply Current ICCsleep EN_RXD = GND ICCU2-U3 mA 0.1 Link in USB low power state 21 Maximum Data Rate 5 tENB Device Enable Time Sleep mode exit time EN_RXD L→ H With Rx termination present tDIS Device Disable Time Sleep mode entry time EN_RXD H→ L TRX.DETECT Rx.Detect Start Event Power-up time Gbps 100 µs 2 µs 100 µs CONTROL LOGIC (under recommended operating conditions) VIH High level Input Voltage 1.4 VCC V VIL Low Level Input Voltage –0.3 0.5 V VHYS Input Hysteresis 150 OSx, EQx, DEx = VCC IIH High Level Input Current EN_RXD = VCC 1 CM = VCC IIL Low Level Input Current mV 30 µA 30 OSx, EQx, DEx = GND –30 EN_RXD = GND –30 µA –1 CM = GND RECEIVER AC/DC AC coupled differential RX peak to peak signal Vindiff_pp RX1, RX2 Input Voltage Swing VCM_RX RX1, RX2 Common Mode Voltage VinCOM_P RX1, RX2 AC Peak common mode voltage ZDC_RX DC common mode impedance Zdiff_RX DC differential input impedance 100 1200 3.3 Measured at Rx pins with termination enabled Device in sleep mode Rx termination not powered. Measured with respect to GND over 500mV max ZRX_High_IMP+ DC Input High Impedance VRX-LFPS-DETpp Measured at receiver pin, below minimum Low Voltage Periodic Signaling (LFPS) output is squelched, above max input signal Detect Threshold is passed to output RLRX-DIFF Differential Return Loss RLRX-CM Common Mode Return Loss V 150 mVP 18 26 30 Ω 72 80 120 Ω 50 85 100 kΩ 300 50 MHz – 1.25 GHz 10 11 1.25 GHz – 2.5 GHz 6 7 11 13 50 MHz – 2.5 GHz Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 mVpp mVpp dB dB 7 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX RL =100Ω +1%, DEx, OSx = NC, Transition Bit 800 1000 1200 UNIT TRANSMITTER AC/DC VTXDIFF_TB_PP Differential peak-to-peak Output Voltage (VID = 800, 1200 mVpp, 5Gbps) VTXDIFF_NTB_PP RL =100Ω +1%, DEx, OSx = GND Transition Bit 870 RL =100Ω +1%, DEx, OSx = VCC Transition Bit 1085 RL =100Ω +1%, DEx=NC, OSx = 0,1,NC Non-Transition Bit 665 RL =100Ω +1%, DEx=0, OSx = 0,1,NC Non-Transition Bit 510 RL =100Ω +1%, DEx=1 OSx = 0,1,NC Non-Transition Bit 375 mV –3.0 OS1,2 = NC (for OS1,2 = 1 and 0 see Table 2) De-Emphasis Level –3.5 –4.0 –6.0 dB –8.5 TDE De-Emphasis Width Zdiff_TX DC Differential Impedance 0.85 ZCM_TX DC Common Mode Impedance Measured w.r.t to AC ground over 0-500mV 90 120 Ω 30 Ω 18 23 f = 50 MHz – 1.25 GHz 9 10 f = 1.25 GHz – 2.5 GHz 6 7 11 12 RLdiff_TX Differential Return Loss RLCM_TX Common Mode Return Loss f = 50 MHz – 2.5 GHz ITX_SC TX short circuit current TX± shorted to GND VTX_CM_DC Transmitter DC common-mode voltage VTX_CM_AC_Active TX AC common mode voltage active VTX_idle_diff-AC-pp Electrical idle differential peak to peak output voltage VTX_CM_DeltaU1-U0 Absolute delta of DC CM voltage during active and idle states VTX_idle_diff-DC DC Electrical idle differential output voltage Voltage must be low pass filtered to remove any AC component Vdetect Voltage change to allow receiver detect Positive voltage to sense receiver termination tR,tF Output Rise/Fall time tRF_MM Output Rise/Fall time mismatch 20%-80% of differential voltage measure 1" from the output pin Tdiff_LH, Tdiff_HL Differential Propagation Delay De-Emphasis = –3.5dB (CH 0 and CH 1). Propagation delay between 50% level at input and output See Figure 5 tidleEntry tidleExit Idle entry and exit times See Figure 6 CTX Tx input capacitance to GND At 2.5 GHz UI 72 dB dB 60 2.0 HPF to remove DC 2.6 3.0 V 30 100 mVpp 10 mV 200 mV 10 mV 600 mV 0 35 0 30 mA 50 ps 20 ps 290 350 ps 4 6 ns 1.25 pF EQUALIZATION TTX-EYE (1) (2) DJTX (2) RJTX (2) (4) TTX-EYE (1) (2) (3) (4) 8 0.14 0.5 0.06 0.3 UIpp (3) Random Jitter (Rj) 0.08 0.2 Total Jitter (Tj) at point B 0.14 0.5 0.06 0.3 UIpp (3) 0.08 0.2 Deterministic Jitter (Dj) (1) (2) DJTX (2) RJTX Total Jitter (Tj) at point A Deterministic Jitter (Dj) (2) (4) Device setting: OS1 = L, DE1 = H, EQ1 = L Device setting: OS2 = H, DE2 = H, EQ2 = L Random Jitter (Rj) -12 Includes Rj at 10 Measured at the end of reference channel in Figure 8 with K28.5 pattern, VID=1000mVpp, 5Gbps, –3.5dB DE from source. UI = 200ps Rj calculated as 14.069 times the RMS random jitter for 10-12 BER Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com IN Tdiff_HL Tdiff_LH OUT Figure 5. Propagation Delay vertical spacer vertical spacer IN+ VEID_TH VCM INtidleEntry tidleExit OUT+ VCM OUT- Figure 6. Electrical Idle Mode Exit and Entry Delay vertical spacer vertical spacer 80 % 20 % tr tf Figure 7. Output RIse and Fall Times Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 9 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Jitter Measurement CH1 A SN65LVPE502 1 2 AWG* CH1 Up to 3m (30AWG) 20" 4" 1"-6" B *Source Jitter Measurements Total Jitter Deterministic Jitter Random Jitter Jitter Measurement CH2 AWG* CH2 (ps) 21pp 8pp 0.95 rms Figure 8. Jitter Measurement Setup vertical spacer vertical spacer 1-bit 1 to N bits tDE 1-bit 1 to N bits EQx = NC -3.5dB -6dB EQx = 0 -8.5dB EQx = 1 VCM VTXDIFF_NTB_PP VTXDIFF_TB_PP tDE Figure 9. Output De-Emphasis Levels OSx = NC 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Typical Eye Diagram and Performance Curves Input Signal Characteristics: Data Rate = 5 Gbps, VID = 1000 mVpp, DE = -3.5 dB, Pattern = K28.5 Device Operating Conditions: VCC = 3.3 V, Temp = 25°C Input Trace Length Held Constant and Output Cable Length Varied Figure 10. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 1 M vertical spacer vertical spacer Figure 11. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 2 M Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 11 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Figure 12. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 3 M vertical spacer vertical spacer Figure 13. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 4 M 12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com 25 Deterministic Jitter - ps - pk-pk 20 15 10 5 Output Deterministic Jitter vs Output USB3.0 Cable Length With Fixed 12” Input Trace 0 1 1.5 2 2.5 3 Output USB Cable Length - m 3.5 4 Figure 14. Jitter Performance Over Different Cable Lengths Input Trace Length Held Constant and Output Trace Varied Figure 15. Input Trace = 4 Inches, 6 mil and Output Trace = 4 Inches, 6 mil Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 13 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Figure 16. Input Trace = 4 Inches, 6 mil and Output Trace = 8 Inches, 6 mil vertical spacer vertical spacer Figure 17. Input Trace = 4 Inches, 6 mil and Output Trace = 12 Inches, 6 mil 14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Figure 18. Input Trace = 4 Inches, 6 mil and Output Trace = 16 Inches, 6 mil vertical spacer vertical spacer Figure 19. Input Trace = 4 Inches, 6 mil and Output Trace = 20 Inches, 6 mil Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 15 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com 10 9 Deterministic Jitter - ps - pk-pk 8 7 6 5 4 3 2 Output Deterministic Jitter vs Output Trace Length With Fixed 4” Input Trace 1 0 4 6 8 10 12 14 16 6 mil Output Trace Length - Inches 18 20 Figure 20. Jitter Performance Over Different Output Trace Lengths vertical spacer vertical spacer Output Trace Length Held Constant and Input Trace Length Varied Figure 21. Input Trace = 4 Inches, 6 mil and Output Trace = 4 Inches, 6 mil 16 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Figure 22. Input Trace = 8 Inches, 6 mil and Output Trace = 4 Inches, 6 mil vertical spacer vertical spacer Figure 23. Input Trace = 12 Inches, 6 mil and Output Trace = 4 Inches, 6 mil Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 17 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Figure 24. Input Trace = 16 Inches, 6 mil and Output Trace = 4 Inches, 6 mil vertical spacer vertical spacer Figure 25. Input Trace = 20 Inches, 6 mil and Output Trace = 4 Inches, 6 mil 18 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com Figure 26. Input Trace = 28 Inches, 6 mil and Output Trace = 4 Inches, 6 mil vertical spacer vertical spacer Figure 27. Input Trace = 32 Inches, 6 mil and Output Trace = 4 Inches, 6 mil Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 19 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com 14 Deterministic Jitter - ps - pk-pk 12 10 8 6 4 2 Output Deterministic Jitter vs Input Trace Length With Fixed 4” Output Trace 0 4 9 14 19 24 6 mil Input Trace Length - Inches 29 Figure 28. Jitter Performance Over Different Input Trace Lengths 20 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 SN65LVPE502 SLLSE29 A – APRIL 2010 – REVISED FEBRUARY 2012 www.ti.com REVISION HISTORY Changes from Original (April 2010 ) to Revision A • Page Changed in Table 1. Pin Description, signals: TX1+, TX1-, TX2+ and TX2- , I/O types changed from O, CML to O, VML also in Descripton, 'CML' to 'VML' ................................................................................................................................ 4 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE502 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVPE502RGER NRND VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 LVPE502 SN65LVPE502RGET NRND VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 LVPE502 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of