SN74AHC125QPWRQ1

SN74AHC125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCLS525A − AUGUST 2003 − REVISED APRIL 2008 DQualified for Automotive Applications DESD Protection Exceeds 1000 V Per D OR PW PACKAGE (TOP VIEW) MIL-STD-883, Method 3015; Exceeds 150 V Using Machine Model (C = 200 pF, R = 0) DEPIC (Enhanced-Performance Implanted CMOS) Process DOperating Range 2-V to 5.5-V VCC DLatch-Up Performance Exceeds 250 mA Per JESD 17 1OE 1A 1Y 2OE 2A 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y description/ordering information The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION{ −40°C 40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − D Tape and reel SN74AHC125QDRQ1 AHC125Q TSSOP − PW Tape and reel SN74AHC125QPWRQ1 AHC125Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHC125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCLS525A − AUGUST 2003 − REVISED APRIL 2008 logic symbol† 1 1OE 1A EN 2 1 3 4 2OE 2A 3OE 3A 4OE 4A † 6 5 1Y 2Y 10 8 9 13 11 12 3Y 4Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 4 5 3A 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AHC125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCLS525A − AUGUST 2003 − REVISED APRIL 2008 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level High level input voltage MIN MAX 2 5.5 VCC = 2 V 1.5 VCC = 3 V 2.1 VCC = 5.5 V UNIT V V 3.85 VCC = 2 V 0.5 VCC = 3 V 0.9 VIL Low-level Low level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V −50 mA IOH High-level High level output current VCC = 5.5 V 1.65 VCC = 2 V IOL Low-level Low level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature V VCC = 3.3 V ± 0.3 V −4 VCC = 5 V ± 0.5 V −8 VCC = 2 V 50 VCC = 3.3 V ± 0.3 V 4 VCC = 5 V ± 0.5 V 8 VCC = 3.3 V ± 0.3 V mA mA mA 100 VCC = 5 V ± 0.5 V 20 −40 125 ns/V °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 50 mA VCC TA = 25°C MAX MIN MIN TYP 2V 1.9 2 1.9 3V 2.9 3 2.9 4.5 V 4.4 4.5 4.4 IOH = −4 mA 3V 2.58 2.48 IOH = −8 mA 4.5 V 3.94 3.8 VOH IOL = 50 mA MAX V 2V 0.1 0.1 3V 0.1 0.1 4.5 V 0.1 0.1 IOL = 4 mA 3V 0.36 0.5 IOL = 8 mA 4.5 V 0.36 0.5 VOL UNIT V II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 mA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 mA ICC VI = VCC or GND, 4 40 mA Ci VI = VCC or GND IO = 0 5.5 V 5V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4 10 pF 3 SN74AHC125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCLS525A − AUGUST 2003 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 15 pF OE Y CL = 15 pF OE Y CL = 15 pF A Y CL = 50 pF OE Y CL = 50 pF OE Y CL = 50 pF TA = 25°C MIN MIN MAX 8 1 9.5 8 1 9.5 5.4 8 1 9.5 5.4 8 1 9.5 7 9.7 1 11.5 7 9.7 1 11.5 8.1 11.5 1 13 8.1 11.5 1 13 7.9 11.5 1 13 7.9 11.5 1 13 9.5 13.2 1 15 9.5 13.2 1 15 TYP MAX 5.6 5.6 UNIT ns ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 15 pF OE Y CL = 15 pF OE Y CL = 15 pF A Y CL = 50 pF OE Y CL = 50 pF OE Y CL = 50 pF TA = 25°C MIN MIN MAX 5.5 1 6.5 5.5 1 6.5 3.6 5.1 1 6 3.6 5.1 1 6 4.6 6.8 1 8 4.6 6.8 1 8 5.3 7.5 1 8.5 5.3 7.5 1 8.5 5.1 7.1 1 8 5.1 7.1 1 8 6.1 8.8 1 10 6.1 8.8 1 10 MIN MAX TYP MAX 3.8 3.8 UNIT ns ns ns ns ns ns noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER VOL(P) Quiet output, maximum dynamic VOL VOL(V) Quiet output, minimum dynamic VOL VOH(V) Quiet output, minimum dynamic VOH 4.4 VIH(D) High-level dynamic input voltage 3.5 VIL(D) Low-level dynamic input voltage UNIT 0.8 V −0.8 V V V 1.5 V TYP UNIT NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 14 pF SN74AHC125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCLS525A − AUGUST 2003 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC 50% VCC Input 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AHC125QDRG4Q1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC125Q SN74AHC125QPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC125Q SN74AHC125QPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AHC125Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of