SN74AHC74QPWRQ1

   
             
 SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC (Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW) CMOS) Process 1CLR 1D 1CLK 1PRE 1Q 1Q GND D Operating Range 2-V to 5.5-V VCC D Latch-Up Performance Exceeds 250 mA Per D JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description The SN74AHC74Q dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION{ −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − D Tape and reel SN74AHC74QDRQ1 TSSOP − PW Tape and reel SN74AHC74QPWRQ1 AHC74Q HA74Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. Copyright  2008, Texas Instruments Incorporated   ! " #$%! "  &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%"  %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
   
             
 SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H† H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic symbol‡ 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 2 1 5 S 3 1Q C1 1D 6 R 10 9 11 1Q 2Q 12 8 13 2Q ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
             
 SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 2 V VCC = 3 V High-level input voltage VCC = 5.5 V VCC = 2 V VIL VI VO IOH ∆t/∆v MAX 2 5.5 Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 3.3 V ± 0.3 V High-level output current Low-level output current Input transition rise or fall rate UNIT V 1.5 2.1 V 3.85 0.5 VCC = 3 V VCC = 5.5 V VCC = 5 V ± 0.5 V VCC = 2 V IOL MIN 0.9 V 1.65 0 5.5 V 0 VCC −50 mA V −4 −8 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 4 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 100 8 20 mA mA mA ns/V TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
   
             
 SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC MIN TA = 25°C TYP MAX MIN 2V 1.9 2 1.9 3V 2.9 3 2.9 4.5 V 4.4 4.5 4.4 3V 2.58 4.5 V 3.94 TEST CONDITIONS IOH = −50 mA VOH IOH = −4 mA IOH = −8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA II ICC VI = 5.5 V or GND VI = VCC or GND, Ci VI = VCC or GND IO = 0 MAX UNIT V 2.48 3.8 2V 0.1 0.1 3V 0.1 0.1 4.5 V 0.1 0.1 V 3V 0.36 0.5 4.5 V 0.36 0.5 0 V to 5.5 V ±0.1 ±1 mA 2 20 mA 5.5 V 5V 2 10 pF timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN PRE or CLR low 6 7 CLK 6 7 Data 6 7 PRE or CLR inactive 5 5 0.5 0.5 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX 4 tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ POST OFFICE BOX 655303 MIN PRE or CLR low 5 5 CLK 5 5 Data 5 5 PRE or CLR inactive 3 3 0.5 0.5 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns 
   
             
 SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax LOAD CAPACITANCE MIN TA = 25°C TYP MAX MIN CL = 15 pF 80 125 70 CL = 50 pF 50 75 45 tPLH tPHL PRE or CLR Q or Q CL = 15 pF tPLH tPHL CLK Q or Q CL = 15 pF tPLH tPHL PRE or CLR Q or Q CL = 50 pF tPLH tPHL CLK Q or Q CL = 50 pF MAX UNIT MHz 7.6 12.3 1 14.5 7.6 12.3 1 14.5 6.7 11.9 1 14 6.7 11.9 1 14 10.1 15.8 1 18 10.1 15.8 1 18 9.2 15.4 1 17.5 9.2 15.4 1 17.5 ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX LOAD CAPACITANCE MIN CL = 15 pF 130 170 110 CL = 50 pF 90 115 75 tPLH tPHL PRE or CLR Q or Q CL = 15 pF tPLH tPHL CLK Q or Q CL = 15 pF tPLH tPHL PRE or CLR Q or Q CL = 50 pF tPLH tPHL CLK Q or Q CL = 50 pF MIN MAX UNIT MHz 4.8 7.7 1 9 4.8 7.7 1 9 4.6 7.3 1 8.5 4.6 7.3 1 8.5 6.3 9.7 1 11 6.3 9.7 1 11 6.1 9.3 1 10.5 6.1 9.3 1 10.5 MIN MAX ns ns ns ns noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.7 V High-level dynamic input voltage 3.5 V Quiet output, minimum dynamic VOL VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. 0.8 V −0.8 V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 32 pF 5 
   
             
 SGDS020A − FEBRUARY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL VCC Output Control Output Waveform 1 S1 at VCC (see Note B) 50% VCC 0V tPZL 50% VCC tPLZ ≈VCC 50% VCC tPZH tPLH VOH 50% VCC VOL 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74AHC74QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 AHC74Q SN74AHC74QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 AHC74Q SN74AHC74QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 HA74Q SN74AHC74QPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR -40 to 125 HA74Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of