SN74AHC573QPWRQ1

SN74AHC573-Q1 www.ti.com.................................................................................................................................................. SCLS697A – DECEMBER 2005 – REVISED APRIL 2008 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS FEATURES 1 • • • PW PACKAGE (TOP VIEW) Qualified for Automotive Applications Operating Range 2-V to 5.5-V VCC 3-State Outputs Directly Drive Bus Lines OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE DESCRIPTION The SN74AHC573 is an octal transparent D-type latch designed for 2-V to 5.5-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) TSSOP – PW ORDERABLE PART NUMBER Reel of 2000 SN74AHC573QPWRQ1 TOP-SIDE MARKING HA573Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE (EACH LATCH) INPUTS OUTPUT Q OE LE D L H H H L H L L L L X Q0 H X X Z 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2008, Texas Instruments Incorporated SN74AHC573-Q1 SCLS697A – DECEMBER 2005 – REVISED APRIL 2008.................................................................................................................................................. www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) OE LE 1 11 C1 1D 2 1D 19 1Q To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VO Output voltage range (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND θJA Package thermal impedance (3) PW package Human-Body Model ESD rating (4) (1) (2) (3) (4) 2 Storage temperature range mA 83 °C/W 1 (H1C) Charged-Device Model 1 (C5) Machine Model Tstg ±75 –65 kV 200 (M3) V 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. ESD protection level per AEC Q100 classification Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): SN74AHC573-Q1 SN74AHC573-Q1 www.ti.com.................................................................................................................................................. SCLS697A – DECEMBER 2005 – REVISED APRIL 2008 Recommended Operating Conditions (1) –40°C to 125°C VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High-level input voltage VCC = 3 V MAX 2 5.5 UNIT V 1.5 2.1 2.1 3.85 3.85 VCC = 2 V Low-level input voltage MIN 1.5 VCC = 5.5 V VIL –40°C to 85°C V 0.5 VCC = 3 V VCC = 5.5 V 0.5 0.9 0.9 1.65 1.65 V VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V µA IOH High-level output current VCC = 2 V IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) –50 –50 VCC = 3.3 V ± 0.3 V –4 –4 VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V 50 50 VCC = 3.3 V ± 0.3 V 4 4 VCC = 5 V ± 0.5 V 8 8 100 100 20 20 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –40 125 –40 85 mA µA mA ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA MAX –40°C to 125°C –40°C to 85°C MIN MAX MIN MAX MIN TYP 2V 1.9 2 1.9 1.9 2.9 3V 2.9 3 2.9 4.5 V 4.4 4.5 4.4 4.4 IOH = –4 mA 3V 2.58 2.48 2.48 IOH = –8 mA 4.5 V 3.94 VOH IOL = 50 µA VOL IOL = 4 mA IOL = 8 mA II TA = 25°C VCC VI = 5.5 V or GND 3.8 UNIT V 3.8 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 V 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1 ±1 µA IOZ VI = VIL or VIH, VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 µA Ci VI = VCC or GND 5V 2.5 10 pF Co VO = VCC or GND 5V 3.5 Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): SN74AHC573-Q1 10 pF Submit Documentation Feedback 3 SN74AHC573-Q1 SCLS697A – DECEMBER 2005 – REVISED APRIL 2008.................................................................................................................................................. www.ti.com Timing Requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration, LE high tsu th –40°C to 125°C MAX MIN –40°C to 85°C MAX MIN UNIT MAX 5 5 5 ns Setup time, data before LE↓ 3.5 3.5 3.5 ns Hold time, data after LE↓ 1.5 1.5 1.5 ns Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN –40°C to 125°C MAX MIN –40°C to 85°C MAX MIN UNIT MAX tw Pulse duration, LE high 5 5 5 ns tsu Setup time, data before LE↓ 3.5 3.5 3.5 ns th Hold time, data after LE↓ 1.5 1.5 1.5 ns Switching Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE D Q CL = 50 pF LE Q CL = 50 pF OE Q CL = 50 pF OE Q CL = 50 pF tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ TA = 25°C MIN –40°C to 125°C –40°C to 85°C UNIT TYP MAX MIN MAX MIN MAX 9.5 14.5 1 16.5 1 16.5 9.5 14.5 1 16.5 1 16.5 10.1 15.4 1 17.5 1 17.5 10.1 15.4 1 17.5 1 17.5 9.8 15 1 17 1 17 9.8 15 1 17 1 17 10.7 14.5 1 16.5 1 16.5 10.7 14.5 1 16.5 1 16.5 ns ns ns ns Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE D Q CL = 50 pF LE Q CL = 50 pF OE Q CL = 50 pF OE Q CL = 50 pF tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ TA = 25°C MIN –40°C to 125°C –40°C to 85°C UNIT TYP MAX MIN MAX MIN MAX 6 8.8 1 10 1 10 6 8.8 1 10 1 10 6.5 9.7 1 11 1 11 6.5 9.7 1 11 1 11 6.7 9.7 1 11 1 11 6.7 9.7 1 11 1 11 6.7 9.7 1 11 1 11 6.7 9.7 1 11 1 11 ns ns ns ns Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS No load, Submit Documentation Feedback f = 1 MHz TYP 16 UNIT pF Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): SN74AHC573-Q1 SN74AHC573-Q1 www.ti.com.................................................................................................................................................. SCLS697A – DECEMBER 2005 – REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL VOH 50% VCC VOL 50% VCC tPHL Out-of-Phase Output Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 50% VCC tPZL tPLZ ≈VCC 50% VCC VOL + 0.3 V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): SN74AHC573-Q1 Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AHC573QPWRG4Q1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA573Q SN74AHC573QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA573Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of