SN74AHC1G125DCKR

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software SN74AHC1G125 SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 SN74AHC1G125 Single Bus Buffer Gate With 3-State Output 1 Features 3 Description • • • • The SN74AHC1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output. 1 Operating Range of 2 V to 5.5 V Max tpd of 6 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V Device Information(1) 2 Applications • • • • • • Projectors TVs Servers Motor Controls: AC Induction Patient Monitoring Electronic Points of Sale PART NUMBER SN74AHC1G125 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm x 1.60 mm SC-70 (5) 2.00 mm x 1.30 mm SOT-553 (5) 1.65 mm x 1.20 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic OE A Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AHC1G125 SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 4 4 4 5 5 5 6 6 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ Switching Characteristics, VCC = 5 V ± 0.5 V ........... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 9 Detailed Description .............................................. 8 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 8 8 8 8 10 Application and Implementation.......................... 9 10.1 Application Information............................................ 9 10.2 Typical Application ................................................. 9 11 Power Supply Recommendations ..................... 10 12 Layout................................................................... 11 12.1 Layout Guidelines ................................................. 11 12.2 Layout Example .................................................... 11 13 Device and Documentation Support ................. 11 13.1 Trademarks ........................................................... 11 13.2 Electrostatic Discharge Caution ............................ 11 13.3 Glossary ................................................................ 11 14 Mechanical, Packaging, and Orderable Information ........................................................... 11 5 Revision History Changes from Revision J (June 2005) to Revision K Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. .......................................... 4 2 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 SN74AHC1G125 www.ti.com SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 6 Pin Configuration and Functions DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) OE 1 A 2 GND 3 OE 1 A 2 GND 3 5 VCC 5 4 DRL PACKAGE (TOP VIEW) VCC Y OE 1 A 2 GND 3 5 VCC 4 Y Y 4 See mechanical drawings for dimensions. Pin Functions PIN NO. 1 NAME OE TYPE DESCRIPTION I Output Enable Input A 2 A I 3 GND — Ground Pin 4 Y O Output Y 5 VCC — Power Pin Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 3 SN74AHC1G125 SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 7 UNIT V (2) –0.5 7 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 °C Continuous channel current through VCC or GND Tstg (1) (2) Storage temperature range –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 1500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 2000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VIH High-level input voltage MIN MAX 2 5.5 VCC = 2 V 1.5 VCC = 3 V 2.1 VCC = 5.5 V UNIT V V 3.85 VCC = 2 V 0.5 VCC = 3 V 0.9 VIL Low-level input voltage VI Input voltage 0 5.5 VO Output voltage 0 VCC V –50 µA VCC = 5.5 V 1.65 VCC = 2 V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V VCC = 3.3 V ± 0.3 V –4 VCC = 5 V ± 0.5 V –8 VCC = 2 V 50 VCC = 3.3 V ± 0.3 V 4 VCC = 5 V ± 0.5 V 8 VCC = 3.3 V ± 0.3 V 100 VCC = 5 V ± 0.5 V 20 –40 125 V mA µA mA ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 SN74AHC1G125 www.ti.com SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 7.4 Thermal Information SN74AHC1G125 THERMAL METRIC (1) DBV DCK DRL UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 231.3 287.6 328.7 RθJC(top) Junction-to-case (top) thermal resistance 119.9 97.7 105.1 RθJB Junction-to-board thermal resistance 60.6 65. 150.3 ψJT Junction-to-top characterization parameter 17.8 2.0 6.9 ψJB Junction-to-board characterization parameter 60.1 64.2 148.4 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 µA VOH –40°C to 85°C MAX MIN MAX –40°C to 125°C MIN TYP MIN 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 4.5 V 4.4 4.4 4.4 IOH = −4 mA 3V 2.58 2.48 2.48 IOH = −8 mA 4.5 V 3.94 3.8 3.8 MAX UNIT V 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.44 0.44 IOL = 8 mA 4.5 V 0.36 0.44 0.44 VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 ±1 µA 5.5 V ±0.25 ±2.5 ±2.5 µA 5.5 V 1 10 10 µA 10 10 10 pF IOL = 50 µA VOL IOL = 4 mA II TA = 25°C IOZ VI = VCC or GND ICC VI = VCC or GND, Ci VI = VCC or GND 5V 4 Co VO = VCC or GND 5V 10 IO = 0 V pF 7.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 15 pF OE Y CL = 15 pF OE Y CL = 15 pF A Y CL = 50 pF OE Y CL = 50 pF OE Y CL = 50 pF TA = 25°C MIN –40°C to 85°C –40°C to 125°C TYP MAX MIN MAX MIN MAX 5.6 8 1 9.5 1 10.5 5.6 8 1 9.5 1 10.5 5.4 8 1 9.5 1 10.5 5.4 8 1 9.5 1 10.5 7 9.7 1 11.5 1 12.5 7 9.7 1 11.5 1 12.5 8.1 11.5 1 13 1 14 8.1 11.5 1 13 1 14 7.9 11.5 1 13 1 14 7.9 11.5 1 13 1 14 9.5 13.2 1 15 1 16 9.5 13.2 1 15 1 16 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 UNIT ns ns ns ns ns ns 5 SN74AHC1G125 SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 www.ti.com 7.7 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 15 pF OE Y CL = 15 pF OE Y CL = 15 pF A Y CL = 50 pF OE Y CL = 50 pF OE Y CL = 50 pF tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ TA = 25°C MIN –40°C to 85°C –40°C to 125°C TYP MAX MIN MAX MIN MAX 3.8 5.5 1 6.5 1 7 3.8 5.5 1 6.5 1 7 3.6 5.1 1 6 1 6.5 3.6 5.1 1 6 1 6.5 4.6 6.8 1 8 1 8.5 4.6 6.8 1 8 1 8.5 5.3 7.5 1 8.5 1 9.5 5.3 7.5 1 8.5 1 9.5 5.1 7.1 1 8 1 9 5.1 7.1 1 8 1 9 6.1 8.8 1 10 1 11 6.1 8.8 1 10 1 11 UNIT ns ns ns ns ns ns 7.8 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, TYP f = 1 MHz 14 UNIT pF 8 8 7 7 6 6 5 5 TPD (ns) TPD (ns) 7.9 Typical Characteristics 4 3 4 3 2 2 1 1 TPD in ns 0 -100 TPD in ns 0 -50 0 50 Temperature (qC) 100 150 0 1 D001 Figure 1. TPD vs Temperature 6 Submit Documentation Feedback 2 3 VCC 4 5 6 D002 Figure 2. TPD vs VCC at 25°C Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 SN74AHC1G125 www.ti.com SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 8 Parameter Measurement Information From Output Under Test Test Point From Output Under Test RL = 1 kΩ VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) 50% VCC 50% VCC tPLZ tPZL ≈VCC 50% VCC VOL + 0.3 V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V tPZH tPLH VOH 50% VCC VOL VCC Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 7 SN74AHC1G125 SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 www.ti.com 9 Detailed Description 9.1 Overview The SN74AHC1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram OE A Y Figure 4. Logic Diagram (Positive Logic) 9.3 Feature Description • • Wide operating voltage range – Operates from 2 V to 5.5 V Allows down-voltage translation – Inputs accept voltages to 5.5 V 9.4 Device Functional Modes Table 1. Function Table INPUTS 8 OE A OUTPUT Y L H H L L L H X Z Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 SN74AHC1G125 www.ti.com SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information SN74AHC1G125 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation. 10.2 Typical Application 5-V system 5-V regulated VCC OE µC or System Logic A Y µC System Logic LEDs GND Figure 5. Typical Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table. – For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table. 2. Recommend Output Conditions – Load currents should not exceed 25 mA per output and 50 mA total for the part. – Outputs should not be pulled above VCC. Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 9 SN74AHC1G125 SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 10.2.3 Application Curves Figure 6. 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 10 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 SN74AHC1G125 www.ti.com SCLS377K – AUGUST 1997 – REVISED DECEMBER 2014 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 12.2 Layout Example Vcc Input Unused Input Output Unused Input Output Input Figure 7. Layout Diagram 13 Device and Documentation Support 13.1 Trademarks All trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links: SN74AHC1G125 11 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74AHC1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A25G Samples 74AHC1G125DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A25G Samples 74AHC1G125DBVTE4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A25G Samples 74AHC1G125DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A25G Samples 74AHC1G125DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM3 Samples 74AHC1G125DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM3 Samples SN74AHC1G125DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (A253, A25G, A25J, A25L, A25S) Samples SN74AHC1G125DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (A253, A25G, A25J, A25L, A25S) Samples SN74AHC1G125DCK3 ACTIVE SC70 DCK 5 3000 RoHS & Non-Green SNBI Level-1-260C-UNLIM -40 to 85 AMY Samples SN74AHC1G125DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (AM3, AMG, AMJ, AM L, AMS) Samples SN74AHC1G125DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (AM3, AMG, AMJ, AM L, AMS) Samples SN74AHC1G125DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 AMS Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of