SN74AHC1G09DCKR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design SN74AHC1G09 SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 SN74AHC1G09 Single 2–Input Positive-AND Gate With Open-Drain Output 1 Features 3 Description • • • • The SN74AHC1G09 is a single 2-input positive-AND gate with an open drain output configuration. The device performs the Boolean logic Y = A × B or Y = A + B in positive logic. 1 • • Operating Range from 2 V to 5.5 V Maximum tpd of 6 ns at 5 V ±8-mA Output Drive at 5 V Schmitt-Trigger Action at All Inputs Makes the Circuit Tolerant for Slower Input Rise and Fall Time Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22: – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) 2 Applications • • • • • • • • • • • • • Barcode Scanners Cable Solutions E-Books Embedded PCs Field Transmitter: Temperature or Pressure Sensors Fingerprint Biometrics HVAC: Heating, Ventilating, and Air Conditioning Network-Attached Storage (NAS) Server Motherboard and PSU Software Defined Radios (SDR) TV: High Definition (HDTV), LCD, and Digital Video Communications Systems Wireless Data Access Cards, Headsets, Keyboards, Mice, and LAN Cards Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AHC1G09DBVR SOT-23 (5) 2.90 mm × 1.60 mm SN74AHC1G09DCKR SC70 (5) 2.00 mm × 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram A B 1 2 4 Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AHC1G09 SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 3 3 4 4 4 5 5 5 5 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ Switching Characteristics, VCC = 5 V ± 0.5 V ........... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 6 Detailed Description .............................................. 7 8.1 Overview ................................................................... 7 8.2 Functional Block Diagram ......................................... 7 8.3 Feature Description................................................... 7 8.4 Device Functional Modes.......................................... 7 9 Application and Implementation .......................... 8 9.1 Application Information.............................................. 8 9.2 Typical Application ................................................... 8 10 Power Supply Recommendations ....................... 9 11 Layout..................................................................... 9 11.1 Layout Guidelines ................................................... 9 11.2 Layout Example ...................................................... 9 12 Device and Documentation Support ................. 10 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 10 10 10 10 10 10 13 Mechanical, Packaging, and Orderable Information ........................................................... 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (January 2016) to Revision D Page • Deleted 200-V Machine Model from Features ....................................................................................................................... 1 • Changed description for pin A from No connection to Input................................................................................................... 3 • Added Receiving Notification of Documentation Updates section ....................................................................................... 10 Changes from Revision B (July 2011) to Revision C • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 SN74AHC1G09 www.ti.com SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View A 1 B 2 GND 3 DCK Package 5-Pin SC70 Top View 5 VCC 4 Y A 1 B 2 GND 3 Not to scale 5 VCC 4 Y Not to scale Pin Functions (1) PIN NAME I/O NO. DESCRIPTION A 1 I Input B 2 I Input GND 3 — Ground VCC 5 — Power pin Y 4 O Output (1) See Mechanical, Packaging, and Orderable Information for dimensions. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage –0.5 7 V VI Input voltage (2) –0.5 7 V –0.5 VCC + 0.7 (2) VO Output voltage IIK Input clamp current (VI < 0) –20 IOK Output clamp current (VO < 0 or VO > VCC) –20 IO Continuous output current (VO = 0 to VCC) –25 +25 mA Continuous current through VCC or GND –50 +50 mA 150 °C 150 °C TJ Maximum junction temperature Tstg Storage temperature (1) (2) –65 V mA mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 3 SN74AHC1G09 SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC (1) Supply voltage VCC = 2 V VIH High-level input voltage MIN MAX UNIT 2 5.5 V 1.5 VCC = 3 V 2.1 VCC = 5.5 V 3.85 V VCC = 2 V VIL Low-level input voltage 0.5 VCC = 3 V 0.9 VCC = 5.5 V 1.65 V VI Input voltage 0 5.5 VO Output voltage 0 5.5 V VCC = 2 V 50 µA VCC = 3.3 V ± 0.3 V 4 VCC = 5 V ± 0.5 V 8 IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) VCC = 3.3 V ± 0.3 V 100 VCC = 5 V ± 0.5 V 20 –55 V mA ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information SN74AHC1G09 THERMAL METRIC (1) RθJA (1) DBV (SOT-23) DCK (SC70) 5 PINS 5 PINS 206 252 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 50 µA VCC TA MIN TYP 0.1 3V 0.1 4.5 V VOL IOL = 4 mA 3V IOL = 8 mA II ICC 4.5 V VI = 5.5 V or GND 0 V to 5.5 V VI = VCC or GND, IO = 0 5.5 V 4 VI = VCC or GND 5V UNIT 0.1 TA = 25°C 0.36 TA = –40°C to +85°C 0.44 TA = –55°C to +125°C 0.55 TA = 25°C 0.36 TA = –40°C to +85°C 0.44 TA = –55°C to +125°C 0.55 TA = 25°C ±0.1 TA = –40°C to +85°C ±1 TA = –55°C to +125°C ±2 TA = 25°C 1 TA = –40°C to +85°C 10 TA = –55°C to +125°C Ci MAX 2V TA = 25°C TA = –55°C to +125°C Submit Documentation Feedback V µA µA 20 4 10 10 pF Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 SN74AHC1G09 www.ti.com SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) OUTPUT CAPACITANCE TA A or B Y CL = 15 pF TA = –40°C to +85°C 1 8 TA = –55°C to +125°C 1 8.5 MIN TYP MAX TA = 25°C tPD 3.6 TA = 25°C A or B Y CL = 50 pF UNIT 7 6.5 ns 11 TA = –40°C to +85°C 1.5 12 TA = –55°C to +125°C 1.5 12.5 ns 6.7 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range, VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) OUTPUT CAPACITANCE TA A or B Y CL = 15 pF TA = –40°C to +85°C 1 6 TA = –55°C to +125°C 1 6.5 MIN TYP MAX 2.5 5 TA = 25°C tPD TA = 25°C A or B Y CL = 50 pF 4.6 UNIT ns 7.5 TA = –40°C to +85°C 1.5 8 TA = –55°C to +125°C 1.5 8.5 ns 6.8 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz TYP UNIT 5 pF 6.9 Typical Characteristics 5 Signal Voltage (V) 4 3 2 1 0 0 5 10 15 20 25 30 35 40 45 50 Time (ns) C001 Figure 1. TPD Across VCC at 25°C Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 5 SN74AHC1G09 SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 www.ti.com 7 Parameter Measurement Information VCC From Output Under Test Test Point From Output Under Test RL = 1 kΩ S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC 50% VCC Input 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 50% VCC tPZL tPLZ ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V tPZH tPLH 50% VCC VCC Output Control VOL + 0.3 V tPHZ 50% VCC VOH − 0.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Since this device has open-drain outputs, tPLZ and tPZL are the same as tPD. G. tPZL is measured at VCC/2. H. tPLZ is measured at VOL + 0.3 V. VOH ≈0 V A. F. VOL Figure 2. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 SN74AHC1G09 www.ti.com SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 8 Detailed Description 8.1 Overview The SN74AHC1G09 device contains one open-drain positive-AND gate with a maximum sink current of 8 mA. A wide operating range of 2 V to 5.5 V enables this device to be used in many different systems, and a low tpd qualifies this device to be used in high-speed applications. 8.2 Functional Block Diagram A B 1 4 2 Y 8.3 Feature Description The wide operating voltage range of 2 V to 5 V allows the SN74AHC1G09 to be used in systems with many different voltage rails. In addition, the voltage tolerance on the output allows the device to be used for inverting up-translation or down-translation. The device is also equipped with Schmitt-trigger inputs, which increase the ability of the device to reject noise. 8.4 Device Functional Modes Table 1 lists the functional modes of the SN74AHC1G09. Table 1. Function Table INPUTS OUTPUT A B Y H H H(Z) L X L X L L Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 7 SN74AHC1G09 SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74AHC1G09 is used in the following example in a basic power sequencing configuration. Power sequencing is often used in applications that require a processor or other delicate device with specific voltage timing requirements in order to protect the device from malfunctioning. 9.2 Typical Application VCC = 5 V A Y MCU (MSP43x) B Temp. EN Sensor VO Figure 3. Typical Application Diagram 9.2.1 Design Requirements This device uses CMOS technology. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions: – Rise time and fall time specifications. See (Δt/ΔV) in Recommended Operating Conditions. – Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions. – Inputs are overvoltage-tolerant, allowing them to go as high as (VI maximum) in Recommended Operating Conditions at any valid VCC. 2. Absolute Maximum Conditions: – Load currents should not exceed (IO maximum) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in Absolute Maximum Ratings. – Outputs should not be pulled above VCC. 8 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 SN74AHC1G09 www.ti.com SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 Typical Application (continued) 9.2.3 Application Curve 5.5 V 5V 4.5 V 4V 3.5 V 3V 2.5 V HC VI AC AHC1G09 2V 1.5 V 1V 0.5 V 0V ±1 V ±1.5 V 0 2 4 6 8 10 12 Time (ns) 14 16 18 20 VCC = 5 V, Load = 50 Ω / 50 pF Figure 4. ICC vs Input Voltage 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended; if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must not ever float. In many cases, functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a triple-input AND gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. The following are the rules that must be observed under all circumstances: • All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. • The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever make more sense or is more convenient. 11.2 Layout Example VCC Unused Input Input Output Unused Input Output Input Figure 5. Layout Diagram Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 9 SN74AHC1G09 SCLS724D – MAY 2011 – REVISED SEPTEMBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Introduction to Logic, SLVA700 • Implications of Slow or Floating CMOS Inputs, SCBA004 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. 10 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: SN74AHC1G09 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74AHC1G09DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 (A093, A09G, A09J) SN74AHC1G09DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 (AJ3, AJG, AJJ) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of