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SN74AHC1G32
SCLS317P – MARCH 1996 – REVISED FEBRUARY 2017
SN74AHC1G32 Single 2-Input Positive-OR Gate
1 Features
3 Description
•
•
•
•
•
The SN74AHC1G32 device is a single 2-input
positive-OR gate. The device performs the Boolean
function Y = A + B or Y = A • B in positive logic.
1
•
Operating Range of 2 V to 5.5 V
Max tpd of 6.5 ns at 5 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Device Information(1)
PART NUMBER
PACKAGE
SN74AHC1G32
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOT (5)
1.60 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AV Receivers
Portable Audio Docks
Blu-Ray Players and Home Theaters
MP3 Players and Recorders
Personal Digital Assistants (PDAs)
Power:
– Telecom and Server AC DC Supply
– Single Controllers
– Analog
– Digital
Client and Enterprise Solid State Drives (SSDs)
LCD and Digital TVs and High-Definition TVs
(HDTVs)
Enterprise Tablets
Video Analytics Servers
Wireless Headsets, Keyboards, and Mice
Simplified Schematic
A
B
1
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G32
SCLS317P – MARCH 1996 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (July 2014) to Revision P
Page
•
Changed Handling Ratings table to ESD Ratings table ......................................................................................................... 4
•
Added MAX values for TA = 25°C in both Switching Characteristics tables. ......................................................................... 5
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 11
Changes from Revision N (June 2005) to Revision O
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. .............................................................................................................................................. 4
•
Changed MAX ambient temperature in Recommended Operating Conditions table. ........................................................... 4
•
Added Thermal Information table. ......................................................................................................................................... 5
•
Added –40 to +125°C to Electrical Characteristics table. ..................................................................................................... 5
•
Added –55°C to 125°C to both Switching Characteristics tables. ......................................................................................... 5
•
Added Typical Characteristics. .............................................................................................................................................. 6
2
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SCLS317P – MARCH 1996 – REVISED FEBRUARY 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
5
3
4
DCK Package
5-Pin SC70
Top View
A
1
B
2
GND
3
V CC
5
V CC
4
Y
Y
DRL Package
5-Pin SOT
Top View
A
1
B
2
GND
3
5
VCC
4
Y
See mechanical drawings for dimensions.
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
A
I
Input A
2
B
I
Input B
3
GND
—
Ground Pin
4
Y
O
Output Y
5
VCC
—
Power Pin
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SCLS317P – MARCH 1996 – REVISED FEBRUARY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
Supply voltage
(2)
MIN
MAX
–0.5
7
UNIT
V
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Output voltage
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
(2)
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature
–60
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
1500
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
MIN
MAX
2
5.5
Low-level input voltage
V
1.5
2.1
V
3.85
VCC = 2 V
VIL
UNIT
0.5
VCC = 3 V
0.9
VCC = 5.5 V
V
1.65
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 2 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise and fall rate
TA
Operating free-air temperature
(1)
4
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 3.3 V ± 0.3 V
100
VCC = 5 V ± 0.5 V
20
–40
125
V
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74AHC1G32
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
DRL (SOT)
5 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
231.3
287.6
328.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
119.9
97.7
105.1
°C/W
RθJB
Junction-to-board thermal resistance
60.6
65.0
150.3
°C/W
ψJT
Junction-to-top characterization parameter
17.8
2.0
6.9
°C/W
ψJB
Junction-to-board characterization parameter
60.1
64.2
148.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
–40 TO +80°C
TYP MAX
MIN
–40 TO +125°C
MAX
MIN
2V
1.9
2
1.9
1.9
3V
2.9
3
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
IOH = –50 µA
VOH
IOL = 50 µA
VOL
UNIT
MAX
V
3.8
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 4 mA
3V
0.36
0.44
0.44
IOL = 8 mA
4.5 V
0.36
0.44
0.44
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1
±1
µA
ICC
VI = VCC or GND,
1
10
10
µA
Ci
VI = VCC or GND
10
10
10
pF
IO = 0
5.5 V
5V
2
v
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
MIN
–40°C to +85°C
TYP
MAX
MIN
5.5
7.9
5.5
7.9
8
8
TYP
–40°C to +125°C
MAX
MIN
TYP
MAX
1
9.5
1
10
1
9.5
1
10
11.4
1
13
1
14
11.4
1
13
1
14
UNIT
ns
ns
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
MIN
–40°C to +85°C
TYP
MAX
MIN
3.8
5.5
3.8
5.5
5.3
5.3
TYP
–40°C to +125°C
MAX
MIN
TYP
MAX
1
6.5
1
7
1
6.5
1
7
7.5
1
8.5
1
9.5
7.5
1
8.5
1
9.5
UNIT
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ns
ns
5
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SCLS317P – MARCH 1996 – REVISED FEBRUARY 2017
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6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
TYP
UNIT
14
pF
f = 1 MHz
6.9 Typical Characteristics
7
8
6
7
TPD in ns
6
TPD (ns)
TPD (ns)
5
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
150
0
1
D001
Figure 1. TPD vs Temperature
6
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2
3
VCC (V)
4
5
6
D002
Figure 2. TPD vs VCC
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SCLS317P – MARCH 1996 – REVISED FEBRUARY 2017
7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74AHC1G32 device is a single 2-input positive OR gate with low drive that produces slow rise and fall
times. This reduces ringing on the output signal. The device also has Schmitt-trigger action that will allow for
slower or noisier inputs. The input signals are high impedance when VCC = 0 V.
8.2 Functional Block Diagram
A
B
1
4
2
Y
8.3 Feature Description
•
•
Wide operating voltage
– Operates from 2 V to 5.5 V
Allows down voltage translation
– Accepts input voltages to 5.5 V
8.4 Device Functional Modes
Table 1 shows the functional modes of the SN74AHC1G32 device.
Table 1. Function Table
INPUTS
8
A
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
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9 Application and Implementation
9.1 Application Information
The SN74AHC1G32 is a low-drive CMOS device that can be used for a multitude of bus-interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs can except voltages to 5.5 V at any valid VCC making it ideal for down
translation.
9.2 Typical Application
VCC
5V
3.3 V - 5 V Regulated
0.1 µF
µC
5-V Driver
Figure 4. Specific Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
• Recommended input conditions
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
• Recommended output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part
– Outputs should not be pulled above VCC
9.2.3 Application Curve
AC
HC
AHC
Figure 5. Switching Characteristics Comparison
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10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is most convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
10
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AHC1G32DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(A323, A32G, A32J,
A32L, A32S)
SN74AHC1G32DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A32G
SN74AHC1G32DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A32G
SN74AHC1G32DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(A323, A32G, A32J,
A32L, A32S)
SN74AHC1G32DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A32G
SN74AHC1G32DCK3
ACTIVE
SC70
DCK
5
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 85
AGY
SN74AHC1G32DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(AG3, AGG, AGJ, AG
L, AGS)
SN74AHC1G32DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AG3
SN74AHC1G32DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AG3
SN74AHC1G32DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(AG3, AGG, AGJ, AG
L, AGS)
SN74AHC1G32DCKTE4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AG3
SN74AHC1G32DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AG3
SN74AHC1G32DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(AGB, AGS)
SN74AHC1G32DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
(AGB, AGS)
(1)
NIPDAUAG
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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