SN74CB3T16211DL

SN74CB3T16211 www.ti.com SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 24-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V TOLERANT LEVEL SHIFTER Check for Samples: SN74CB3T16211 FEATURES 1 • 2 • • • • • • • • • • • • • • • • Member of the Texas Instruments Widebus™ Family Output Voltage Translation Tracks VCC Supports Mixed-Mode Signal Operation on All Data I/O Ports – 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC – 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC 5-V Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typ) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typ) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 70 μA Max) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Supports Digital Applications: Level Translation, PCI Interface, Bus Isolation Ideal for Low-Power Portable Equipment DGG, DGV, OR DL PACKAGE (TOP VIEW) NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 1A11 1A12 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 1B11 1B12 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 NC - No internal connection BRK BRK BRK BRK BRK 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2012, Texas Instruments Incorporated SN74CB3T16211 SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 www.ti.com DESCRIPTION/ORDERING INFORMATION The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). DESCRIPTION/ORDERING INFORMATION (CONTINUED) Figure 1. Typical DC Voltage-Translation Characteristics The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground. The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Table 1. ORDERING INFORMATION PACKAGE (1) TA (1) 2 TOP-SIDE MARKING SN74CB3T16211DL Tape and reel SN74CB3T16211DLR Tube SN74CB3T16211DGG Tape and reel SN74CB3T16211DGGR TVSOP – DGV Tape and reel SN74CB3T16211DGVR KR211 VFBGA – GQL (Pb-free) Tape and reel SN74CB3T16211GQLR KR211 VFBGA – ZQL (Pb-free) Tape and reel SN74CB3T16211ZQLR KR211 SSOP – DL –40°C to 85°C ORDERABLE PART NUMBER Tube TSSOP – DGG CB3T16211 CB3T16211 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 SN74CB3T16211 www.ti.com SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 brk brk GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 Table 2. TERMINAL ASSIGNMENTS 1 2 3 4 5 6 B A 1A2 1A1 NC (1) 1OE 2OE 1B1 C B 1A5 1A4 1A3 1B2 1B3 1B4 C 1A7 GND 1A6 1B5 GND 1B6 D 1A10 1A8 1A9 1B8 1B7 1B9 E 1A12 1A11 1B10 1B11 A D E F F 2A1 2A2 2B1 1B12 G G VCC GND 2A3 2B3 GND 2B2 H H 2A4 2A5 2A6 2B6 2B5 2B4 J J 2A7 2A8 2A9 2B9 2B8 2B7 K K 2A10 2A11 2A12 2B12 2B11 2B10 brk (1) NC – No internal connection Table 3. FUNCTION TABLE (EACH 12-BIT BUS SWITCH) INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 54 1A1 1B1 SW 14 1A12 42 1B12 SW 56 1OE 15 2A1 41 2B1 SW 28 2A12 29 SW 2B12 55 2OE Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 3 SN74CB3T16211 SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 www.ti.com SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) B A VG(1) Control Circuit EN(2) (1) Gate voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. (2) Internal enable signal applied to the switch Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) (2) MIN MAX UNIT VCC Supply voltage range VIN Control input voltage range (2) –0.5 7 V (3) –0.5 7 VI/O Switch I/O voltage range (2) V (3) (4) –0.5 7 V IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA II/O ON-state switch current (5) ±128 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (6) Tstg Storage temperature range DGG package 64 DGV package 48 DL package 56 GQL/ZQL package (1) (2) (3) (4) (5) (6) °C/W 42 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) 4 MIN MAX 2.3 3.6 UNIT VCC = 2.3 V to 2.7 V 1.7 5.5 VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V –40 85 °C V V V All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 SN74CB3T16211 www.ti.com SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 3 V, II = –18 mA VOH See Figure 3 and Figure 4 IIN Control inputs VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND VCC = 3.6 V, Switch ON, VIN = VCC or GND II TYP (2) MIN Ioff VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND V ±10 μA VI = 0.7 V to VCC – 0.7 V –40 μA ±5 VCC = 0, VO = 0 to 5.5 V, VI = 0 ICC –1.2 ±20 VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND (3) UNIT VI = VCC – 0.7 V to 5.5 V VI = 0 to 0.7 V IOZ MAX ±10 μA 10 μA VI = VCC or GND 70 VI = 5.5 V 70 μA Control inputs VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Control inputs VCC = 3.3 V, VIN = VCC or GND 4 pF Cio(OFF) VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND 5 pF Cio(ON) VCC = 3.3 V, Switch ON, VIN = VCC or GND VI/O = 5.5 V or 3.3 V VI/O = GND 13 VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0 IO = 24 mA 5 9.5 IO = 16 mA 5 9.5 IO = 64 mA 5 8.5 IO = 32 mA 5 8.5 ΔICC (4) Cin ron (5) VCC = 3 V, VI = 0 (1) (2) (3) (4) (5) 300 5 μA pF Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER tpd (1) (1) FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 UNIT MAX A or B B or A 0.25 ns ten OE A or B 1 12 1 10 ns tdis OE A or B 1 7.5 1 8.5 ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 5 SN74CB3T16211 SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator VI S1 RL VO 50 Ω 50 Ω VG2 RL CL (see Note A) TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V or GND 5.5 V or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V 5.5 V 30 pF 50 pF 0.15 V 0.3 V V∆ VCC Output Control (VIN) VCC/2 VCC VCC/2 VCC/2 0V tPLH VOH Output VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPZH tPHL VCC/2 0V tPZL Output Control (VIN) Open GND tPHZ VOH VCC/2 VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 2. Test Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 SN74CB3T16211 www.ti.com SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs INPUT VOLTAGE OUTPUT VOLTAGE vs INPUT VOLTAGE 4 VCC = 2.3 V IO = 1 µA TA = 25°C 3 VO – Output Voltage – V VO – Output Voltage – V 4 2 1 0 VCC = 3 V IO = 1 µA TA = 25°C 3 2 1 0 0 1 2 3 4 5 6 0 1 VI - Input Voltage - V 2 3 4 5 6 VI - Input Voltage - V Figure 3. Data Output Voltage vs Data Input Voltage Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 7 SN74CB3T16211 SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VOH – Output Voltage High – V VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 85°C 3.5 VOH – Output Voltage High – V 4 4 100 µA 8 mA 16 mA 24 mA 3 2.5 2 1.5 2.3 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 25°C 100 µA 8 mA 16 mA 24 mA 3 2.5 2 1.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC – Supply Voltage – V VCC – Supply Voltage – V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VOH – Output Voltage High – V 4 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = −40°C 100 µA 8 mA 16 mA 24 mA 3 2.5 2 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC – Supply Voltage – V Figure 4. VOH Values 8 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 SN74CB3T16211 www.ti.com SCDS147C – OCTOBER 2003 – REVISED AUGUST 2012 REVISION HISTORY Changes from Revision B (January 2006) to Revision C • Page Updated graphic and note in figure 1. .................................................................................................................................. 2 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Links: SN74CB3T16211 9 PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74CB3T16211DGGRE4 ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T16211 Samples SN74CB3T16211DGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T16211 Samples SN74CB3T16211DGVR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 KR211 Samples SN74CB3T16211DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T16211 Samples SN74CB3T16211DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T16211 Samples SN74CB3T16211ZQLR OBSOLETE BGA MICROSTAR JUNIOR ZQL 56 TBD Call TI Call TI KR211 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of