SN75DP120
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SLLSE08 – OCTOBER 2009
DisplayPort 1:1 Dual-Mode Repeater
Check for Samples: SN75DP120
FEATURES
1
•
•
•
•
•
DP Signal Repeater Supporting Dual-Mode
DisplayPort DP1.1a (DP++) Signaling
Supports Data Rates up to 2.7Gbps
Participates in DP Link Training to set Output
Voltage and Pre-Emphasis Levels
Automatic Selectable Equalization for
Improved Signal Integrity
Integrated HPD Inversion and Level
Translation Required on Some Source
Platforms
•
•
•
Enhanced ESD: 11 kV HBM on All Pins
Enhanced Commercial Temperature Range:
0°C to 85°C
36 Pin 6 × 6 QFN Package
APPLICATIONS
•
Personal Computer Market
– Desktop PC
– Notebook PC
– PC Docking Station
– PC Standalone Video Card
DESCRIPTION
The SN75DP120 is a single port Dual-Mode DisplayPort (DP++) repeater that regenerates the DP high speed
digital link.
Four levels of differential output voltage swing (VOD) and four levels of pre-emphasis are supported in
accordance with the DisplayPort specification version 1.1a.The device monitors the AUX channel and
automatically adjusts the output signaling levels in response to link training commands. The SN75DP120 also
supports multiple selectable levels of equalization to provide improved signal integrity in cases where the input
link has a high level of loss. The equalization level will be automatically selected based on link training. The
equalization in the DP120 is optimized to compensate losses of up to 6dB for frequencies up to 1.35GHz. This
corresponds to approximately 18–24 inches of FR4 trace with 4–6mil width.
A built in level translator for the hot plug detect (HPD) line and level translator / inverter for the cable adapter
detect line (CAD) allow for a reduction of the overall circuitry needed for a DisplayPort source system.
When not in use, the SN75DP120 device supports an ultra low power shutdown mode. In this mode the main link
outputs are disabled and pulled to GND, and the device draws less then 40 µW of power.
The device is characterized for an extended operational temperature range from 0°C to 85°C.
TYPICAL APPLICATION
GPU
DP++
SN75DP120
Fully Buffered
Solution
DP++
DisplayPort
Enabled
Monitor or HDTV
Computer/Notebook/Docking Station
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN75DP120
SLLSE08 – OCTOBER 2009
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TYPICAL IMPLEMENTATION
DP Only Source
Side Redriver
HPD_SINK
SN75
DP120
DP Receptacle
HPD_SRC
GfX
AUX AUX
INp INn
AUX CH- AUX CH+
Main Link
Lanes 0-3
100K
AUX CH+
AUX CH100K
3.3V
DP++ Source Side
Redriver
HPD_SRC
HPD_SINK
SN75
DP120
CAD_SINK
GfX
AUX
INp
DDC_CLK
DDC_SDA
AUX CH-
AUX CH+
AUX
INn
DP Receptacle
CAD_SRC
Main Link
Lanes 0-3
100K
AUX CH+
AUX CH100K
3.3V
2
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DATA FLOW BLOCK DIAGRAM
VDD referenced, inverted or
noninverted depending on CAD_INV
CAD_SRC
CADsrc
0.9V inverted or VDD noninverted,
depending on HPD_INV input setting
HPD_SRC
CADsink
CAD_SINK
HPDsink
HPD_SINK
HPDsrc
R inHPD
~125k
VDD
CAD_INV
CADinv
HPD_INV
HPDinv
VIterm
50
VBIAS
50
50
50
IN1p
EQ
OUT1p
DP++
Driver
IN1n
OUT1n
VIterm
50
VBIAS
50
50
50
IN2p
EQ
IN2n
OUT2p
DP++
Driver
OUT2n
VIterm
50
VBIAS
50
50
50
IN3p
EQ
IN3n
OUT3p
DP++
Driver
VIterm
50
50
50
IN4p
OUT3n
VBIAS
EQ
DP++
Driver
50
OUT4p
OUT4n
IN4n
AMPL
PRE_ EMP
EQ
VCC
GND
LP #
CADsink
AUX Monitor
and Link
Training
AMPL
PRE_ EMP
EQ
CADinv
HPDinv
HPDsrc
CADsrc
CADsink
HPDsink
Control
Logic
See Applications section
for LP# pin RC values
AUX_INp
AUX_INn
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OUT3n
OUT3p
GND
OUT2n
OUT2p
VCC
OUT1n
OUT1p
HPD_INV
RHH PACKAGE (TOP VIEW)
27 26 25 24 23 22 21 20 19
VCC
28
18
AUX_INn
OUT0n
29
17
AUX_INp
OUT0p
30
16
VCC
CAD_INV
31
15
HPD_SINK
GND
32
LP#
SN75DP120
36
10
VDD
1
2
3
4
5
6
7
8
9
IN3n
HPD_SRC
VCC
IN3p
CAD_SRC
11
GND
12
35
IN2n
34
IN0n
VCC
IN0p
IN2p
GND
IN1n
13
IN1p
CAD_SINK
33
GND
14
PIN FUNCTIONS
PIN
SIGNAL
NO.
I/O
DESCRIPTION
MAIN LINK INPUT PINS
IN0p/n
34, 35
IN1p/n
2, 3
IN2p/n
5, 6
IN3p/n
8, 9
DisplayPort Main Link Channel 0 Differential Input
I[100Ω diff]
DisplayPort Main Link Channel 1 Differential Input
DisplayPort Main Link Channel 2 Differential Input
DisplayPort Main Link Channel 3 Differential Input
MAIN LINK OUTPUT PINS
OUT0p/n
30, 29
OUT1p/n
26, 25
OUT2p/n
23, 22
OUT3p/n
20, 19
DisplayPort Main Link Channel 0 Differential Output
O[100Ω diff]
DisplayPort Main Link Channel 1 Differential Output
DisplayPort Main Link Channel 2 Differential Output
DisplayPort Main Link Channel 3 Differential Output
HOT PLUG DETECT PINS
HPD_SRC
11
HPD_SINK
15
O[3.3V/0.9V SE]
Hot Plug Detect Output to the DisplayPort Source
The polarity and output level of HPD_SRC is set by the HPD_INV pin
I[CMOS] w/ 125kΩ
Hot Plug Detect Input from DisplayPort Sink
pulldown
AUXILIARY DATA PINS
AUX_INp/n
17, 18
I/O
Bidirectional DisplayPort Auxiliary Data Line
CAD_SRC
12
O[CMOS]
Cable Adapter Detect Output to the DisplayPort Source
The polarity of CAD_SRC is set by the CAD_INV pin.
CAD_SINK
14
I [CMOS]
DisplayPort Cable Adapter Detect Input; No pulldown resistor on this pin.
CABLE ADAPTER DETECT PINS
CONTROL PINS (1)
LP#
(1)
4
33
I [CMOS]
Low Power Shutdown Mode
When LP# = H; Device in Active Mode
When LP# = L; Device in Shutdown mode. All main link outputs are disabled and pulled to
GND; Inputs ignored. HPD_SRC follows HPD_SINK.
An external capacitor may be required on this pin if it is connected to VCC by a pullup resistor.
See Application Information section.
(H) Logic High; (L) Logic Low
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PIN FUNCTIONS (continued)
PIN
SIGNAL
NO.
CAD_INV
31
I/O
DESCRIPTION
I [CMOS] w/ weak
pulldown
HPD_INV
27
I [CMOS] w/ weak
pulldown
CAD output polarity Inversion
When CAD_INV = H; CAD_SRC is INVERSE logic of CAD_SINK
When CAD_INV = L; CAD_SRC is NON-INVERSE logic of CAD_SINK
HPD output polarity Inversion
When HPD_INV = H; HPD_SRC is set to INVERSE logic of HPD_SINK, and HPD_SRC VOH is
fixed at 0.8V to 1.1V, i.e. not referenced to VDD
When HPD_INV = L; HPD_SRC is set to NON-INVERSE logic of HPD_SINK, and HPD_SRC
VOH is referenced to VDD
SUPPLY AND GROUND PINS
VDD
10
VCC
4, 16, 24,
28, 36
HPD_SRC (when HPD_INV = H) and CAD_SRC Supply
3.3V Supply
GND
1, 7, 13,
21, 32
Ground
STATUS DETECT AND OPERATING MODES FLOW DIAGRAM
The SN75DP120 switches between power saving and active modes in the following way:
LP# low
Power up
LP#=0
HPD_SINK low
for >tT(HPD)
LP# low
ShutDown
Mode
Standby
Mode
D3 pwr
down mode
LP# high
HPD_SINK low
for >tT(HPD)
LP# low
HPD_SINK
High AND
AUX Link
Training Started
Active Mode
CAD=0 -> DP
CAD=1 -> TMDS
enter D3
AUX cmd
Exit D3
AUX cmd
OR
HPD_SINK
Low to High
transition
invalid DPCD
register entry
any
e
st a t
Output
Disable
Mode
DPCD register
corrected
Figure 1. SN75DP120 Operational Modes Flow Chart
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Table 1. Description of SN75DP120 Modes
MODE
CHARACTERISTICS
CONDITIONS
ShutDown
Mode
Least amount of power consumption (most circuitry turned off);
HPD_SRC reflects HPD_SINK state, all other outputs are high
impedance and all other inputs are ignored.
DPCD registers and logic are held reset to default values
LP# is low
Standby Mode
Low power consumption; main link inputs and outputs are disabled,
AUX monitoring is enabled
LP# is high;
HPD_SINK low for longer than tT(HPD)
D3 Power
Down Mode
Low power consumption; main link inputs and outputs disabled,
AUX monitoring is enabled
LP# is high;
AUX command requested DP sink to enter D3
power saving mode
Active Mode
Data transfer (normal operation);
The device is either in TMDS mode (CAD_SINK=high) or DP mode
(CAD_SINK=low);
LP# is high;
HPD_SINK is high
HPD_SINK can also be low for less than tT(HPD)
(e.g. sink interrupt request to source)
Link Training has begun or completed
In DP mode, the AUX monitor is actively monitoring for link training,
and the output signal swing, input equalization level and lane count
depend on the link training. At power-up all main link outputs are
disabled by default. AUX Link training is necessary to overwrite the
DPCD registers to enable main link outputs.
In TMDS mode, the output signal swing will be 600mVp-p, and
transactions on the AUX lines will be ignored.
Output Disable DPCD write commands on the AUX bus detected by the SN75DP120
EN is high
Mode
will also write to the local DP120 DPCD register. The local DPCD
DPCD register 101h or 103h entry is invalid
registers should always be written with valid entries. If register 101h or
103h is written with an invalid value, the SN75DP120 disables the
OUTx main link output signals, forcing the DP sink to issue an
interrupt. The DP source can now re-train the link using valid DPCD
register values. As soon as all DPCD registers contain a valid entry,
the SN75DP120 switches back into the appropriate mode of operation.
For a list of valid and invalid DPCD register entries refer to Table 3 and
the DP1.1a specification Table 2-52 and Table 3-12.
Table 2. Transition Between Operational Modes
MODE TRANSITION
Shutdown → Standby
USE CASE
Activate DP120
TRANSITION SPECIFICS
1. LP# transitions from low to high
2. Receiver enters Standby mode
3. AUX listener turns on and begins to monitor the AUX
lines
Standby → Active
Turn on main link (monitor plugged in)
Active → D3
DP source requests temporary power down for
power savings
1. HPD_SINK input asserts high
2. Main link outputs turn on
1. Receive D3 entry command on AUX
2. Main link inputs and outputs are disabled
3. AUX monitor remains active
D3 → Active
Exit temporary power down
D3 → Standby
Exit temporary power down
1. HPD_SINK de-asserted to low for longer than tT(HPD)
Active → Standby
turn off main link (monitor unplugged)
1. HPD_SINK de-asserted for longer than tT(HPD)
Active/Standby →
Shutdown
Turn off DP120
1. AUX channel receives D3 exit command or HPD_SINK
transitions from low to high
2. Enable main link
2. Main link inputs and outputs are disabled
1. LP# pulled low
2. AUX, Main link inputs and outputs are disabled
3. Most IC circuitry is shut down for ultra low power
consumption
4. HPD_SRC reflects HPD_SINK
Any State → Output
Disable Mode
6
Invalid DPCD write value to register 101h or 103h
1. OUTx becomes disabled
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Table 2. Transition Between Operational Modes (continued)
MODE TRANSITION
Output Disable Mode
→ Any State
USE CASE
TRANSITION SPECIFICS
DPCD register values correct to a valid register
entry
1. Appropriate mode is re-entered
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
SN75DP120RHHR
DP120
36-pin QFN reel (large)
SN75DP120RHHT
DP120
36-pin QFN reel (small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE / UNIT
Supply voltage range (2)
VDD
–0.3 V to 4.0 V
Supply voltage range
VCC
–0.3 V to 4.0 V
Main Link I/O (INx, OUTx)
–0.3 V to VCC + 0.3 V
Main Link I/O (INx, OUTx) differential voltage
Voltage range
1.5V
HPD_SINK and CAD_SINK
–0.3 V to 5.5 V
HPD_SRC and CAD_SRC
–0.3 V to VCC + 0.3 V
Auxiliary (AUX_IN)
–0.3 V to 5.5 V
Control pins
–0.3 V to 4.0 V
Human body model (3)
Electrostatic discharge
11 kV
Charged-device model
(4)
±1500 V
Machine model (5)
±200 V
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-E
Tested in accordance with JEDEC Standard 22, Test Method C101-D
Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
PACKAGE
36-pin QFN (RHH)
(1)
DERATING FACTOR
ABOVE TA = 25°C
(1)
TA = 85°C
POWER RATING
PCB JEDEC STANDARD
TA ≤ 25°C
Low-K
1250 mW
12.5 mW/°C
500 mW
High-K
3095 mW
30.95 mW/°C
1238 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
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THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
UNIT
RθJB
Junction-to-board thermal
resistance
RθJC
Junction-to-case thermal
resistance
PN
Device power in Active Mode
LP# = VCC, ML: VOD = 1200mVp-p, 2.7Gbps PRBS;
AUX: VID = 1000mVp-p, 1Mbps
PRBS; VDD= 3.6V, VCC=3.6V Highest power level. All lanes
running at largest VOD swing.
PPDWN
Device Power under D3
Power Down Mode or
Standby
LP# = VCC, ML: VID = 0mVp-p, AUX: VID = 0mVp-p;
VDD= 3.6V, VCC=3.6V
PLP
Device power dissipation in
Shutdown mode
LP# = 0V, VDD= 3.6V, VCC=3.6V, HPD_INV = NC, 0V
40
µW
LP# = 0V, VDD= 3.6V, VCC=3.6, HPD_INV=VCC
2.5
mW
MAX
UNIT
(1)
4x4 Thermal vias under PowerPAD
MAX
4.35
°C/W
20.3
°C/W
720
mW
44
mW
The maximum rating is simulated under VDD, VCC = 3.6V.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
VDD
HPD_SRC and CAD_SRC reference voltage; HPD_SRC Ref voltage only when
HPD_INV = 0V
1.62
3.6
VCC
Supply voltage
3
3.6
V
TA
Operating free-air temperature
0
85
°C
0.20
1.40
Vp-p
2.7
Gbps
60
Ω
0
2
V
0
5.25
V
3.3
V
MAIN LINK DIFFERENTIAL PINS (INX, OUTX)
VID
Peak-to-peak input differential voltage
dR
Data rate
Rt
Termination resistance
VCM
Output common mode voltage
40
50
AUXILIARY PINS (AUX_IN)
VI
Input voltage
dR(AUX)
Auxiliary data rate
1
Mbps
HPD_SINK AND CAD_SINK
VIH
High-level input voltage
1.9
3.6
V
VIL
Low-level input voltage
0
0.8
V
CONTROL PINS (LP#, HPD_INV, CAD_INV)
VIH
High-level input voltage
1.9
3.6
V
VIL
Low-level input voltage
0
0.8
V
DEVICE POWER
The SN75DP120 main and AUX link is designed to run from a single supply voltage of 3.3V. However since the
device has a built in level shifter, another supply voltage (VDD) is needed to set the voltage level of HPD_SRC
and CAD_SRC pins.
NOTE
An external capacitor may be required on LP# pin if that pin is tied to the supply
through a pullup resistor. The capacitor specifies a proper power on reset for the
device. See Applications section for recommended resistor and capacitor values.
8
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
165
200
mA
LP# = VCC, ML: VID = 0mVp-p,
AUX: VID = 0mVp-p; VDD= 3.6V, VCC=3.6V
8
12
mA
LP# = 0V, VDD= 3.6V, VCC=3.6V HPD_INV,
CAD_INV = NC, 0V
1
10
µA
400
640
4
mA
1.2
1.8
µs
ICC
Supply current under active operating LP# = VCC, ML: VOD = 1200mVp-p,
mode
2.7Gbps PRBS; AUX: VID = 1000mVp-p,
1Mbps PRBS; VDD= 3.6V, VCC=3.6V
IPDWN
Device power under power down
mode (D3) or standby main link
disabled
Low power current
ILP
MIN
LP# = 0V, VDD= 3.6V, VCC=3.6V
HPD_INV=VCC
IDD
Supply current
VDD = 3.6V, HPD_INV = VDD
tPWDNEX
D3 Powerdown or standby mode exit
time
Total time for the device to exit from D3 or standby
state to active mode
HOT PLUG AND CABLE ADAPTER DETECT
The SN75DP120 has an integrated 125KΩ pull down on the HPD_SINK input pin. The HPD and CAD timing
diagrams in this section are for the non-inverting case. The same timing diagrams apply for the inverting case
except the output is inverted. The VOH level of CAD_SRC follows that of VDD irrespective of CAD_INV setting.
However VOH for HPD_SRC depends on HPD_INV setting. When HPD_INV is low or left floating, HPD_SRC
VOH follows that of VDD. When HPD_INV = H then HPD_SRC VOH is set to 0.8V – 1.1V irrespective of VDD.
Explanation of HPD power management and interrupt behavior of the SN75DP120 is located in the Application
Information section at the end of the datasheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH3.3
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 3.3 V, IOH = –100 µA,
CAD_SINK, HPD_SINK = H
3
V
VOH2.5
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 2.5 V, IOH = –100 µA,
CAD_SINK, HPD_SINK = H
2.25
V
VOH1.8
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 1.8 V, IOH = –100 µA,
CAD_SINK, HPD_SINK = H
1.62
VOL3.3
High-level output voltage
(CAD_SRC and HPD_SRC)
VOL2.5
VOL1.8
HPD_INV, CAD_INV = L
1.8
V
VDD = 3.3 V, IOL = 100 µA,
CAD_SINK, HPD_SINK = L
0.1
V
Low-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 2.5 V, IOL = 100 µA,
CAD_SINK, HPD_SINK = L
0.1
V
Low-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 1.8 V, IOL = 100 µA,
CAD_SINK, HPD_SINK = L
0.1
V
1.1
V
0.1
V
HPD_INV = H
VOH1.1
High-level output voltage
(HPD_SRC)
IOH = –100 µA,
HPD_SINK = L
VOL1.1
Low-level output voltage
(HPD_SRC)
IOH = 100 µA,
HPD_SINK = H
IIH
High-level input current
(HPD_SINK, CAD_SINK, HPD_INV, CAD_INV)
VIH = 2.0 V, VDD = 3.6 V
(Leakage includes pull down resistor)
–5
35
µA
IL
lLow-level input current
(HPD_SINK, CAD_SINK, HPD_INV, CAD_INV)
VIL = 0.8 V, VDD = 3.6 V
(Leakage includes pull down resistor)
–5
35
µA
RHPDIN
Weak pull down resistor on HPD_SINK
150
kΩ
0.8
100
0.9
125
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tPD(CAD)
Propagation delay
VDD = 3.3 V, See Figure 2 and Figure 5
tPD(HPD)
Propagation delay
VDD = 3.3 V, See Figure 2 and Figure 3, CL = 20 pF
tT(HPD)
HPD logic shut off time
VDD = 3.3 V, See Figure 4
MAX
6.4
22
6.4
250
UNIT
ns
22
ns
550
ms
1.1V
HPD_INV = L
HPD_INV = H
HPD Sink
HPD SRC
DP120
125 KW
10 KW
HPD Sink
100 KW
HPD SRC
DP120
125 KW
CAD_ INV = L
CAD Sink
TYP
100 KW
CAD_ INV =H
CAD Source
DP120
1 MW
1 MW
CL
CAD Sink
DP120
1 MW
CAD Source
CL
Figure 2. HPD and CAD Test Circuits
VCC
HPD _SINK
50%
0V
tPD(HPD)
VDD
HPD_SRC
tPD(HPD)
50%
0V
Figure 3. HPD Timing Diagram #1 (HPD_INV = L)
10
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HPD_SINK
VCC
0V
VDD
Sink Hot Plug Detect
Timeout
t T(HPD)
HPD _SRC
0V
Standby
Active
Figure 4. HPD Timing Diagram #2 (HPD_INV = L)
VCC
CAD _ SINK
50%
0V
t PD(CAD)
VCC
t PD(CAD)
CAD_ SRC
50%
0V
Figure 5. CAD Timing Diagram
DisplayPort Auxiliary Pins
The SN75DP120 is designed to monitor the bidirectional auxiliary signals in DP mode and participates in link
training. The SN75DP120 adjusts the output swing, output pre-emphasis, and the EQ setting of every main link
port. The SN75DP120 AUX monitor configures the output based on the DPCD addresses below.
The AUX channel is monitored for the Display Port D3 standby command. Upon detecting the D3 command, the
SN75DP120 will go into a low power standby state with the AUX activity monitor remaining active.
Table 3. DPCD Lookup Table
ADDRESS
NAME
00100h
LINK_BW_SET
DESCRIPTION
Main Link Bandwidth Setting
Bits 7:0 = link bandwidth setting
● 06h = 1.62Gbps per lane (default)
● 0Ah = 2.7Gbps per lane
Note: Setting the register value in register 0100h to anything else but 0Ah puts the device into
1.62Gbps mode.
00101h
LANE_COUNT_SET
Determines the number of lanes to be enabled
Bits 4:0 = lane count
● 1h = one lane
● 2h = two lanes
● 4h = four lanes
Note: Any other register value in register 0101h bit 4:0 is invalid and disables all OUTx lanes until
the register value is changed back to a valid entry. Default all lanes are disabled.
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Table 3. DPCD Lookup Table (continued)
ADDRESS
00103h
NAME
DESCRIPTION
TRAINING_LANE0_SET Sets the VOD and pre-emphasis levels for lane 0
Bits 1:0 = voltage swing
● 00 = voltage swing level 0 (default)
● 01 = voltage swing level 1
● 10 = voltage swing level 2
● 11 = voltage swing level 3
Bits 4:3 = pre-emphasis level
● 00 = pre-emphasis level 0 (default)
● 01 = pre-emphasis level 1
● 10 = pre-emphasis level 2
● 11 = pre-emphasis level 3
Note: The following combinations of output swing and pre-emphasis are not allowed for register
103h bits [1:0]/[4:3]: 01/11, 10/10, 10/11, 11/01, 11/10, 11/11; setting the DPCD register to any of
these invalid combinations disables all OUTx lanes until the register value is changed back to a
valid entry.
00104h
TRAINING_LANE1_SET
Sets the VOD and pre-emphasis levels for lane 1,
Same definition as lane 0
00105h
TRAINING_LANE2_SET
Sets the VOD and pre-emphasis levels for lane 2,
Same definition as lane 0
00106h
TRAINING_LANE3_SET
Sets the VOD and pre-emphasis levels for lane 3,
Same definition as lane 0
00600h
SET_POWER
Sets the power mode of the device
Bits 1:0 = Power mode
● 01 = Normal mode (default)
● 10 = Power down mode (D3 or Standby Mode)
When power down mode is selected, the main link and all analog circuits are shut down to minimize
power consumption. The AUX channel is still monitored. Upon detecting a D3 exit command or if
CAD_SNK goes high, the device exits the power down mode. The device will also exit D3 if
HPD_SNK goes low for longer than tT(HPD), which indicates that the DP sink was disconnected.
Note: Setting the register to the invalid combination 0600h[1:0]=00 or 11 is ignored by the device
and the device remains in normal mode.
ELECTRICAL CHARACTERISTICS
over recommended operating (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
1.6
Vp-p
Differential input voltage
VID(HYS)
Differential input hysteresis
IH
High-level input current
–1
1
µA
IL
Low-level input current
–1
1
µA
Tjit
Maximum allowable UI variation within a single
transaction
0.1
UI
12
0.25
MAX
VID
50
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Source Connector
GND
Sink Connector
2.5- 3.3V
SN75DP120
AUX+
AUX100 KW
1 MW
AUX+
50 W
75-200nF
75-200nF
AUX-
50 W
50 W
50 W
75-200nF
75-200nF
100 KW
1 MW
CAD= 0
3.3 V
GND
Figure 6. Auxiliary Channel Measurement
DisplayPort Main Link Pins
The SN75DP120 is designed to support DisplayPort’s high speed differential main link with four levels of output
voltage swing and four levels of pre-emphasis. The main link I/Os of the SN75DP120 are designed to be
compliant to the DisplayPort 1.1a specification.
ELECTRICAL CHARACTERISTICS
over recommended operating (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTx (Mainlink Outputs)
VODpp(1)
VODpp(2)
Output differential peak-to-peak
voltage Level 1
Output differential peak-to-peak
voltage Level 2
PRBS7 pattern at 1.67 Gbps and 2.7 Gbps,
Measured at TP1 in Figure 8
VODpp(3)
Output differential peak-to-peak
voltage Level 3
VODpp(4)
Output differential peak-to-peak
voltage Level 4
VODpp(5)
Output differential peak-to-peak
voltage TMDS mode
CAD_SINK = 3.6V
VODpp(CTS1.1)
Output differential peak-to-peak
voltage for DP Compliance v1.1
Level 3 (800mVpp),
Pattern used is PRBS7,
Measured at TP2 in Figure 8,
Per Eye Mask Test in CTS1.1
ΔVODpp1
Output differential peak-to-peak
voltage increase from Level 1 to
Level 2
ΔVODpp2
Output differential peak-to-peak
voltage increase from Level 2 to
Level 3
ΔVODpp3
Output differential peak-to-peak
voltage increase from Level 3 to
Level 4
1.67 Gbps
400
2.7 Gbps
350
Measured at TP2,
ΔVODppn = 20*log(VODpp2(n+1) / VODpp2(n)),
Refer to Section 3.2 in DP CTS1.1
400
mVp-p
600
mVp-p
800
mVp-p
1200
mVp-p
600
mVp-p
mVp-p
1.8
3.3
5.0
dB
1.1
2.7
4.1
dB
1.8
3.4
5.0
dB
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VPRE(0)
Driver output pre-emphasis 0 dB
Level
VPRE(1)
Driver output pre-emphasis
3.5 dB Level
VPRE(2)
Driver output pre-emphasis
6 dB level
VPRE(3)
Driver output pre-emphasis
9.5 dB level
VPRE2(0)
Driver output pre-emphasis
0dB level
Measured at TP2
Pre-emphasis delta
Measured at TP2,
At each supported pre-emphasis level:
Δ VPREn = VPRE2(n+1) - VPRE2(n)
ΔVPRE1
ΔVPRE2
ΔVPRE3
MIN
TYP
MAX
All VOD levels
See Figure 3-3 in DP CTS1.1,
PRBS7 pattern at 1.67 Gbps and 2.7
Gbps,
Measured at TP1
0
UNIT
dB
VOD = VODpp(1),
VODpp(2),
VODpp(3)
3.5
dB
VOD = VODpp(1),
VODpp(2)
6.0
dB
VOD = VODpp(1)
9.5
dB
0
dB
2.5
dB
1.9
dB
1.9
dB
VPRE_NPP
Pre-emphasis non-transition
peak-to-peak voltage range
All supported pre-emphasis levels,
Measured at TP2
ROUT2
Driver output impedance
40
RINT
Input termination impedance
40
VIterm
Input termination voltage
VOterm
Output common mode voltage
40
mV-pp
50
60
Ω
50
60
Ω
0
2
V
0
2
V
20
mVrms
VTXACCM
Output AC common mode voltage
Measured at 1.62Gbps and 2.7Gbps (All output and preemphasis levels),
Measured at TP2
ITXSHORT
Output short circuit current limit
OUT pins shorted to GND
50
mA
IRXSHORT
Input short circuit current limit
IN pins shorted to GND
50
mA
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
tR/F(DP)
Differential Output edge rate
(20%–80%)
PARAMETER
No pre-emphasis, 800mV differential swing,
Measured at TP1, PRBS7
60
tPD(ML)
Propagation delay time
tSK(1)
MAX
UNIT
150
ps
dR = 2.7Gbps, No pre-emphasis, 800 mV differential voltage
swing, See Figure 9
450
ps
Output Intra-pair skew
dR = 2.7Gbps, No pre-emphasis, 800 mV differential voltage
swing, PRBS7, See Figure 10
15
ps
tSK(2)
Output Inter-pair skew (1)
dR = 2.7Gbps, No pre-emphasis, 800 mV differential voltage
swing, PRBS7
40
ps
Peak-to-peak output residual jitter at
Pkg Pins
No pre-emphasis, All levels differential
voltage swing, PRBS7. Vid = 400 mVpp
TTP3-TTP2 in Figure 11
dR = 2.7 Gbps
10
tDPJIT1(PP)
dR = 1.62 Gbps
10
0.08
Peak-to-peak output residual jitter
No pre-emphasis, All levels differential
voltage swing, PRBS7. Vid = 400 mVpp,
TTP4-TTP1 in Figure 11
dR = 2.7 Gbps
tDPJIT2(PP)
dR = 1.62 Gbps
0.06
tSK(in)
Intra-pair skew at the input package
pins
dR = 2.7 Gbps
100
dR = 1.62 Gbps
300
TTMDSJIT1(PP)
Peak-to-peak output residual jitter at
Pkg Pins
dR = 2.25 Gbps, CAD_SINK = H , Input Vid = 600 mVp-p,
No pre-emphasis, See Figure 12
10
ps
TTMDSJIT2(PP)
Peak-to-peak output residual jitter
dR = 2.25 Gbps CAD_SINK = H, Input Vid = 600 mVp-p,
No pre-emphasis, See Figure 12
0.1
UI
(1)
14
TYP
ps
UI
ps
tSK(2) is the magnitude of the time difference between tPD(ML) of any two mainlink outputs on a single device.
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VOD
tF
tR
100%
80 %
RMS(VOCM)
0V
20 %
V TXACCM ( RMS )
0%
D+
V Iterm
0 V to 2V
D-
50 W
50 W
50 W
50 W
0. 5 pF
D+
100 nF
VD+
Receiver
V ID
Y
Driver
D-
100 nF
100 nF
VY
Z
VD-
100 nF
VZ
V ID = ( VD+ - VD- )
V IDp -p = 2*(VD+ - VD- )
VICM = ( VD+ + VD- )/2
V OD = VY - VZ
V ODp -p = 2*(VY – VZ )
V OCM = ( VY + VZ )/2
Figure 7. Main Link Test Circuit and Definitions
2 inch
FR4
TP1
DP Part
Signal
Analyzer
TP2
1 inch
FR4
Figure 8. Display Port Compliance Setup
ML_IN x+
ML_IN x-
Main Link
Input
0V
tPD(ML)
Main Link
Output
tPD(ML)
0V
Figure 9. Main Link Delay Measurement
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OUT-
50%
OUT+
tOUT+r
t sk(1)
tOUT-f
tOUT-r tOUT+f
= 0.5 * | (t OUT+r – t OUT-f) + (
t OUT+f
– t OUT-r) |
Figure 10. Intra-Pair Skew Measurement
Dock
Connector
6”
Coax
RX
+EQ
OUT
SMA
SMA
Coax
Clk-
Coax
SN75DP120
RX
+EQ
SMA
FR4 PCB
Trace
Coax
Video
Pattern
Generator
FR4 PCB
Trace
Coax
Clk+
RT
Coax
SMA
Data-
RT
SMA
SMA
Data+
GND
5”
GND
RT
Jitter Test
Instrument
RT
SMA
Coax
OUT
SMA
Coax
Jitter Test
Instrument
6“
TTP1
TTP2
RT = 50 W
TTP3
TTP4
(1)
All jitter measured at BER of 10-e9.
(2)
Residual jitter reflects the total jitter measured at TTP4 minus the jitter at TTP1.
(3)
5 inches on the output represents 2 inches of trace, plus connector, plus 2 more inches of trace.
Figure 11. Jitter Measurement Setup – DP Mode
16
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13”
GND
5”
SMA
Coax
RX
+ EQ
SMA
Coax
FR4 PCB
Trace
DataVideo
Pattern
Generator
SMA
600mVpp Clk+
Coax
GND
RT
SMA
RX
+ EQ
SMA
Clk-
SMA
SN75DP120
Coax
Coax
RT
Coax
OUT
FR4 PCB
Trace
Data+
RT
SMA
Jitter Test
Instrument
RT
Coax
OUT
SMA
Coax
Jitter Test
Instrument
RT = 50 W
TTP1
TTP2
TTP3
TTP4
(1)
All jitter measured at BER of 10-e9.
(2)
Residual jitter reflects the total jitter measured at TTP4 minus the jitter at TTP1.
(3)
Input trace of 13 inches represents 6 inches trace, connector, and additional 6 inches of trace.
(4)
Output trace of 5 inches represents 2 inches of trace, connector, and 2 inches of trace.
(5)
Input edge rate from Video Pattern Generator is 50ps (20%–80%) with output level 600mVpp.
(6)
CAD_SINK is H and DP120 output levels are set to 600mVp-p level.
Figure 12. Jitter Measurement Setup – TMDS Mode
TYPICAL CHARACTERISTICS
70
2.7Gbps, 400mVpp, 9.5dB
60
DJ - ps - pk-pk
1.62Gbps, 400mVpp, 9.5dB
50
40
2.7Gbps, 400mVpp, 6dB
1.62Gbps, 400mVpp, 6dB
30
2.7Gbps, 400mVpp, 3.5dB
20
2.7Gbps, 800mVpp, 0dB
1.62Gbps, 400mVpp, 3.5dB 1.62Gbps, 800mVpp, 0dB
10
1.62Gbps, 400mVpp, 0dB
0
0
2.7Gbps, 400mVpp, 0dB
5
10
15
20
Input Trace Length (inches) [width = 4 mil]
25
Figure 13. Output Jitter vs Input Trace Length
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TYPICAL CHARACTERISTICS (continued)
Figure 14. Eye Diagram at TP2 with 22 Inch FR4 Input Trace
Output Set at 800mVpp, 0dB at RBR (1.62 Gbps), with DP Source Compliance Eyemask
Figure 15. Eye Diagram at TP2 with 22 Inch FR4 Input Trace
Output Set at 800mVpp, 0dB at HBR (2.7 Gbps), with DP Source Compliance Eyemask
18
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APPLICATION INFORMATION
POWER ON RESET
On power up, the interaction of the LP# pin and power on ramp could result in digital circuits not being set
correctly. The device should not be enabled until the power on ramp has settled to 3V or higher to guarantee a
correct power on reset of the digital circuitry. If LP# cannot be held low by microcontroller or other circuitry until
the power on ramp has settled, then a pullup resistor and external capacitor are required to hold the device in the
low power reset state.
To use LP# as a reset pin, the pullup resistor should be connected from VCC to LP# and the capacitor from LP#
pin to GND. The RC time constant should be larger than 5 times of the power on ramp time (0 to VCC). The
pullup resistor should be less than 100KΩ. The following table shows example of power on ramp time and R and
C values.
Table 4. Recommended LP# RC Values
POWER ON RAMP
R
C
100 µs
6 kΩ
0.1 µF
0.5 ms
40 kΩ
0.1 µF
1 ms
100 kΩ
0.1 µF
5 ms
100 kΩ
0.5 µF
10 ms
100 kΩ
1 µF
HPD POWER MANAGEMENT AND INTERRUPT BEHAVIOR
The power management of the SN75DP120 is controlled by the state of the HPD_SINK pin as well as the low
power (LP#) pin. When HPD_SINK is LOW for tT(HPD) the SN75DP120 will enter a standby state. In this state
main link outputs will be high impedance and shutdown to conserve power. When HPD_SINK goes high the
device will enter the normal operational state.
The LP# pin puts the SN75DP120 in its lowest power mode, shutdown, when LP# is low. In this state, almost all
circuitry is shutdown with inputs and outputs at high impedance. HPD is still active, however, and HPD_SRC will
follow HPD_SINK.
1. HPD and Main Link behavior
– Case one: In this case HPD_SINK is initially LOW and the low power pin is also LOW. In this initial state
the device is in a low power mode. Once the HPD input goes to a HIGH state the device will remain in
the low power mode with both the main link and auxiliary I/O in a high impedance state. Refer Figure 16.
However the HPD_SRC signal is not gated by the LP# pin. HPD_SRC will follow HPD_SINK after the
propagation delay tPD(HPD).
– Case two: In this case HPD_SINK is initially LOW and the low power pin is HIGH. In this initial state the
device is in a standby mode. Once the HPD input goes to a HIGH state the device will come out of the
standby mode and will enter active mode enabling the main link. The HPD output to the source will follow
the logic state of the input HPD. See Figure 17, where HPD_INV = L.
1
1
LP#
LP#
0
0
1
1
HPD_SINK
HPD_SINK
0
0
HPD_SRC
1
Z
0
HPD_SRC
1
1
HI-Z
Main Link
1
Z
0
HI-Z
Main Link
DATA
0
0
Figure 16.
Figure 17.
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2. HPD Interrupt and Time Out
– In this case the HPD_SINK input is initially HIGH. The HPD_SRC output logic state will follow the state of
the HPD_SINK input (when HPD_INV = L). If the HPD_SINK input pulses LOW, as may be the case if the
Sink device is requesting an interrupt, the HPD_SRC output to the source will also pulse Low for the
same duration of time with a slight delay (see Figure 18). The delay of this signal through the
SN75DP120 is specified as tPD(HPD). If the duration of the LOW pulse exceeds tT(HPD) the device will
assume that an unplug event has occurred and enter the low power state (see Figure 19). Once the
HPD_SINK input goes high again the device will return to the active state as indicated in Figure 17.
1
1
LP#
LP#
0
0
1
1
HPD_SINK
HPD_SINK
0
HPD_SRC
0
1
Z
0
HPD_SRC
1
1
DATA
Main Link
DATA
Main Link
0
HI-Z
0
Figure 18.
20
1
Z
0
Figure 19.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75DP120RHHR
ACTIVE
VQFN
RHH
36
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
DP120
SN75DP120RHHT
ACTIVE
VQFN
RHH
36
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
DP120
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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