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SN75LVDS83B
SLLS846C – MAY 2009 – REVISED AUGUST 2014
SN75LVDS83B FlatLink™ Transmitter
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
LVDS Display Series Interfaces Directly to LCD
Display Panels With Integrated LVDS
Package Options: 4.5-mm x 7-mm BGA, and 8.1mm x 14-mm TSSOP
1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
Directly to Low-Power, Low-Voltage Application
and Graphic Processors
Transfer Rate up to 135 Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10 MHz to
135 MHz
Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI
Operates From a Single 3.3-V Supply and 170
mW (Typ.) at 75 MHz
28 Data Channels Plus Clock in Low-Voltage TTL
to 4 Data Channels Plus Clock Out Low-Voltage
Differential
Consumes Less Than 1 mW When Disabled
Selectable Rising or Falling Clock Edge Triggered
Inputs
ESD: 5-kV HBM
Support Spread Spectrum Clocking (SSC)
Compatible with all OMAP™ 2x, OMAP™ 3x, and
DaVinci™ Application Processors
LCD Display Panel Driver
UMPC and Netbook PC
Digital Picture Frame
3 Description
The SN75LVDS83B FlatLink™ transmitter contains
four 7-bit parallel-load serial-out shift registers, a 7X
clock synthesizer, and five Low-Voltage Differential
Signaling (LVDS) line drivers in a single integrated
circuit. These functions allow 28 bits of single-ended
LVTTL data to be synchronously transmitted over five
balanced-pair conductors for receipt by a compatible
receiver, such as the SN75LVDS82 and LCD panels
with integrated LVDS receiver.
When transmitting, data bits D0 through D27 are
each loaded into registers upon the edge of the input
clock signal (CLKIN). The rising or falling edge of the
clock can be selected via the clock select (CLKSEL)
pin. The frequency of CLKIN is multiplied seven
times, and then used to unload the data registers in
7-bit slices and serially. The four serial streams and a
phase-locked clock (CLKOUT) are then output to
LVDS output drivers. The frequency of CLKOUT is
the same as the input clock, CLKIN.
Device Information(1)
PART NUMBER
SN75LVDS83B
PACKAGE
BODY SIZE (NOM)
TSSOP (56)
14.00 mm x 5.10 mm
BGA MICROSTAR
JUNIOR (56)
7.00 mm x 4.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
swiv
Application
processor
TM
(e.g. OMAP )
el
SN75LVDS83B
TM
FlatLink Transmitter
Package Options
TSSOP: 8 x 14mm DGG
BGA: 4.5 x 7mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVDS83B
SLLS846C – MAY 2009 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
3
6
Absolute Maximum Ratings ...................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Dissipation Ratings ................................................... 7
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 8
Switching Characteristics ........................................ 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 12
9
Detailed Description ............................................ 15
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
16
16
18
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ................................................ 19
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 30
13 Device and Documentation Support ................. 32
13.1 Trademarks ........................................................... 32
13.2 Electrostatic Discharge Caution ............................ 32
13.3 Glossary ................................................................ 32
14 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2011) to Revision C
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision A (October 2009) to Revision B
Page
•
Added Storage temperature, Ts to ABSOLUTE MAXIMUM RATINGS .................................................................................. 6
•
Added Note 3 to DISSIPATION RATINGS............................................................................................................................. 7
•
Deleted max values for Supply current (average) .................................................................................................................. 8
•
Changed Enable time units from ns to µs ............................................................................................................................ 10
•
Added Thermal Characteristics table ................................................................................................................................... 10
•
Changed G7(LSB) to G7(MSB) in Figure 15........................................................................................................................ 21
•
Added Note C to Figure 15................................................................................................................................................... 21
•
Added Note D to Figure 15................................................................................................................................................... 21
•
Added connection between GND and D23 to Figure 19 ...................................................................................................... 25
Changes from Original (May 2009) to Revision A
Page
•
Changed text and replaced TBDs in Note A and Note B of Figure 15................................................................................. 21
•
Changed Note B of Figure 16 - Replaced TBDs. ................................................................................................................. 22
•
Changed Note B of Figure 17 - Replaced TBDs. ................................................................................................................. 23
•
Changed Note C of Figure 18 - Replaced TBDs.................................................................................................................. 24
•
Changed Figure 19 - removed 3 GND pin locations. ........................................................................................................... 25
•
Changed Figure 20 - removed 3 GND pin locations. ........................................................................................................... 26
2
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SLLS846C – MAY 2009 – REVISED AUGUST 2014
5 Description (Continued)
The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the
clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all
internal registers to a low-level.
The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.
Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock
frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.
6 Pin Configuration and Functions
56-PIN
DGG PACKAGE
(TOP VIEW)
IOVCC
1
56
D5
2
3
55
54
D7
GND
D8
4
53
5
52
GND
D1
6
51
D0
D9
D10
7
50
8
49
D27
GND
VCC
D11
9
10
48
47
D12
11
46
D13
12
45
Y1P
GND
D14
13
44
14
15
43
42
LVDSVCC
GND
Y2M
16
41
17
18
40
39
19
38
D19
GND
20
37
CLKOUTP
Y3M
Y3P
21
36
GND
D20
35
34
GND
D21
22
23
D22
24
33
D23
25
32
IOVCC
D24
D25
26
31
27
30
28
29
D6
D15
D16
CLKSEL
D17
D18
D4
D3
D2
Y0M
Y0P
Y1M
Y2P
CLKOUTM
PLLVCC
GND
SHTDN
CLKIN
D26
GND
DGG Pin List
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
1
IOVCC
15
D15
29
GND
43
GND
2
D5
16
D16
30
D26
44
LVDSVCC
3
D6
17
CLKSEL
31
CLKIN
45
Y1P
4
D7
18
D17
32
SHTDN
46
Y1M
5
GND
19
D18
33
GND
47
Y0P
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DGG Pin List (continued)
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
6
D8
20
D19
34
PLLVCC
48
Y0M
7
D9
21
GND
35
GND
49
GND
8
D10
22
D20
36
GND
50
D27
9
VCC
23
D21
37
Y3P
51
D0
10
D11
24
D22
38
Y3M
52
D1
11
D12
25
D23
39
CLKOUTP
53
GND
12
D13
26
IOVCC
40
CLKOUTM
54
D2
13
GND
27
D24
41
Y2P
55
D3
14
D14
28
D25
42
Y2M
56
D4
56-PIN
ZQL PACKAGE
(TOP VIEW)
6
5
4
3
2
1
D8
D7
D5
D4
D2
D1
D9
GND
D6
D3
D0
D27
D11
VCC
D10
GND
Y0P
Y0M
D13
D12
IOVCC
GND
Y1P
Y1M
D14
GND
GND
D16
D15
Y2P
Y2M
D17
D18
CLKSEL
GND
CLKP
CLKM
D19
GND
IOVCC
GND
Y3P
Y3M
D20
D21
D25
SHTDN
PLLVCC
GND
D22
D23
D24
D26
CLKIN
GND
K
J
H
G
F
LVDSVCC
E
D
C
B
A
ZQL Pin List
4
BALL
SIGNAL
BALL
SIGNAL
BALL
SIGNAL
A1
GND
A2
CLKIN
A3
D26
A4
D24
A5
D23
A6
D22
B1
GND
B2
PLLVCC
B3
SHTDN
B4
D25
B5
D21
B6
D20
C1
Y3M
C2
Y3P
C3
GND
C4
IOVCC
C5
GND
C6
D19
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ZQL Pin List (continued)
BALL
SIGNAL
BALL
SIGNAL
BALL
SIGNAL
D1
CLKM
D2
CLKP
D3
GND
D4
CLKSEL
D5
D18
D6
D17
E1
Y2M
E2
Y2P
E3
ball not populated
E4
ball not populated
E5
D15
E6
D16
F1
LVDSVCC
F2
GND
F3
ball not populated
F4
ball not populated
F5
GND
F6
D14
G1
Y1M
G2
Y1P
G3
GND
G4
IOVCC
G5
D12
G6
D13
H1
Y0M
H2
Y0P
H3
GND
H4
D10
H5
VCC
H6
D11
J1
D27
J2
D0
J3
D3
J4
D6
J5
GND
J6
D9
K1
D1
K2
D2
K3
D4
K4
D5
K5
D7
K6
D8
Pin Functions
PIN
I/O
Y0P, Y0M, Y1P,
Y1M, Y2P, Y2M
Y3P, Y3M
DESCRIPTION
Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
LVDS Out
Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
CLKP, CLKM
Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
D0 – D27
Data inputs; supports 1.8 V to 3.3 V input voltage selectable by VDD supply. To connect a graphic
source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily
intuitive).
For input bit assignment see Figure 15 to Figure 18 for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23,
and D27 to GND.
CLKIN
CMOS IN with
pulldn
Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
SHTDN
Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and
high (assert) for normal operation.
CLKSEL
Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger
(CLKSEL = VIL).
VCC
3.3 V digital supply voltage
IOVCC
PLLVCC
I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
Power Supply (1)
3.3 V PLL analog supply
LVDSVCC
3.3 V LVDS output analog supply
GND
Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
(1)
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC (2)
–0.5
4
V
Voltage range at any output terminal
–0.5
VCC + 0.5
V
Voltage range at any input terminal
–0.5
IOVCC + 0.5
V
Continuous power dissipation
(1)
(2)
See Dissipation Ratings
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
All voltages are with respect to the GND terminals.
7.2 Handling Ratings
Tstg
Storage temperature range
MIN
MAX
–65
150
°C
5
kV
Human Body Model (HBM) (1) all pins
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Charged Device Model (CDM) (2) all pins
500
Machine Model (MM) (3) all pins
150
UNIT
V
In accordance with JEDEC Standard 22, Test Method A114-A.
In accordance with JEDEC Standard 22, Test Method C101.
In accordance with JEDEC Standard 22, Test Method A115-A.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply voltage, VCC
PARAMETER
3
3.3
3.6
LVDS output Supply voltage, LVDSVCC
3
3.3
3.6
PLL analog supply voltage, PLLVCC
3
3.3
3.6
1.62
1.8 / 2.5 / 3.3
3.6
IO input reference supply voltage, IOVCC
Power supply noise on any VCC terminal
High-level input voltage, VIH
Low-level input voltage, VIL
Differential load impedance, ZL
Operating free-air temperature, TA
6
UNIT
V
0.1
IOVCC = 1.8 V
IOVCC/2 + 0.3 V
IOVCC = 2.5 V
IOVCC/2 + 0.4 V
IOVCC = 3.3 V
IOVCC/2 + 0.5 V
V
IOVCC = 1.8 V
IOVCC/2 - 0.3 V
IOVCC = 2.5 V
IOVCC/2 - 0.4 V
IOVCC = 3.3 V
IOVCC/2 - 0.5 V
V
90
132
Ω
–10
70
C
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7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ZQL
TEST CONDITIONS
MIN
TYP
DGG
MAX
MIN
TYP MAX
UNIT
Low-K JEDEC test board, 1s (single signal layer), no air flow
85
High-K JEDEC test board, 2s2p (double signal layer, double
buried power plane), no air flow
67.1
63.4
Junction-to-case
thermal resistance
Cu cold plate measurement process
25.2
15.9
°C/W
θJB
Junction-to-board
thermal resistance
EIA/JESD 51-8
31.0
32.5
°C/W
ψJT
Junction-to-top of
package
EIA/JESD 51-2
0.8
0.4
°C/W
ψJB Junction-to-board
EIA/JESD 51-6
30.3
32.2
°C/W
θJA
Junction-to-free-air
thermal resistance
θJC
TA
Operating ambient
temperature range
TJ
Virtual junction
temperature
°C/W
–10
70
–10
70
°C
0
105
0
105
°C
7.5 Dissipation Ratings
PACKAGE
CIRCUIT BOARD MODEL (1)
DGG
Low-K
ZQL
DGG (3)
High-K
ZQL
(1)
(2)
(3)
TJA ≤ 25°C
DERATING FACTOR (2)
ABOVE TJA = 25°C
TJA = 70°C
POWER RATING
1111 mW
12.3 mW/°C
555 mW
1034 mW
11.5 mW/°C
517 mW
1730 mW
19 mW/°C
865 mW
2000 mW
22 mW/°C
1000 mW
In accordance with the High-K and Low-K thermal metric definitions of EIA/JESD51-2.
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
DGG junction to case thermal resistance (θJC) is 15.4°C/W.
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VT
Input voltage threshold
|VOD|
Differential steady-state output voltage
magnitude
TEST CONDITIONS
MIN
TYP (1)
MAX
IOVCC/2
250
UNIT
V
450
mV
RL = 100Ω, See Figure 7
Δ|VOD|
Change in the steady-state differential
output voltage magnitude between
opposite binary states
VOC(SS)
Steady-state common-mode output
voltage
VOC(PP)
Peak-to-peak common-mode output
voltage
IIH
High-level input current
VIH = IOVCC
IIL
Low-level input current
VIL = 0 V
±10
μA
VOY = 0 V
±24
mA
1
See Figure 7
tR/F (Dx, CLKin) = 1ns
1.125
35
1.375
mV
V
35
mV
25
μA
IOS
Short-circuit output current
VOD = 0 V
±12
mA
IOZ
High-impedance state output current
VO = 0 V to VCC
±20
μA
Rpdn
Input pull-down integrated resistor on all
inputs (Dx, CLKSEL, SHTDN, CLKIN)
IOVCC = 1.8 V
200
IOVCC = 3.3 V
100
IQ
Quiescent current (average)
(1)
disabled, all inputs at GND;
SHTDN = VIL
2
kΩ
100
μA
All typical values are at VCC = 3.3 V, TA = 25°C.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
SHTDN = VIH, RL = 100Ω (5 places),
grayscale pattern (Figure 8)
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
51.9
I(IOVCC) with IOVCC = 3.3 V
0.4
I(IOVCC) with IOVCC = 1.8 V
0.1
mA
SHTDN = VIH, RL = 100Ω (5 places), 50%
transition density pattern (Figure 8),
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
53.3
I(IOVCC) with IOVCC = 3.3 V
0.6
I(IOVCC) with IOVCC = 1.8 V
0.2
mA
SHTDN = VIH, RL = 100Ω (5 places), worstcase pattern (Figure 9),
VCC = 3.6 V, fCLK = 75 MHz
ICC
Supply current (average)
I(VCC) + I(PLLVCC) + I(LVDSVCC)
63.7
I(IOVCC) with IOVCC = 3.3 V
1.3
I(IOVCC) with IOVCC = 1.8 V
0.5
mA
SHTDN = VIH, RL = 100Ω (5 places), worstcase pattern (Figure 9),
fCLK = 100 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
81.6
I(IOVCC) with IOVCC = 3.6 V
1.6
I(IOVCC) with IOVCC = 1.8 V
0.6
mA
SHTDN = VIH, RL = 100Ω (5 places), worstcase pattern (Figure 9),
fCLK = 135 MHz
CI
I(VCC) + I(PLLVCC) + I(LVDSVCC)
102.2
I(IOVCC) with IOVCC = 3.6 V
2.1
I(IOVCC) with IOVCC = 1.8 V
0.8
Input capacitance
mA
2
pF
7.7 Timing Requirements
PARAMETER
Input clock period, tc
Input clock modulation
MIN
MAX
UNIT
7.4
100
ns
with modulation frequency 30 kHz
8%
with modulation frequency 50 kHz
High-level input clock pulse width duration, tw
6%
0.4 tc
Input signal transition time, tt
Data set up time, D0 through D27 before CLKIN (See Figure 6)
Data hold time, D0 through D27 after CLKIN
8
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0.6 tc
ns
3
ns
2
ns
0.8
ns
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Dn
CLKIN
or
CLKIN
CLKOUT
Previous cycle
Next
Current cycle
Y0
D0-1
D7
D6
D4
D3
D2
D1
D0
D7+1
Y1
D8-1
D18
D15
D14
D13
D12
D9
D8
D18+1
Y2
D19-1
D26
D25
D24
D22
D21
D20
D19
D26+1
Y3
D27-1
D23
D17
D16
D11
D10
D5
D27
D23+1
Figure 1. Typical SN75LVDS83B Load and Shift Sequences
LVDSVCC
IOVCC
5W
D or
SHTDN
50W
7V
YnP or
YnM
10kW
300kW
7V
Figure 2. Equivalent Input and Output Schematic Diagrams
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7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
-0.1
0
0.1
ns
UNIT
t0
Delay time, CLKOUT↑ after Yn valid
(serial bit position 0, equal D1, D9,
D20, D5)
t1
Delay time, CLKOUT↑ after Yn valid
(serial bit position 1, equal D0, D8,
D19, D27)
1
/7 tc - 0.1
1
/7 tc + 0.1
ns
t2
Delay time, CLKOUT↑ after Yn valid
(serial bit position 2, equal D7, D18,
D26. D23)
2
/7 tc - 0.1
2
/7 tc + 0.1
ns
t3
Delay time, CLKOUT↑ after Yn valid
(serial bit position 3; equal D6, D15,
D25, D17)
3
/7 tc - 0.1
3
/7 tc + 0.1
ns
t4
Delay time, CLKOUT↑ after Yn valid
(serial bit position 4, equal D4, D14,
D24, D16)
4
/7 tc - 0.1
4
/7 tc + 0.1
ns
t5
Delay time, CLKOUT↑ after Yn valid
(serial bit position 5, equal D3, D13,
D22, D11)
5
/7 tc - 0.1
5
/7 tc + 0.1
ns
t6
Delay time, CLKOUT↑ after Yn valid
(serial bit position 6, equal D2, D12,
D21, D10)
6
/7 tc - 0.1
6
/7 tc + 0.1
ns
tc(o)
Output clock period
Δtc(o)
Output clock cycle-to-cycle jitter
See Figure 10, tC = 10ns,
|Input clock jitter| < 25ps (2)
tc
(3)
tC = 10ns; clean reference clock, see
Figure 11
±26
tC = 10ns with 0.05UI added noise
modulated at 3MHz, see Figure 11
±44
tC = 7.4ns; clean reference clock,
see Figure 11
±35
tC = 7.4ns with 0.05UI added noise
modulated at 3MHz, see Figure 11
±42
ns
ps
tw
High-level output clock pulse
duration
tr/f
Differential output voltage transition
time (tr or tf)
See Figure 7
ten
Enable time, SHTDN↑ to phase lock
(Yn valid)
f(clk) = 135 MHz, See Figure 12
6
µs
tdis
Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)
f(clk) = 135 MHz, See Figure 13
7
ns
(1)
(2)
(3)
10
4
/7 tc
225
ns
500
ps
All typical values are at VCC = 3.3 V, TA = 25°C.
|Input clock jitter| is the magnitude of the change in the input clock period.
The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
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7.9 Typical Characteristics
800
Total Device Current (Using Grayscale
pattern) Over Pixel Clock Frequency
Output Jitter
90
700
80
600
Period Clock Jitter - ps-pp
ICC - Average Supply Current - mA
100
VCC = 3.6V
70
60
50
VCC = 3.3V
40
20
50
300
200
100
30
30
400
CLK Frequency During Test = 100MHz
VCC = 3V
10
Input Jitter
500
70
90
110
130
0
0.01
0.10
1
10
f(mod) - Input Modular Frequency - MHz
fclk - Clock Frequency - MHz
Figure 3. Average Grayscale ICC vs Clock Frequency
PRBS Data Signal
V - Voltage - 80mV/div
CLKL Signal
Figure 4. Output Clock Jitter vs Input Clock Jitter
Clock Signal: 135MHz
tk - Time - 1ns/div
Figure 5. Typical PRBS Output Signal Over One Clock Period
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8 Parameter Measurement Information
tsu
thold
Dn
CLKIN
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0 V.
Figure 6. Set Up and Hold Time Definition
49.9W ± 1% (2 PLCS)
YP
VOD
VOC
YM
100%
80%
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
VOC(PP)
VOC(SS)
VOC(SS)
0V
Figure 7. Test Load and Voltage Definitions for LVDS Outputs
12
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Parameter Measurement Information (continued)
CLKIN
D0,8,16
D1,9,17
D2,10,18
D3,11,19
D4-7,12-15,20-23
D24-27
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 8. 16 Grayscale Test Pattern
T
CLKIN
EVEN Dn
ODD Dn
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 9. Worst-Case Power Test Pattern
t7
CLKIN
CLKOUT
t6
t5
t4
t3
t2
t0
Yn
t1
VOD(H)
~2.5V
CLKOUT
or Yn
1.40V
CLKIN
0.00V
~0.5V
VOD(L)
t7
t0-6
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 10. SN75LVDS83B Timing Definitions
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Parameter Measurement Information (continued)
Reference
+
Device
Under
Test
VCO
+
Modulation
v(t) = A sin(2 pfmodt)
HP8656B Signal
Generator,
0.1 MHz-990 MHz
RF Output
HP8665A Synthesized
Signal Generator,
0.1 MHz-4200 MHz
Device Under
Test
RF Output
Modulation Input
CLKIN
CLKOUT
DTS2070C
Digital
TimeScope
Input
Figure 11. Output Clock Jitter Test Set Up
CLKIN
Dn
ten
SHTDN
Invalid
Yn
Valid
Figure 12. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 13. Disable Time Waveforms
14
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9 Detailed Description
9.1 Overview
FlatLink™ is an LVDS SerDes data transmission system. The SN75LVDS83B takes in three (or four) data words
each containing seven single-ended data bits and converts this to an LVDS serial output. Each serial output runs
at seven times that of the parallel data rate. The deserializer (receiver) device operates in the reverse manner.
The three (or four) LVDS serial inputs are transformed back to the original seven-bit parallel single-ended data.
FlatLink™ devices are available in 21:3 or 28:4 SerDes ratios.
• The 21-bit devices are designed for 6-bit RGB video for a total of 18 bits in addition to three extra bits for
horizontal synchronization, vertical synchronization, and data enable.
• The 28-bit devices are intended for 8-bit RGB video applications. Again, the extra four bits are for horizontal
synchronization, vertical synchronization, data enable, and the remaining is the reserved bit. These 28-bit
devices can also be used in 6-bit and 4-bit RGB applications as shown in the subsequent system diagrams.
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9.2 Functional Block Diagram
Parallel-Load 7-bit
Shift Register
D0, D1, D2, D3,
D4, D6, D7
7
Y0P
A,B,...G
SHIFT/LOAD
>CLK
Y0M
Parallel-Load 7-bit
Shift Register
D8, D9, D12, D13,
D14, D15, D18
7
Y1P
A,B,...G
SHIFT/LOAD
>CLK
Y1M
Parallel-Load 7-bit
Shift Register
D19, D20, D21, D22,
D24, D25, D26
7
Y2P
A,B,...G
SHIFT/LOAD
>CLK
Y2M
Parallel-Load 7-bit
Shift Register
D27, D5, D10, D11,
D16, D17, D23
7
Y3P
Y3M
A,B,...G
SHIFT/LOAD
>CLK
Control Logic
SHTDN
7X Clock/PLL
7XCLK
CLKIN
CLKOUTP
CLKOUTM
>CLK
CLKINH
CLKSEL
RISING/FALLING EDGE
9.3 Feature Description
9.3.1 TTL Input Data
The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video
information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The
data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the
CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN75LVDS83B and can connect directly to lowpower, low-voltage application and graphic processors. The bit mapping is listed in Table 1.
16
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Feature Description (continued)
Table 1. Pixel Bit Ordering
RED
GREEN
BLUE
R0
G0
B0
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R7
G7
B7
LSB
4-bit MSB
6-bit MSB
8-bit MSB
9.3.2 LVDS Output Data
The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts.
Table 2. Pixel Data Assignment
SERIAL
CHANNEL
Y0
Y1
Y2
Y3
CLKOUT
8-BIT
DATA BITS
6-BIT
4-BIT
NON-LINEAR STEP LINEAR STEP
SIZE
SIZE
FORMAT-1
FORMAT-2
FORMAT-3
D0
R0D27
R2
R2
R0
R2
VCC
D1
R1
R3
R3
R1
R3
GND
D2
R2
R4
R4
R2
R0
R0
D3
R3
R5
R5
R3
R1
R1
D4
R4
R6
R6
R4
R2
R2
D6
R5
R7
R7
R5
R3
R3
D7
G0
G2
G2
G0
G2
VCC
D8
G1
G3
G3
G1
G3
GND
D9
G2
G4
G4
G2
G0
G0
D12
G3
G5
G5
G3
G1
G1
D13
G4
G6
G6
G4
G2
G2
D14
G5
G7
G7
G5
G3
G3
D15
B0
B2
B2
B0
B2
VCC
D18
B1
B3
B3
B1
B3
GND
D19
B2
B4
B4
B2
B0
B0
D20
B3
B5
B5
B3
B1
B1
D21
B4
B6
B6
B4
B2
B2
D22
B5
B7
B7
B5
B3
B3
D24
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
D25
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
D26
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
D27
R6
R0
GND
GND
GND
GND
D5
R7
R1
GND
GND
GND
GND
D10
G6
G0
GND
GND
GND
GND
D11
G7
G1
GND
GND
GND
GND
D16
B6
B0
GND
GND
GND
GND
D17
B7
B1
GND
GND
GND
GND
D23
RSVD
RSVD
GND
GND
GND
GND
CLKIN
CLK
CLK
CLK
CLK
CLK
CLK
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9.4 Device Functional Modes
9.4.1 Input Clock Edge
The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the
CLKIN signal, where the rising or falling edge of the clock may be selected via CLKSEL. The selection of a clock
rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pull-up resistor to pull
CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to
GND.
9.4.2 Low Power Mode
The SN75LVDS83B can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin
SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A lowlevel on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to enable
the device for normal operation.
18
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10 Application and Implementation
10.1 Application Information
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a PCB routing example.
10.2 Typical Application
J1
U1H
GND1
GND2
GND3
GND4
GND5
GND6
GND7
PLLGND
LVDSGND1
LVDSGND2
J3
CLKM
CLKP
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
IOVCC
R4
4.7k
R5
4.7k
R6
4.7k
R7
4.7k
R8
4.7k
R9
4.7k
Y3P
Y3M
R10
4.7k
JMP1
U1B
J2
K1
K2
J3
K3
J4
K5
D0
D1
D2
D3
D4
D6
D7
D1
D2
G2
G1
J5
E1
E2
sma_surface
J6
sma_surface
C2
C1
J7
sma_surface
SN65LVDS83BZQL
J8
sma_surface
J9
sma_surface
14
Header 7x2
J10
sma_surface
IOVCC
R11
4.7k
R12
4.7k
R13
4.7k
R14
4.7k
R15
4.7k
R16
4.7k
R17
4.7k
sma_surface
JMP2
U1C
K6
J6
G5
G6
F6
E5
D5
J4
sma_surface
H2
H1
1 2
SN65LVDS83BZQL
D8
D9
D12
D13
D14
D15
D18
sma_surface
U1A
SN65LVDS83BZQL
D0
D1
D2
D3
D4
D6
D7
J2
sma_surface
C3
C5
D3
F5
G3
H3
J5
A1
B1
F2
D8
D9
D12
D13
D14
D15
D18
1 2
IOVCC
IOVCC
14
R1
4.7k
Header 7x2
SN65LVDS83BZQL
R2
IOVCC
R18
4.7k
R19
4.7k
R20
4.7k
R21
4.7k
R22
4.7k
R23
4.7k
R24
4.7k
JMP6
U1G
JMP3
U1D
D19
D20
D21
D22
D24
D25
D 26
C6
B6
B5
A6
A4
B4
A3
D19
D20
D21
D22
D24
D25
D26
SHTDN
CLKSEL
1 2
B3
D4
SHTDN
CLKSEL
1 2
3 4
Header 2x2
SN65LVDS83BZQL
14
U1J
NC1
NC2
NC3
NC4
Header 7x2
SN65LVDS83BZQL
IOVCC
R25
4.7k
R26
4.7k
R27
4.7k
R28
4.7k
R29
4.7k
R30
4.7k
E3
E4
F3
F4
SN65LVDS83BZQL
R31
4.7k
JMP4
U1E
D5
D10
D11
D16
D17
D23
D27
K4
H4
H6
E6
D6
A5
J1
D5
D10
D11
D16
D17
D23
D27
VCC
1 2
IOVCC
U1I
VCC
PLLVCC
LVDSVCC
14
IOVCC1
IOVCC2
Header 7x2
SN65LVDS83BZQL
G4
B2
F1
H5
C4
SN65LVDS83BZQL
VCC
VCC
C31
1uF
C32
0.1uF
C33
0.01uF
VCC
C34
1uF
C35
0.1uF
C36
0.01uF
IOVCC
C40
1uF
C41
0.1uF
C42
0.01uF
C37
1uF
C38
0.1uF
C39
0.01uF
PLACE UNDER LVDS83B
(bottom pcb side)
Figure 14. Schematic Example (SN75LVDS83B Evaluation Board)
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Typical Application (continued)
10.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
VCC
3.3 V
VCCIO
1.8 V
CLKIN
Falling edge
SHTDN#
High
Format
18-bit GPU to 24-bit LCD
10.2.2 Detailed Design Procedure
10.2.2.1 Power Up Sequence
The SN75LVDS83B does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN75LVDS83B SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83B shutdown to SHTDN = VIH.
5. Send >1ms of black video data; this allows the LVDS83B to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN75LVDS83B SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set SN75LVDS83B input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
10.2.2.2 Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 15 through Figure 18 show how
each signal should be connected from the graphic source through the SN75LVDS83B input, output and LVDS
LCD panel input. Detailed notes are provided with each figure.
20
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SN75LVDS83B
4.8k
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
Y0M
Y0P
Y2M
Y2P
Y3M
Y3P
100
to column
driver
100
FPC
Cable
Panel connector
Y1M
Y1P
CLKOUTM
CLKOUTP
LVDS
timing
Controller
(8bpc, 24bpp)
100
100
to row driver
100
VCC
PLLVCC
LVDSVCC
24-bpp LCD Display
GND
SHTDN
D27
D5
D0
D1
D2
D3
D4
D6
D10
D11
D7
D8
D9
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
CLKIN
CLKSEL
FORMAT2 (See Note A)
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
IOVCC
VDDGPUIO
GND
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(MSB)
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD (Note C)
CLK
FORMAT1
Main board connector
24-bpc GPU
3.3V
C2
3.3V
C3
(See Note B)
Main Board
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
•
Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
•
Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN75LVDS83B inputs must be tied to a valid logic
level.
Figure 15. 24-Bit Color Host to 24-Bit LCD Panel Application
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B0(LSB)
B1
B2
B3
B4
B5(MSB)
C1
100
FPC
Cable
Panel connector
to column
driver
CLKOUTM
CLKOUTP
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
to row driver
18-bpp LCD Display
Y3M
Y3P
4.8k
1.8V or 2.5V
or 3.3V
Y1M
Y1P
Y2M
Y2P
IOVCC
VDDGPUIO
GND
HSYNC
VSYNC
ENABLE
RSVD
CLK
100
Rpullup
(See Note A)
VCC
PLLVCC
LVDSVCC
G0(LSB)
G1
G2
G3
G4
G5(MSB)
Y0M
Y0P
Main board connector
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
GND
R0(LSB)
R1
R2
R3
R4
R5(MSB)
SHTDN
CLKSEL
18-bpp GPU
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3.3V
C2
3.3V
C3
Rpulldown
(See Note B)
Main Board
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 16. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
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12-bpp GPU
SN75LVDS83B
(See Note B)
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(See Note B)
B2 or VCC
B3 or GND
B0
B1
B2
B3(MSB)
C1
FPC
Cable
t
Panell connector
Main board connector
CLKOUTM
CLKOUTP
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
to row driver
18-bpp LCD Display
Y3M
Y3P
4.8k
1.8V or 2.5V
or 3.3V
100
Y2M
Y2P
IOVCC
VDDGPUIO
GND
HSYNC
VSYNC
ENABLE
RSVD
CLK
to column
driver
Rpullup
(See Note A)
VCC
PLLVCC
LVDSVCC
G2 or VCC
G3 or GND
G0
G1
G2
G3(MSB)
100
Y1M
Y1P
SHTDN
CLKSEL
(See Note B)
Y0M
Y0P
GND
R2 or VCC
R3 or GND
R0
R1
R2
R3(MSB)
3.3V
C2
3.3V
C3
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 N.C.
Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of
the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color
space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect
D0, D7, and D15 to VCC.
Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 17. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application
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SN75LVDS83B
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
G7(MSB)
B0 and B1: NC
(See Note B)
B2
B3
B4
B5
B6
B7(MSB)
B0 and B1: NC
(See Note B)
CLKOUTM
CLKOUTP
C1
FPC
Cable
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
to row driver
18-bpp LCD Display
Y3M
Y3P
4.8k
1.8V or 2.5V
or 3.3V
100
Y2M
Y2P
IOVCC
VDDGPUIO
GND
HSYNC
VSYNC
ENABLE
RSVD
CLK
to column
driver
Y1M
Y1P
t
Panell connector
G2
G3
G4
G5
G6
100
Main board connector
G0 and G1: NC
(See Note B)
Y0M
Y0P
SHTDN
CLKSEL
R7(MSB)
Rpullup
(See Note A)
VCC
PLLVCC
LVDSVCC
R2
R3
R4
R5
R6
GND
24-bpp GPU
R0 and R1: NC
(See Note B)
3.3V
C2
3.3V
C3
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 18. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
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10.2.2.3 PCB Routing
Figure 19 and Figure 20 show a possible breakout of the data input and output signals from the BGA package.
R1
R2
R3
R4
R5
R6
R7
R8
G0
G1
D8
D7
D5
D4
D2
D1
D9
GND
D6
D3
D0
D27
D11
VCC
D10
GND
Y0P
Y0M
D13
D12
IOVCC
GND
Y1P
Y1M
D14
GND
D16
D15
D17
D18
CLKSEL
D19
GND
IOVCC
D20
D21
D25
D22
D23
D24
G2
G3
G4
G5
G6
G7
B0
B1
LVDS GND LVDS VCC
Y2P
Y2M
GND
CLKP
CLKM
GND
Y3P
Y3M
B2
B3
B4
B5
B6
SHTDN PLLVCC LVDS GND
+PLL GND
D26
CLKIN
PLL GND
B7
HS
VS
EN
CLK
Figure 19. 24-Bit Color Routing (See Figure 15 for the Schematic)
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G1
G0
D8
D7
R5 R4 R3 R2
D5
D4
D2
R1
R0
D1
To GND
G2
G3
D9
GND
D6
D3
D0
D27
D11
VCC
D10
GND
Y0P
Y0M
D13
D12
IOVCC
GND
Y1P
Y1M
D14
GND
D16
D15
D17
D18
CLKSEL
D19
GND
IOVCC
G4
G5
B0
LVDS GND LVDS VCC
To GND
B1
Y2P
Y2M
GND
CLKP
CLKM
GND
Y3P
Y3M
B2
remains
unconnected
B3
B4
D20
D21
D22
D23
D25
SHTDN
PLLVCC LVDS GND
+PLL GND
CLKIN
B5
D24
PLL GND
D26
HS VS EN
CLK
Figure 20. 18-Bit Color Routing (See Figure 16, Figure 17, and Figure 18 for the Schematic)
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10.2.3 Application Curve
Figure 21. 18b GPU to 24b LCD
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11 Power Supply Recommendations
Power supply PLL, IO, and LVDS pins must be uncoupled from each.
12 Layout
12.1 Layout Guidelines
12.1.1 Board Stackup
There is no fundamental information about how many layers should be used and how the board stackup should
look. Again, the easiest way the get good results is to use the design from the EVMs of Texas Instruments. The
magazine Elektronik Praxis has published an article with an analysis of different board stackups. These are listed
in Table 3. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a
GND plane. Better is the use of a four-layer PCB, with a GND and a VCC plane and two signal layers. If the
circuit is complex and signals must be routed as stripline, because of propagation delay and/or characteristic
impedance, a six-layer stackup should be used.
Table 3. Possible Board Stackup on a Four-Layer PCB
MODEL 1
MODEL 2
MODEL 3
MODEL 4
Layer 1
SIG
SIG
SIG
GND
Layer 2
SIG
GND
GND
SIG
Layer 3
VCC
VCC
SIG
VCC
Layer 4
GND
SIG
VCC
SIG
Decoupling
Good
Good
Bad
Bad
Bad
EMC
Bad
Bad
Bad
Signal Integrity
Bad
Bad
Good
Bad
Self Disturbance
Satisfaction
Satisfaction
Satisfaction
High
12.1.2 Power and Ground Planes
A complete ground plane in high-speed design is essential. Additionally, a complete power plane is
recommended as well. In a complex system, several regulated voltages can be present. The best solution is for
every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers
just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In
a mixed-signal design, e.g., using data converters, the manufacturer often recommends splitting the analog
ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part. Take
care when using split ground planes because:
• Split ground planes act as slot antennas and radiate.
• A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal,
and the signal can induce noise into the nonrelated reference plane (Figure 22).
• With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the
ground plane. Always take care of the return current (Figure 23).
For Figure 23, do not route a signal referenced to digital ground over analog ground and vice versa. The return
current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal
induces noise, due to crosstalk (dotted red line) into the analog ground plane.
28
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Figure 22. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting
Figure 23. Crosstalk Induced by the Return Current Path
12.1.3 Traces, Vias, and Other PCB Components
A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the
characteristic impedance changes. This impedance change causes reflections.
• Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any
impedance change, the best routing would be a round bend (see Figure 24).
• Separate high-speed signals (e.g., clock signals) from low-speed signals and digital from analog signals;
again, placement is important.
• To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route
them with 90° to each other.
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Figure 24. Poor and Good Right Angle Bends
12.2 Layout Example
Figure 25. SN75LVDS83B EVM Top Layer – TSSOP Package
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Layout Example (continued)
Figure 26. SN75LVDS83B EVM VCC Layer – TSSOP Package
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13 Device and Documentation Support
13.1 Trademarks
OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75LVDS83BDGG
ACTIVE
TSSOP
DGG
56
35
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-10 to 70
LVDS83B
SN75LVDS83BDGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-10 to 70
LVDS83B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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