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TCA9543A
SCPS206B – MARCH 2014 – REVISED NOVEMBER 2019
TCA9543A Low Voltage 2-Channel I2C Bus Switch With Interrupt Logic And Reset
1 Features
2 Applications
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1-of-2 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Two active-low interrupt inputs
Active-low interrupt output
Active-low reset input
Two address pins allowing up to four TCA9543A
devices on the I2C bus
Channel selection via I2C bus, in any combination
Power-up with all switch channels deselected
Low RON switches
Allows voltage-level translation between
1.8-V, 2.5-V, 3.3-V, and 5-V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power-supply voltage range of 1.65-V
to 5.5-V
5.5-V Tolerant inputs
0 to 400-kHz Clock frequency
Latch-up Performance exceeds 100-mA Per
JESD78
ESD Protection exceeds JESD 22
– 4000-V Human-body model (A114-A)
– 1500-V Charged-device model (C101)
Servers
Routers (telecom switching equipment)
Factory automation
Products with I2C slave address conflicts (multiple,
identical temp sensors)
3 Description
The TCA9543A is a dual bidirectional translating
switch controlled by the I2C bus. The SCL/SDA
upstream pair fans out to two downstream pairs, or
channels. Either individual SCn/SDn channel or both
channels can be selected, determined by the
contents of the programmable control register. Two
interrupt inputs (INT1–INT0), one for each of the
downstream pairs, are provided. One interrupt output
(INT) acts as an AND of the two interrupt inputs.
An active-low reset (RESET) input allows the
TCA9543A to recover from a situation where one of
the downstream I2C buses is stuck in a low state.
Pulling RESET low resets the I2C state machine and
causes both of the channels to be deselected, as
does the internal power-on reset function.
The pass gates of the switches are constructed such
that the VCC terminal can be used to limit the
maximum high voltage, which will be passed by the
TCA9543A. This allows the use of different bus
voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V
parts can communicate with 5-V parts without any
additional protection. External pull-up resistors pull
the bus up to the desired voltage level for each
channel. All I/O terminals are 5.5-V tolerant.
Device Information(1)
PART NUMBER
TCA9543A
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
SOIC (14)
8.65 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
I2C or SMBus
Master
(e.g. Processor)
SDA
SCL
INT
VCC
Channel 0
SD0
SC0
INT0
RESET
Slaves A0, A1...AN
TCA9543A
A0
A1
GND
SD1
SC1
INT1
Channel 1
Slaves B0, B1...BN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9543A
SCPS206B – MARCH 2014 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Interrupt and Reset Timing Requirements ................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
12
12
12
14
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 20
10.1 Power-On Reset Requirements ........................... 20
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision A (February 2015) to Revision B
Page
•
Changed the Pin Configuration images appearance.............................................................................................................. 3
•
Changed VCC = 3.3 V to VCC = 2.5 V in Figure 16 .............................................................................................................. 17
Changes from Original (September 2012) to Revision A
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added D package to the datasheet. ...................................................................................................................................... 1
•
Changed Handling Ratings table to ESD Ratings .................................................................................................................. 4
•
Added D package to the Thermal Information table. ............................................................................................................. 4
2
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SCPS206B – MARCH 2014 – REVISED NOVEMBER 2019
5 Pin Configuration and Functions
D Package
SOIC 14 Pins
Top View
PW Package
TSSOP 14 Pins
Top View
A0
1
14
VCC
A1
2
13
SDA
RE SET
3
12
SCL
INT0
4
11
INT
SD0
5
10
SC1
SC0
6
9
SD1
GND
7
8
INT1
A0
1
14
VCC
A1
2
13
SDA
RE SET
3
12
SCL
INT0
4
11
INT
SD0
5
10
SC1
SC0
6
9
SD1
GND
7
8
INT1
No t to scale
No t to scale
Pin Functions
PIN
(1)
DESCRIPTION
NO.
NAME
1
A0
Address input 0. Connect directly to VCC or ground.
2
A1
Address input 1. Connect directly to VCC or ground.
3
RESET
4
INT0
Active-low interrupt input 0. Connect to VDPU0 (1) through a pull-up resistor.
5
SD0
Serial data 0. Connect to VDPU0 (1) through a pull-up resistor.
6
SC0
Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor.
7
GND
Ground
8
INT1
Active-low interrupt input 1. Connect to VDPU1 (1) through a pull-up resistor.
9
SD1
Serial data 1. Connect to VDPU1 (1) through a pull-up resistor.
10
SC1
Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor.
11
INT
Active-low interrupt output. Connect to VDPUM (1) through a pull-up resistor.
12
SCL
Serial clock line. Connect to VDPUM (1) through a pull-up resistor.
13
SDA
Serial data line. Connect to VDPUM (1) through a pull-up resistor.
14
VCC
Supply power
Active-low reset input. Connect to VCC or VDPUM (1) through a pull-up resistor, if not used.
VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0 and VDPU1 are
the slave channel reference voltages.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
UNIT
Supply voltage range
–0.5
7
V
(2)
–0.5
VI
Input voltage range
7
V
II
Input current
±20
mA
IO
Output current
±25
mA
Continuous current through VCC
±100
mA
Continuous current through GND
±100
mA
Ptot
Total power dissipation
400
mW
TA
Operating free-air temperature range
–40
85
°C
Tstg
Storage temperature range
–60
150
°C
(1)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
1.65
5.5
SCL, SDA
0.7 × VCC
6
A1, A0, INT1, INT0, RESET
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A1, A0, INT1, INT0, RESET
–0.5
0.3 × VCC
–40
85
UNIT
V
V
V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
TCA9543A
THERMAL METRIC
(1)
PW
D
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
130.9
102.8
RθJCtop
Junction-to-case (top) thermal resistance
59.2
63.9
RθJB
Junction-to-board thermal resistance
72.7
57.1
ψJT
Junction-to-top characterization parameter
10.5
26.7
ψJB
Junction-to-board characterization parameter
72.1
56.8
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCPS206B – MARCH 2014 – REVISED NOVEMBER 2019
6.5 Electrical Characteristics (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VPORR
Power-on reset voltage,
VCC rising
No load: VI = VCC or GND (3)
VPORF
Power-on reset voltage,
VCC falling (4)
No load: VI = VCC or GND (3)
VCC
MIN TYP (2)
MAX
1.2
1.5
0.8
5V
2.6
3.3 V
Switch output voltage
1.0
II
VOL = 0.6 V
1.1
1.65 V to 5.5 V
10
3
7
6
10
SCL, SDA
VI = VCC or GND (3)
1.65 V to 5.5 V
–1
1
SC1–SC0, SD1–SD0
VI = VCC or GND
(3)
1.65 V to 5.5 V
–1
1
A1, A0
VI = VCC or GND (3)
1.65 V to 5.5 V
–1
1
INT1–INT0
VI = VCC or GND (3)
1.65 V to 5.5 V
–1
1
RESET
VI = VCC or GND (3)
1.65 V to 5.5 V
–1
1
fSCL = 100
kHz
3
VI = VCC or GND (3)
IO = 0
tr,max = 300 ns
VI = VCC or GND (3)
IO = 0
tr,max = 1 µs
ICC
Low inputs
VI = GND (3)
IO = 0
Standby
mode
High inputs
INT1–INT0
Supplycurrent
change
SCL, SDA
μA
mA
VOL = 0.4 V
Operating
mode
(1)
(2)
(3)
(4)
0.5
INT
fSCL = 400
kHz
ΔICC
1.8
1.65 V to 5.5 V
VOL = 0.4 V
SDA
IOL
V
0.8
1.65 V to 1.95 V
VO = VCC
2.8
1.4
1.8 V
INT
4.5
1.6
2.5 V
2.3 V to 2.7 V
IOH
V
1.9
3 V to 3.6 V
VSWin = VCC,
ISWout = –100 μA
V
3.6
4.5 V to 5.5 V
Vpass
1
UNIT
VI = VCC
IO = 0
5.5 V
50
3.6 V
20
2.7 V
11
1.65 V
6
5.5 V
35
3.6 V
14
2.7 V
5
1.65 V
2
5.5 V
1.6
2
3.6 V
1.0
1.3
2.7 V
0.7
1.1
1.65 V
0.4
0.55
5.5 V
1.6
2
3.6 V
1.0
1.3
2.7 V
0.7
1.1
1.65 V
0.4
0.55
3
20
3
20
2
15
2
15
One INT1–INT0 input at 0.6 V,
Other inputs at VCC or GND (3)
One INT1–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND (3)
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND (3)
1.65 V to 5.5 V
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND (3)
μA
μA
μA
For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
RESET = VCC (held high) when all other input voltages, VI = GND
The power-on reset circuit resets the I2C bus logic when VCC < VPORF.
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Electrical Characteristics(1) (continued)
over recommended operating free-air temperature range (unless otherwise noted)
MIN TYP (2)
MAX
1.65 V to 5.5 V
4.5
6
1.65 V to 5.5 V
4.5
6
VI = VCC or GND (3)
1.65 V to 5.5 V
4.5
5.5
VI = VCC or GND (3), Switch OFF
1.65 V to 5.5 V
15
19
6
8
PARAMETER
Ci
TEST CONDITIONS
A1, A0
VI = VCC or GND
(3)
INT1–INT0
VI = VCC or GND (3)
RESET
SCL, SDA
Cio(OFF) (5)
SC1–SC0, SD1–SD0
VCC
VO = 0.4 V, IO = 15 mA
RON
Switch on-state resistance
VO = 0.4 V, IO = 10 mA
(5)
4.5 V to 5.5 V
4
10
16
3 V to 3.6 V
5
13
20
2.3 V to 2.7 V
7
16
45
1.65 V to 1.95 V
10
25
70
UNIT
pF
pF
Ω
Cio(ON) depends on the device capacitance and load that is downstream from the device.
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
MIN
MAX
100
UNIT
MIN
MAX
0
400
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
μs
tscl
I2C clock low time
4.7
1.3
μs
2
tsp
I C spike time
tsds
I2C serial-data setup time
250
50
100
tsdh
I2C serial-data hold time
0 (1)
0 (1)
ticr
I2C input rise time
2
ticf
I C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between stop and start
10-pF to 400-pF bus
2
50
kHz
ns
ns
μs
1000
20 + 0.1Cb (2)
300
ns
300
20 + 0.1Cb
(2)
300
ns
300
20 + 0.1Cb (2)
300
ns
4.7
1.3
μs
tsts
I C start or repeated start condition setup
4.7
0.6
μs
tsth
I2C start or repeated start condition hold
4
0.6
μs
tsps
I2C stop condition setup
4
0.6
μs
tvdL(Data) Valid-data time (high to low)
(3)
SCL low to SDA output low valid
tvdH(Data) Valid-data time (low to high) (3)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
Cb
I2C bus capacitive load
(1)
(2)
(3)
6
1
1
μs
0.6
0.6
μs
1
1
μs
400
400
pF
A device internally must provide a hold time of at least 300-ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF
Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)
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6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7)
PARAMETER
tpd (1)
Propagation delay time
tiv
Interrupt valid time (2)
tir
Interrupt reset delay time
(1)
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
(2)
FROM
(INPUT)
TO
(OUTPUT)
SDA or SCL
SDn or SCn
INTn
INT
4
μs
INTn
INT
2
μs
MIN
MAX
0.3
1
UNIT
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 7)
(2)
6.8 Interrupt and Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7)
PARAMETER
MIN
(1)
tPWRL
Required low-level pulse duration of INTn inputs
tPWRH
Required high-level pulse duration of INTn inputs (1)
tWL
Pulse duration, RESET low
trst
(2)
tREC
(1)
(2)
MAX
1
μs
0.5
μs
4
ns
RESET time (SDA clear)
500
Recovery time from RESET to start
UNIT
0
ns
ns
The device has interrupt input rejection circuitry for pulses less than the listed minimum.
trst is the propagation delay measured from the time the RESET terminal is first asserted low to the time the SDA terminal is asserted
high, signaling a stop condition. It must be a minimum of tWL.
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6.9 Typical Characteristics
800
1.8
VCC = 5.5V
VCC = 3.3V
VCC = 1.65V
1.6
ICC, Standby Mode (µA)
700
VOL (mV)
600
500
400
300
200
1.2
1
0.8
0.6
25ºC (Room Temperature)
85ºC
-40ºC
0.4
100
0.2
1.5
0
0
2
4
IOL
6
(mA)
8
10
12
2
2.5
3
D003
Figure 1. SDA Output Low Voltage (VOL) vs Load Current
(IOL) at Three VCC Levels
4
4.5
5
5.5
D004
30
25ºC (Room Temperature)
85ºC
-40º
5.6
25
5.4
RON (Ohm)
20
5.2
5
4.8
15
10
4.6
4.4
25ºC (Room Temperature)
85ºC
-40ºC
5
4.2
0
4
0
0.5
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
0
0.5
D001
Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs.
Supply Voltage (VCC) at Three Temperature Points
8
3.5
VCC (V)
Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
Three Temperature Points
6
5.8
Cio(OFF) (pF)
1.4
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
D001
Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at
Three Temperatures
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
SDn, SCn
DUT
CL = 50 pF
(See Note A)
I2C PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Start
Address
Stop
Address
Bit 7
Condition Condition
Bit 6
(S)
(MSB)
(P)
BYTE
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
ACK
(A)
Stop
Condition
(P)
DESCRIPTION
I2C
1
2
address + R/W
Control register data
tscl
tsch
0.7 × VCC
SCL
tvd(ACK)
or tvdL
tvdH
ticr
ticf
tbuf
tsp
0.3 × VCC
tsts
0.7 × VCC
SDA
0.3 × VCC
ticr
ticf
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
Stop
Condition
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
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Parameter Measurement Information (continued)
Figure 6. Reset Timing
VCC
RL = 4.7 kΩ
DUT
INT
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
INTn
(input)
0.5 × VCC
INTn
(input)
tir
tiv
INT
(output)
0.5 × VCC
0.5 × VCC
INT
(output)
VOLTAGE WAVEFORMS (tiv)
0.5 × VCC
VOLTAGE WAVEFORMS (tir)
A.
CL includes probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
Figure 7. Interrupt Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The TCA9543A is a 2-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to
two channels of slave devices, SC0/SD0-SC1/SD1. Either individual downstream channel can be selected as
well as both channels. The TCA9543A also supports interrupt signals in order for the master to detect an
interrupt on the INT output terminal that can result from any of the slave devices connected to the INT1-INT0
input terminals.
The device offers an active-low RESET input which resets the state machine and allows the TCA9543A to
recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Either using the RESET
function or causing a POR will cause both channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 terminals), a single 8-bit control register is written to or read from to determine the
selected channels and state of the interrupts.
The TCA9543A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
8.2 Functional Block Diagram
SC0
6
TCA9543A
10
SC1
5
SD0
9
SD1
GND
VCC
RESET
SCL
7
Switch Control Logic
14
3
Power-On
Reset
12
1
Input Filter
SDA
13
INT0 4
8
INT1
I2C Bus
Control
Interrupt Logic
2
Output Filter
11
A0
A1
INT
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8.3 Feature Description
The TCA9543A is a dual channel bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9543A features I2C control using a single 8-bit control register
in which bits 1 and 0 control the enabling and disabling of the two switch channels of I2C data flow. The
TCA9543A also supports interrupt signals for each slave channel and this data is held in bits 5 and 4 of the
control register. Depending on the application, voltage translation of the I2C bus can also be achieved using the
TCA9543A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that
communication on the I2C bus enters a fault state, the TCA9543A can be reset to resume normal operation using
the RESET terminal feature or by a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1
RESET Input
The RESET input can be used to recover the TCA9543A from a bus-fault condition. The registers and the I2C
state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL.
Both channels also are deselected in this case. RESET must be connected to VCC through a pull-up resistor.
8.4.2 Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TCA9543A in a reset condition until VCC has
reached VPORR. At this point, the reset condition is released and the TCA9543A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below VPORF to reset the device.
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time is interpreted as control signals (see Figure 8).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of data
allowed
Figure 8. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 9).
SDA
SDA
SCL
SCL
S
P
STOP Condition
START Condition
Figure 9. Definition of Start and Stop Conditions
12
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Programming (continued)
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master and the devices that are controlled by the master are the slaves (see
Figure 10).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Slave
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
2
I C-Bus
Multiplexer
Slave
Figure 10. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 11). Setup and hold times must be taken
into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 11. Acknowledgment on I2C Bus
Data is transmitted to the TCA9543A control register using the write mode shown in Figure 12.
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Programming (continued)
Control Register
Slave Address
SDA
S
1
1
1
0
0
A1
A0
Start
Condition
0
A
X
X
X
X
X
X
R/W Acknowledge
From Slave
B1
B0
A
P
Acknowledge
From Slave
Stop
Condition
Figure 12. Write Control Register
Data is read from the TCA9543A control register using the read mode shown in Figure 13.
Last Byte
Control Register
Slave Address
SDA
S
1
1
1
0
0
A1
A0
Start
Condition
1
A
X
X
INT1 INT0
X
R/W Acknowledge
From Slave
X
B1
B0 NA
P
No Acknowledge
From Master
Stop
Condition
Figure 13. Read Control Register
8.6 Register Maps
8.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9543A is shown in Figure 14. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address terminals and they must be pulled high or low.
1
1
1
Fixed
0
0
A1
A0 R/W
Hardware
selectable
Figure 14. Slave Address TCA9543A
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
8.6.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9543A,
which is stored in the control register (see Figure 15). If multiple bytes are received by the TCA9543A, it saves
the last byte received. This register can be written and read via the I2C bus.
14
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Register Maps (continued)
Channel Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
X
X
5
4
INT1 INT0
3
2
1
0
X
X
B1
B0
Channel 0
Channel 1
INT0
INT1
Figure 15. Control Register
8.6.3 Control Register Definition
One or both SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). After the TCA9543A has been addressed, the control register is written. The two LSBs of the control
byte are used to determine which channel or channels are to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition must occur always right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1)
D7
X
(1)
D6
X
INT1
X
INT0
X
D3
X
D2
X
X
X
X
X
X
X
0
0
0
0
0
0
B1
X
0
1
0
B0
COMMAND
0
Channel 0 disabled
1
X
0
Channel 0 enabled
Channel 1 disabled
Channel 1 enabled
No channel selected; power-up/reset default state
Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance.
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8.6.4 Interrupt Handling
The TCA9543A provides two interrupt inputs (one for each channel) and one open-drain interrupt output (see
Table 2). When an interrupt is generated by any device, it is detected by the TCA9543A and the interrupt output
is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control
register.
Bit 4 and Bit 5 of the control register correspond to the INT0 and INT1 inputs of the TCA9543A, respectively.
Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master then can address the
TCA9543A and read the contents of the control register to determine which channel contains the device
generating the interrupt. The master then can reconfigure the TCA9543A to select this channel, and locate the
device generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC through a pull-up resistor.
Table 2. Control Register Read (Interrupt) (1)
D7
X
(1)
16
D6
X
X
X
0
0
INT1
X
0
1
0
INT0
0
1
D3
X
D2
X
B1
X
B0
X
X
X
X
X
X
0
0
0
0
0
COMMAND
No interrupt on channel 0
Interrupt on channel 0
No interrupt on channel 1
Interrupt on channel 1
No channel selected; power-up/reset default state
Two interrupts can be active at the same time.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9543A will contain an I2C (or SMBus) master device and up to two I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if two identical digital
temperature sensors are needed in the application, one sensor can be connected at each channel: 0 and 1.
When the temperature at a specific location needs to be read, the appropriate channel can be enabled and the
other channel switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across both channels. If both switches will be enabled simultaneously, additional design
requirements must be considered (See Design Requirements and Detailed Design Procedure).
9.2 Typical Application
A typical application of the TCA9543A contains anywhere from 1 to 3 separate data pull-up voltages, VDPUX , one
for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 and VDPU1). In the event
where the master device and both slave devices operate at the same voltage, then the pass voltage, Vpass =
VDPUX. Once the maximum Vpass is known, Vcc can be selected easily using Figure 17. In an application where
voltage translation is necessary, additional design requirements must be considered (See Design Requirements).
Figure 16 shows an application in which the TCA9543A can be used.
VDPUM = 1.65 V to 5.5 V
VCC = 2.5 V
VDPU0 = 1.65 V to 5.5 V
VCC
13
SDA
12
SCL
11
SDA
SCL
SD0
INT
INT0
5
6
Channel 0
SC0
4
2
I C/SMBus
Master
3
RESET
2
1
7
TCA9543A
VDPU1 = 1.65 V to 5.5 V
A1
SD1
A0
GND
SC1
9
10
8
Channel 1
INT1
Figure 16. Typical Application Schematic
9.2.1 Design Requirements
The pull-up resistors on the INT1-INT0 terminals in the application schematic are not required in all applications.
If the device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is
required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up
resistor is not required. The interrupt inputs should not be left floating in the application.
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Typical Application (continued)
The A0 and A1 terminals are hardware selectable to control the slave address of the TCA9543A. These
terminals may be tied directly to GND or VCC in the application.
If both slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to GND
on the master side will be the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9543A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 17 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9543A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 17, Vpass(max) is 2.7 V when the TCA9543A
supply voltage is 4 V or lower, so the TCA9543A supply voltage could be set to 3.3 V. Pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 16).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL:
VDPUX - VOL(max)
Rp(min) =
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9543A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If both channels will
be activated simultaneously, each of the slaves on both channels will contribute to total bus capacitance.
18
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Typical Application (continued)
9.2.3 Application Curves
25
5
20
Rp(max) (kOhm)
4
Vpass (V)
Standard-mode
Fast-mode
25ºC (Room Temperature)
85ºC
-40ºC
3
2
15
10
5
1
0
0
0
0.5
Space
spacespace
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
0
5.5
50
100
150
200
250
Cb (pF)
D007
Space
spacespace
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
Figure 17. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
300
350
400
450
D008
Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 18. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
1.8
1.6
Rp(min) (kOhm)
1.4
1.2
1
0.8
0.6
0.4
VDPUX > 2V
VDPUX 2 V
Figure 19. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX)
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10 Power Supply Recommendations
The operating power-supply voltage range of the TCA9543A is 1.65-V to 5.5-V applied at the VCC terminal.
When the TCA9543A is powered on for the first time or anytime the device needs to be reset by cycling the
power supply, the power-on reset requirements must be followed to ensure the I2C bus logic is initialized
properly.
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9543A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 20.
VCC
Ramp-Up
Ramp-Down
VCC_TRR
VCC drops below VPORF – 50 mV
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 20. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 3 specifies the performance of the power-on reset feature for TCA9543A for both types of power-on reset.
Table 3. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MIN
TYP
MAX
UNIT
VCC_FT
Fall time
See Figure 20
1
100
ms
VCC_RT
Rise time
See Figure 20
0.1
100
ms
VCC_TRR
Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
when VCC drops to GND)
See Figure 20
40
VCC_GH
Level that VCC can glitch down to, but not cause a functional
disruption when VCC_GW = 1 μs
See Figure 21
1.2
V
VCC_GW
Glitch width that will not cause a functional disruption when
VCC_GH = 0.5 × VCC
See Figure 21
10
μs
VPORF
Voltage trip point of POR on falling VCC
See Figure 22
0.8
1.25
V
VPORR
Voltage trip point of POR on rising VCC
See Figure 22
1.05
1.5
V
(1)
20
μs
All supply sequencing and ramp rate values are measured at TA = 25°C
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 21 and Table 3 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 21. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 22 and Table 3 provide more details on this specification.
VCC
VPORR
VPORF
Time
POR
Time
Figure 22. VPOR
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA9543A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that
are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon
pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the
VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and
a smaller capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane can connect all of the pull-up resistors to the appropriate reference voltage.
In an application where voltage translation is required, VDPUM, VDPU0, and VDPU1, may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a
short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper
weight).
11.2 Layout Example
LEGEND
Partial Power Plane
Polygonal
Copper Pour
To I2C Master
VIA to Power Plane
VIA to GND Plane (Inner Layer)
By-pass/De-coupling
capacitors
VDPUM
A0
VCC
A1
SDA
RESET
INT0
SD0
SC0
TCA9543A
VDPU0
VCC
GND
SCL
INT
SC1
SD1
VDPU1
To Slave Channel 1
To Slave Channel 0
GND
INT1
GND
Figure 23. Layout Example
22
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TCA9543ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TCA9543A
TCA9543APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PW543A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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