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TLV8544, TLV8542, TLV8541
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
TLV854x 500-nA, RRIO, Nanopower Operational Amplifiers for Cost-Optimized Systems
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TLV854x ultra-low-power operational amplifiers
(op amps) are intended for cost-optimized sensing
applications in wireless and low-power wired
equipment. The TLV854x family of op amps minimize
power consumption in equipment such as motion
detecting security systems (like microwave and PIR
motion sensing) where operational battery life is
critical. They also have a carefully designed CMOS
input stage, enabling very low, femto-ampere bias
currents, thereby reducing IBIAS and IOS errors that
would otherwise impact sensitive applications.
Examples of these include transimpedance amplifier
(TIA) configurations with megaohm feedback
resistors, and high source impedance sensing
applications. Additionally, built-in EMI protection
reduces sensitivity to unwanted RF signals from
sources such as mobile phones, WiFi, radio
transmitters and tab readers.
1
•
For Cost-Optimized Systems
Nanopower Supply Current: 500 nA per Channel
Offset Voltage: 3.1 mV (maximum)
TcVos: 0.8 µV/°C
Gain Bandwidth: 8 kHz
Unity-Gain Stable
Low Input-Bias Current: 100 fA
Wide Supply Range: 1.7 V to 3.6 V
Rail-to-Rail Input and Output (RRIO)
Temperature Range –40°C to +125°C
Industry Standard Package
– Quad in 14-pin TSSOP and SOIC
– Dual in 8-pin SOIC
– Single in 5-pin SOT-23
Leadless Package
– Dual in 8-Pin X2QFN
2 Applications
•
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
TLV8544
Motion Detectors Using PIR Sensors SNAA301
Motion Detectors Using Microwave Sensors
Gas Detectors
Ionization Smoke Alarms
Thermostats
Remote Sensors, IoT (Internet of Things)
Active RFID Readers and Tags
Portable Medical Equipment
Glucose Monitoring
TLV8542
TLV8541
PACKAGE
BODY SIZE
TSSOP (14)
5.00 mm × 4.40 mm
SOIC (14)
8.65 mm × 3.91 mm
SOIC (8)
4.9 mm × 3.90 mm
X2QFN (8)
1.50 mm × 1.50 mm
SOT-23 (5)
2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Nanopower Amplifiers Family
FAMILY
CHANNEL
COUNT
IQ PER
CHANNEL
VOS
(MAXIMUM)
VSUPPLY
TLV854x
1, 2, 4
500 nA
3.1 mV
1.7 to 3.6 V
TLV880x
1, 2
320 nA
4.5 mV
1.7 to 5.5 V
LPV81x
1, 2
425 nA
0.3 mV
1.6 to 5.5 V
Low Power PIR Motion Detector
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV8544, TLV8542, TLV8541
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
7
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application: Battery-Powered Wireless PIR
Motion Detectors ...................................................... 15
9.3 Typical Application: 60-Hz Twin T Notch Filter ....... 19
9.4 Dos and Don'ts ....................................................... 20
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision D (November 2017) to Revision E
Page
•
Released TLV8542 X2QFN package as production data ...................................................................................................... 1
•
Released TLV8544 SOIC package as production data ........................................................................................................ 1
Changes from Revision C (October 2017) to Revision D
Page
•
Production Data Release of TLV8541 ................................................................................................................................... 1
•
Added 8-pin X2QFN package for the TLV8542...................................................................................................................... 1
Changes from Revision B (June 2017) to Revision C
•
Page
Changed TLV8542 dual datasheet to production data........................................................................................................... 1
Changes from Revision A (March 2017) to Revision B
•
Page
Added Advance Information TLV8542 to the TLV8544 Data Sheet ...................................................................................... 1
Changes from Original (December 2016) to Revision A
•
Page
Changed Product Preview to Production Data release. ........................................................................................................ 1
5 Description (continued)
The TLV854x op amps operates with a single supply voltage down to 1.7 V supply, providing continuous
performance in low battery situations over the extended temperature range of –40°C to +125°C. All versions are
specified for operation from –40°C to 125°C. The TLV8541 (single version) is available in the 5-pin SOT-23 while
the TLV8542 (dual version) is available in the 8-pin SOIC package. The 4-channel TLV8544 (quad version) is
available in the industry standard 14-pin TSSOP package.
2
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
TLV8544, TLV8542, TLV8541
www.ti.com
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
6 Pin Configuration and Functions
TLV8541 DBV Package
5-Pin SOT-23
Top View
Pin Functions: TLV8541 DBV
PIN
I/O
DESCRIPTION
NUMBER
NAME
1
OUT
O
Output
2
V–
P
Negative (lowest) power supply
3
+IN
I
Non-Inverting Input
4
–IN
I
Inverting Input
5
V+
P
Positive (highest) power supply
TLV8542 D Package
8-Pin SOIC
Top View
TLV8542 RUG Package
8-Pin X2QFN
Top View
OUT A
1
-IN A
+IN A
8
V+
OUT B
2
6
-IN B
3
5
+IN B
4
7
V-
Pin Functions: TLV8542 D & RUG
PIN
I/O
DESCRIPTION
NUMBER
NAME
1
OUT A
O
Channel A Output
2
–IN A
I
Channel A Inverting Input
3
+IN A
I
Channel A Non-Inverting Input
4
V–
P
Negative (lowest) power supply
5
+IN B
I
Channel B Non-Inverting Input
6
–IN B
I
Channel B Inverting Input
7
OUT B
O
Channel B Output
8
V+
P
Positive (highest) power supply
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
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TLV8544, TLV8542, TLV8541
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
www.ti.com
TLV8544 PW and D Package
14-Pin TSSOP and SOIC
Top View
Pin Functions: TLV8544 PW & D
PIN
I/O
DESCRIPTION
NUMBER
NAME
1
OUTA
O
Channel A output
2
–INA
I
Channel A inverting input
3
+INA
I
Channel A non-inverting input
4
V+
P
Positive (highest) power supply
5
+INB
I
Channel B non-inverting input
6
–INB
I
Channel B inverting input
7
OUTB
O
Channel B output
8
OUTC
O
Channel C output
9
–INC
I
Channel C inverting input
10
+INC
I
Channel C non-inverting input
11
V–
P
Negative (lowest) power supply
12
+IND
I
Channel D non-inverting input
13
–IND
I
Channel D inverting input
14
OUTD
O
Channel D output
4
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
TLV8544, TLV8542, TLV8541
www.ti.com
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
UNIT
–0.3
4
V
Common mode
(V–) – 0.3
(V+) + 0.3
V
Differential
(V–) – 0.3
(V+) + 0.3
V
–10
10
mA
Supply voltage, Vs = (V+) – (V–)
Input pins
Voltage
Input pins
Current
Output short current (4)
Continuous
Continuous
Operating ambient temperature
–40
125
°C
Storage temperature, Tstg
–65
150
°C
150
°C
Junction temperature
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Short-circuit to ground.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage (V+ – V–)
1.7
3.6
V
Specified ambient temperature
–40
125
°C
7.4 Thermal Information
TLV8544
THERMAL METRIC (1)
TLV8542
TLV8541
PW
(TSSOP)
D
(SOIC)
D
(SOIC)
RUG
(X2QFN)
DBV
(SOT-23)
14 PINS
14 PINS
8 PINS
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
124.5
104.1
141.6
188.3
244.6
°C/W
RθJC(to
Junction-to-case (top) thermal resistance
52.7
61.5
85.7
88.9
127.3
°C/W
RθJB
Junction-to-board thermal resistance
66.2
59.9
84.7
100.2
79.4
°C/W
ψJT
Junction-to-top characterization parameter
7.3
22.9
36.3
3.9
44.1
°C/W
ψJB
Junction-to-board characterization parameter
65.7
59.5
84.0
100.3
78.8
°C/W
RθJC(b
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
N/A
°C/W
p)
ot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
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TLV8544, TLV8542, TLV8541
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
www.ti.com
7.5 Electrical Characteristics
TA = 25°C, VS = 1.8 V to 3.3 V, VCM = VOUT = VS / 2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCM = V– , VS = 1.8 V and 3.3 V
–3.1
See Plots
3.1
VCM = V+, VS = 1.8 V and 3.3 V
–3.4
See Plots
3.4
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset drift
VCM = V–, TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
VCM = V– , VS =1.8 V and 3.3 V
66
mV
0.8
µV/°C
90
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
VS = 3.3 V
0
(V–) ≤ VCM ≤ (V+), Vs = 3.3 V
60
(V–) ≤ VCM ≤ (V+) – 1.2 V
3.3
80
V
dB
90
INPUT BIAS CURRENT
IB
Input bias current
100
fA
IOS
Input offset current
100
fA
Differential
2
pF
Common mode
4
pF
INPUT IMPEDANCE
NOISE
En
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
8.6
µVp–p
en
Input voltage noise density
ƒ = 1 kHz
264
nV/√Hz
Open-loop voltage gain
(V–) + 0.3 V ≤ VO ≤ (V+) – 0.3 V, RL =
100 kΩ to V+/2
120
dB
VOH
Voltage output swing from
positive rail
RL = 100 kΩ to V+/2, VS = 3.3 V
12
mV
VOL
Voltage output swing from
negative rail
RL = 100 kΩ to V+/2, VS = 3.3 V
12
mV
OPEN-LOOP GAIN
AOL
OUTPUT
ISC
Short-circuit current
ZO
Open loop output impedance
Sourcing, VO to V–, VIN(diff) = 100 mV,
VS = 3.3 V
15
Sinking, VO to V+, VIN(diff) = –100 mV,
VS = 3.3 V
30
mA
ƒ = 1 kHz, IO = 0 mA
8
kΩ
8
kHz
FREQUENCY RESPONSE
GBP
Gain-bandwidth product
SR
CL = 20 pF, RL = 10 MΩ
Slew rate (10% to 90%)
G = 1, rising edge, CL = 20 pF
3.5
G = 1, falling edge, CL = 20 pF
4.5
V/ms
POWER SUPPLY
IQ–TLV8541
Quiescent Current
VCM = V–, IO = 0 mA, VS = 3.3 V
550
640
nA
IQ–TLV8542
Quiescent Current, per channel
VCM = V–, IO = 0 mA, VS = 3.3 V
550
640
nA
IQ–TLV8544
Quiescent current, per channel
VCM = V–, IO = 0 mA, VS = 3.3 V
500
640
nA
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SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
7.6 Typical Characteristics
10
8
9
Percentage of Amplifiers (%)
9
6
5
4
3
2
8
7
6
5
4
3
2
1
1
0
0
VOS_
-1600
-1400
-1200
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1200
1400
1600
7
-1600
-1400
-1200
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1200
1400
1600
Percentage of Amplifiers (%)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
VOS_
Offset Voltage (µV)
VS = 1.8 V
VCM = V+
Offset Voltage (µV)
Data from 1500 4-channel devices
VS = 1.8 V
Figure 1. Offset Voltage Production Distribution
VCM = V–
Data from 1500 4-channel devices
Figure 2. Offset Voltage Production Distribution
10
8
Percentage of Amplifiers (%)
6
5
4
3
2
8
7
6
5
4
3
2
1
1
0
-1600
-1400
-1200
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1200
1400
1600
0
VOS_
-1600
-1400
-1200
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1200
1400
1600
Percentage of Amplifiers (%)
9
7
VOS_
Offset Voltage (µV)
VS = 3.3 V
VCM = V+
Offset Voltage (µV)
Data from 1500 4-channel devices
VS = 3.3 V
800
720
720
640
560
480
400
320
240
160
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
80
0
Data from 1500 4-channel devices
Figure 4. Offset Voltage Production Distribution
800
Quiecent Current per Channel (nA)
Quiecent Current per Channel (nA)
Figure 3. Offset Voltage Production Distribution
VCM = V–
640
560
480
400
320
240
160
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
80
0
0
0.2
0.4
VS = 1.8 V
0.6
0.8
1
1.2
1.4
Common Mode Voltage (V)
TA = –40, 25, 125°C
1.6
1.8
0
0.3
0.6
SNOS
Per Channel
Figure 5. Supply Current vs Common Mode Voltage
0.9 1.2 1.5 1.8 2.1 2.4
Common Mode Voltage (V)
VS = 3.3 V
TA = –40, 25, 125°C
2.7
3
3.3
SNOS
Per Channel
Figure 6. Supply Current vs Common Mode Voltage
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Typical Characteristics (continued)
50
50
0
0
Input Offset Voltage (PV)
Input Offset Voltage (PV)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
-50
-100
-150
-200
-250
Vos (PV) at 125 qC
Vos (PV) at 25 qC
Vos (PV) at -40 qC
-300
-350
-0.5 -0.25
0
0.25 0.5 0.75 1 1.25
Common Mode Voltage (V)
VS = 1.8 V
1.5
1.75
-100
-150
-200
-250
-350
-0.5
2
0
0.5
Vos-
TA = –40, 25, 125°C
VS = 3.3 V
1
1.5
2
2.5
Common Mode Voltage (V)
3
3.5
Vos-
TA = –40, 25, 125°C
Figure 8. Typical Offset Voltage vs Common Mode Voltage
120
100
CMRR (dB)
Supply Current per Channel (nA)
-50
-300
Figure 7. Typical Offset Voltage vs Common Mode Voltage
625
600
575
550
525
500
475
450
425
400
375
350
325
300
1.6
Vos (PV) at 125 qC
Vos (PV) at 25 qC
Vos (PV) at -40 qC
80
60
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
1.8
2
2.2
VS = 1.6 to 3.6V
2.4 2.6 2.8
3
Supply Voltage (V)
3.2
3.4
40
10
3.6
100
TA = –40, 25, 125°C
1k
10k
Frequency (Hz)
SNOS
VCM = V-
VS= 3.3V
Figure 9. Supply Current vs Supply Voltage, Low VCM
SNOS
TA = 25°C
Figure 10. CMRR vs Frequency
135
1
Output Swing from V- (V)
PSRR (dB)
120
105
90
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
75
100P
60
10
100
VS= 3.3V
1k
Frequency (Hz)
10k
PSRR
TA = 25°C
Figure 11. PSRR vs Frequency
8
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100k
VCM = V–
10m
100m
1
Output Sinking Current (mA)
VS = 1.8 V
10
SNOS
TA = –40, 25, 125°C
Figure 12. Output Swing vs Sinking Current
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
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SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
Typical Characteristics (continued)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
1
Output Swing from V+ (V)
Output Swing from V- (V)
1
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100P
100m
VS = 3.3 V
1
Output Sinking Current (mA)
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100P
1m
10
10m
100m
1
Output Sourcing Current (mA)
SNOS
TA = –40, 25, 125°C
VS = 1.8 V
Figure 13. Output Swing vs Sinking Current
10
SNOS
TA = –40, 25, 125°C
Figure 14. Output Swing vs Sourcing Current
100
80
60
Input Bias Current (fA)
Output Swing from V+ (V)
1
100m
10m
10m
VS = 3.3 V
100m
1
Output Sourcing Current (mA)
0
-20
-40
-80
-100
10
0
0.2
0.4
SNOS
TA = –40, 25, 125°C
VS = 1.8 V
Figure 15. Output Swing vs Sourcing Current
0.6
0.8
1
1.2
1.4
Common Mode Voltage (V)
1.6
1.8
SNOS
TA = –40°C
Figure 16. Input Bias Current vs Common Mode Voltage
200
100
160
80
120
60
Input Bias Current (fA)
Input Bias Current (fA)
20
-60
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
1m
40
80
40
0
-40
-80
-120
40
20
0
-20
-40
-60
-160
-80
-200
-100
0
0.5
VS = 3.3 V
1
1.5
2
2.5
Common Mode Voltage (V)
3
3.5
0
0.2
0.4
SNOS
TA = –40°C
Figure 17. Input Bias Current vs Common Mode Voltage
VS = 1.8 V
0.6 0.8
1
1.2 1.4
Common Mode Voltage
1.6
1.8
2
SNOS
TA = 25°C
Figure 18. Input Bias Current vs Common Mode Voltage
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Typical Characteristics (continued)
200
100
160
80
120
60
Input Bias Current (pA)
80
40
0
-40
-80
-120
40
20
0
-20
-40
-60
-160
-80
-200
-100
0
0.5
1
1.5
2
2.5
Common Mode Voltage (V)
VS = 3.3 V
3
3.5
0
0.2
0.4
SNOS
TA = 25°C
0.6 0.8
1
1.2 1.4
Common Mode Voltage (V)
VS= 1.8V
Figure 19. Input Bias Current vs Common Mode Voltage
1.8
TA = 125°C
Figure 20. Input Bias Current vs Common Mode Voltage
160
150
100
125
120
Phase
80
80
AOL (dB)
40
0
-40
-80
100
60
75
40
50
20
25
-120
125 qC
25 qC
-40 qC
0
-160
0
Gain
-20
-200
0
0.5
1
1.5
2
2.5
Common Mode Voltage (V)
VS = 3.3 V
3
2
SNOS
120
200
Input Bias Current (pA)
1.6
Phase (q)
Input Bias Current (fA)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
10
3.5
100
SNOS
TA = 125°C
VS = 3.3 V
Figure 21. Input Bias Current vs Common Mode Voltage
1k
Frequency (Hz)]
-25
100k
10k
AOL_
TA = –40, 25, 125°C
CL = 50 pF
Figure 22. Open Loop Gain and Phase
1k
20000
100
1000
ZO (k:)
Voltage Noise (nV/—RtHz)
10000
10
100
1
10
100m
1
VS = 3.3 V
10
100
Frequency (Hz)
1k
TA = 25°C
Figure 23. Input Voltage Noise vs Frequency
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10k
SNOS
100
VS = 3.3 V
1k
Frequency (Hz)
10k
100k
SNOS
TA = 25°C
Figure 24. Open Loop Output Impedance
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Typical Characteristics (continued)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
120
Input
Output
100
25 mV/div
EMIRR (dB)
80
60
40
0dBm
-10dBm
-20dBm
20
0
10
100
Frequency (MHz)
VS = 3.3 V
AV = 1
2 ms/div
1000
SNOS
SNOS
TA = 25°C
VIN
VS = 1.8 V
= 0.9 ± 0.1 V
TA = 25°C
AV = 1
CL = 50 pF
Figure 26. Small Signal Pulse Response, 1.8 V
Figure 25. EMIRR Performance
Input
Output
25 mv/div
200 mV/div
Input
Output
2 ms/div
2 ms/div
SNOS
VS = 3.3 V
VIN = 1.65 ± 0.1 V
TA = 25 °C
AV = 1
SNOS
CL = 50 pF
Figure 27. Small Signal Pulse Response, 3.3 V
VS = 1.8 V
VIN = 0.9 ± 0.5 V
TA = 25°C
AV = 1
CL = 50 pF
Figure 28. Large Signal Pulse Response, 1.8 V
200 mV/div
Input
Output
2 ms/div
SNOS
VS = 3.3 V
VIN = 1.65 ± 1 V
TA = 25°C
AV = 1
CL = 50 pF
Figure 29. Large Signal Pulse Response, 3.3 V
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8 Detailed Description
8.1 Overview
The TLV854x amplifiers are unity-gain stable and can operate on a single supply, making them highly versatile
and easy to use.
Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics
curves.
8.2 Functional Block Diagram
V+
-IN
OUT
+IN
+
V-
8.3 Feature Description
The differential inputs of the TLV854x device consist of a non-inverting input (+IN) and an inverting input (–IN).
The device amplifies only the difference in voltage between the two inputs, which is called the differential input
voltage. The output voltage of the op-amps VOUT are given by Equation 1:
VOUT = AOL [(+IN) – (–IN)]
where
•
AOL is the open-loop gain of the amplifier, typically around 100 dB.
(1)
8.4 Device Functional Modes
8.4.1 Rail-To-Rail Input
The input common-mode voltage range of the TLV854x extends to the supply rails. This is achieved with a
complementary input stage — an N-channel input differential pair in parallel with a P-channel differential pair.
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 800 mV to 200 mV above
the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to
approximately (V+) – 800 mV. There is a small transition region, typically (V+) – 1.2 V to (V+) – 0.8 V, in which
both pairs are on. This 400-mV transition region can vary 200 mV with process variation. Within the 400-mV
transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation
outside this region.
8.4.2 Supply Current Changes Over Common Mode
Because of the ultra-low supply current, changes in common mode voltages cause a noticeable change in the
supply current as the input stages transition through the transition region, as shown in Figure 30.
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Device Functional Modes (continued)
Quiecent Current per Channel (nA)
800
720
640
560
480
400
320
240
160
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
80
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Common Mode Voltage (V)
1.6
1.8
SNOS
Figure 30. Supply Current Change Over Common Mode at 1.8 V
For the lowest supply current operation, keep the input common mode range between V– and 1 V below V+.
8.4.3 Design Optimization With Rail-To-Rail Input
In most applications, operation is within the range of only one differential pair. However, some applications can
subject the amplifier to a common-mode signal in the transition region. Under this condition, the inherent
mismatch between the two differential pairs may lead to degradation of the CMRR and THD. The unity-gain
buffer configuration is the most problematic as it traverses through the transition region if a sufficiently wide input
swing is required.
8.4.4 Design Optimization for Nanopower Operation
When designing for ultra-low power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors react with stray capacitance in the circuit and the input capacitance of
the operational amplifier (op amp). These parasitic RC combinations can affect the stability of the overall system.
A feedback capacitor may be required to assure stability and limit overshoot or gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors because large electolytics may have static leakage currents in the tens to
hundreds of nanoamps.
8.4.5 Common-Mode Rejection
The CMRR for the TLV854x is specified in two ways so the best match for a given application may be used.
First, the CMRR of the device in the common-mode range below the transition region (VCM < (V+) – 1.2 V) is
given. This specification is the best indicator of the capability of the device when the application requires use of
one of the differential input pairs. Second, the CMRR at VS = 3.3 V over the entire common-mode range is
specified.
8.4.6 Output Stage
The TLV854x output voltage swings 20 mV from rails at a 3.3-V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The TLV854x maximum output voltage swing defines the maximum swing possible under a particular output
load.
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Device Functional Modes (continued)
8.4.7 Driving Capacitive Load
The TLV854x is internally compensated for stable unity-gain operation, with a 8-kHz typical gain bandwidth.
However, the unity-gain follower is the most sensitive configuration-to-capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the output impedance of the amplifier
creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly
reduced, the response is under-damped, which causes peaking in the transfer and, when there is too much
peaking, the op amp might start oscillating.
In order to drive heavy (> 50 pF) capacitive loads, use an isolation resistor, RISO, as shown in Figure 31. By
using this isolation resistor, the capacitive load is isolated from the output of the amplifier. The larger the value of
RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop is stable,
independent of the value of CL. However, larger values of RISO (e.g. 50 kΩ) result in reduced output swing and
reduced output current drive.
RISO
VOUT
VIN
+
CL
Figure 31. Resistive Isolation of Capacitive Load
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV854x is a nanopower op amps that provides 8-kHz bandwidth with only 500-nA typical quiescent current
per channel and near precision drift specifications at a low cost. These rail-to-rail input and output amplifiers are
specifically designed for battery-powered applications. The input common-mode voltage range extends to the
power-supply rails and the output swings to within millivolts of the rails, maintaining a wide dynamic range.
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9.2 Typical Application: Battery-Powered Wireless PIR Motion Detectors
VBAT
CR2032
coin cell
Radiated heat from an
object in motion
Quad Package
Supply Pin
R1
C1
PIR
IVREF
VBAT
VBAT
R7
C7
R8
C2
D
Vin
Rg
S
R2
+
TLV8544
C
_
MCU I/O
+
+
TLV8544
A
_
Fresnel
Lens
TLV8544
_ B
C4 R4
Signal
+
R3
R9
R5
C3
C5
VBAT
D1
TLV8544
D
_
MCU I/O
C8
R10
VREF generator
network
D2
R6
C6
Gain Stages,
bandpass filters
Window
Comparator
Figure 32. PIR Motion Detector Circuit
9.2.1 Design Requirements
Smart building automation systems employ a large number of various sensing nodes distributed throughout
small, medium, and large infrastructures. The sensing nodes measure motion, temperature, vibration, and other
parameters of interest. Wireless nodes are monitored in a central location. Because of the large number of
distributed nodes , battery-operation and cost-optimized electronic components are required. Typically, the
wireless nodes need to run on a single CR2032 coin battery for eight to ten years.
For more information see Design of Ultra-Low Power Discrete Signal Conditioning Circuit for Battery-Power,
Ultra-Low-Power Wireless PIR Motion Detector Reference Design and BOOSTXL-TLV8544PIR User's Guide.
The BOOSTXL-TLV8544PIR along with the companion CC2650 LaunchPad, LAUNCHXL-CC2650 can be
obtained from the TI website for hands-on experiments.
9.2.2 Detailed Design Procedure
Referring to Figure 32, the TLV8544 4-channel op amp is powered directly by a 3.3-V CR2032 coin battery. The
first two amplifier stages of the TLV8544 implement active filter functionality. The remaining two amplifiers of the
TLV8544 are used for building a window comparator. The comparator flags the detection of a motion event to an
ultra-low-power wireless microcontroller on the same board. Due to the higher gain in the filter stages and higher
output noise from the sensor, it is necessary to optimize the placement of the high-frequency filter pole and the
window comparator thresholds to avoid false detection.
The first two amplifiers (A and B) in the circuit are used in identical active bandpass filters with corner
frequencies of 0.7 and 10.6 Hz. Each filter stage has a gain of about 220 V/V to account for the reduced
sensitivity of the sensor due to the low current biasing of the PIR sensor. Considering the 8-kHz unity gain
bandwidth (UGBW) product of the TLV8544, the bandwidth of each stage is limited to approximately 36 Hz. The
above choice of cutoff frequencies give a relatively wide bandwidth to detect a person running in the field of view,
yet narrow enough to limit the peak-to-peak noise at the output of the filters.
Amplifier A is a noninverting gain/filter stage providing the high input impedance needed to prevent loading of the
sensor. The DC gain of the stage due to the presence of C6 is unity. Therefore, the sensor output provides the
bias voltage needed at the A stage to avoid clipping of the lower cycle of the input signal. Diodes D1 and D2 limit
the output signal, avoiding overdriving of the second stage and consequently placing a large charge on coupling
capacitor C4, which helps with the recovery time.
9.2.2.1 Calculation of the Cutoff Frequencies and Gain of Stage A:
The low cutoff frequency of the bandpass filter in stage A is:
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Typical Application: Battery-Powered Wireless PIR Motion Detectors (continued)
¦Clow
1
2S u R 6 u C6
(2)
Choosing R6 = 6.81 kΩ and C6 = 33 μF, the low cutoff frequency is fClow= 0.71 Hz. The high cutoff frequency of
the filter is:
¦Chigh
1
2S u R5 u C5
(3)
For R5 = 1.5 MΩ and C5 = 0.01 µF, the high cutoff frequency is fChigh= 10.6 Hz. The gain of the stage is:
G
1
R5
R6
(4)
Choosing R5 = 1.5 MΩ and R6 = 6.81 kΩ, the gain of the stage A is G = 221.26 V/V (46.9 dB).
9.2.2.2 Calculation of the Cutoff Frequencies and Gain of Stage B
As shown in Figure 32, amplifier B is an inverting bandpass filter and gain stage. Capacitor C4 creates an AC
coupled path between the A and the B stages. Thus the signal level must be shifted at the input of the amplifier
B. This is done by connecting a midpoint voltage of the reference voltage dividers comprising R10, R9, R8 and
R7 to the non-inverting input of amplifier B, biasing the input signal to the mid-rail (1.65 V). A very large feedback
resistor R3 is chosen to minimize the dynamic current due to presence of peak-to-peak noise voltage at the
output of this stage.
The low cutoff frequency of the filter of the stage B is:
¦Clow
1
2S u R 4 u C 4
(5)
Choosing R4 = 68.1 kΩ and C4 = 3.3 μF, the low cutoff frequency is fClow = 0.71 Hz. The high cutoff frequency of
the filter is:
¦Chigh
1
2S u R3 u C3
(6)
For R3 = 15 MΩ and C3 = 1000 pF, the high cutoff frequency is fChigh= 10.6 Hz. The gain of the stage is:
G
R3
R4
(7)
For R3 = 15 MΩ and R4 = 68.1 kΩ, the gain is calculated |G| = 220.26 V/V (46.9 dB).
9.2.2.3 Calculation of the Total Gain of Stages A and B
The overall gain of the two stages A and B is: GTotal= GA × GB= 221.26 × 220.26 = 48810 V/V = 93.77 dB.
9.2.2.4 Window Comparator Stage
The signal from a moving object in front of the PIR sensor, after amplification and filtering, is connected to a
window comparator. The comparator converts the analog signal to digital pulses for interrupting an on-board
microcontroller unit (MCU), flagging detection of motion. A different approach is to digitize the analog signal
continuously by an analog-to-digital converter (ADC) and implement the comparator functionality in the digital
domain. This method has the advantage of enabling the post processing of the data to reduce the chance of
false detection. However, continuous conversion and processing of data by the MCU increases the power
consumption, lowering the lifetime of the battery substantially.
Rather than using a separate low-power comparator integrated circuits to implement the window comparator
section of the circuit, the remaining op amps in the TLV8544 package are used to implement the comparator
stage. Benefits of this approach include fewer components and thus reduced system cost.
Although an op amp can sometimes be used as a comparator, an amplifier cannot be used as a comparator
interchangeably in all applications because of relatively long recovery time of the amplifier from output saturation
and relatively long propagation delay due to internal compensation. Particularly, the nanopower op amps have
very slow slew rate, limiting their usage as a comparator in only applications with very low frequency input signal.
Fortunately, PIR sensor signals are relatively slow and this should not be an issue.
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Typical Application: Battery-Powered Wireless PIR Motion Detectors (continued)
The new TLV8544 device is particularly suitable for implementing a window comparator in a battery operated PIR
motion detector application because of its rail-to-rail operation capability, relatively low offset voltage, low offset
voltage drift, very low bias current, and nanopower consumption, all at an optimal cost. The input signal of the
comparator stage in the presence of moving heat source across the sensor is shown in Figure 33. The signal is
centered at mid-rail and can swing up or down from the center.
The window comparator is a combination of a non-inverting comparator implemented with amplifier D and an
inverting comparator implemented with amplifier C, as shown in Figure 32.
VBAT
VREF_High
PIR signal
Vbias
VREF_Low
GND
&RPS ³'´ 2XWSXW
&RPS ³&´ 2XWSXW
Order of the pulses depends on the
direction of the motion
Figure 33. Ideal Amplified PIR Signal and the Output of the Window Comparator Circuit
9.2.2.5 Reference Voltages
Referring to Figure 32, the divider networks comprising R7, R8, R9, and R10, generate the reference voltages
VREF_High and VREF_Low of the window comparator. The center point of the divider provides the bias voltage
of the gain in the stage B through the connection to the noninverting input of the amplifier.
Due to the very low bias current of the TLV8544 device, it is possible to use very large values of resistors in the
divider networks to minimize the current to ground through the resistors to a negligible amount. For R7 = R8 =
R9 = R10 = 15 MΩ:
VREF_High
§ R7 R8 R9 ·
¨ R7 R8 R9 R10 ¸ VCC
©
¹
4.5 u 106
VREF_Low
R7
§
·
¨ R8 R9 R10 R7 ¸ VCC
©
¹
1.5 u 106
6 u 106
6 u 106
u VCC
0.75 u VCC
u VCC
0.25 u VCC
(8)
(9)
Low leakage ceramic capacitors C7, and C8, maintain constant threshold voltages, preventing potential chatter at
the output of the comparators. It should be noted that using cheap electrolytic capacitors must be avoided as
they have high (many µA) leakage current. The comparator outputs stay low in the absence of motion across the
sensor. In the presence of motion, comparators C and D generate high output pulses as shown in Figure 33. The
order of the pulses depends on the direction of the motion in front of the sensor.
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Typical Application: Battery-Powered Wireless PIR Motion Detectors (continued)
9.2.3 Application Curve
Scope plots of the amplified PIR signal at the input of the noninverting comparator and the corresponding output
signal are shown in Figure 34 and Figure 35. As the PIR signal (blue line) crosses the VREF_High threshold, the
output of the comparator switches from the cutoff (slightly higher than ground) state to the saturation state
(slightly lower than VBAT = 3.3 V). Depending on the speed of the object, the PIR signal peaks to its maximum
and roles off within several seconds. When the signal crosses the VREF_High threshold on the way down, the
output of the noninverting amplifier toggles back to the cutoff region (low).
The data for plot of Figure 34 was captured using the BOOSTXL-TLV8544PIR board. Because the motion was
created at very close proximity of the sensor on the booster board used to collect the data, the signal was limited
by the diode in the first stage as shown in the plot.
Figure 34. Noninverting Comparator Input and Output Signals
Referring to Figure 34, the output of the inverting comparator during the lower cycle of the PIR signal switches
form the cutoff region to the saturation region as the input signal crosses the VREF_Low threshold.
Figure 35. Noninverting Comparator Input and Output Signals
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9.3 Typical Application: 60-Hz Twin T Notch Filter
VBAT
CR2032 coin cell
10 M
10 M
VBAT
Signal from a remote sensor
containing 60 Hz noise
+
¼
TLV8544
VIN
To ADC
10 0Ÿ
270 pF
10 0Ÿ
VOUT
10 0Ÿ
270 pF
10 0Ÿ
60 Hz Twin notch filter
With gain of Av = 2 V/V
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Figure 36. 60 Hz-Notch Filter
9.3.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60-Hz
interference from AC power lines. The circuit of Figure 36 filters out (notches out) the 60 Hz and provides a
system gain of AV = 2 V/V for the sensor signal represented by a 1-kHz sine wave. Similar stages may be
cascaded to remove 2nd and 3rd harmonics of 60 Hz. Thanks to the nanopower consumption of the TLV8544,
even five such circuits can run for 9.5 years from a small CR2032 lithium cell. These batteries have a nominal
voltage of 3 V and an end of life voltage of 2 V. With an operating voltage from 1.7 V to 3.6 V the TLV8544
device can function over this voltage range.
9.3.2 Detailed Design Procedure
The notch frequency is set by:
F0 = 1 / 2πRC.
(10)
To achieve a 60-Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50-Hz noise, use R = 11.8 MΩ and C =
270 pF.
The twin T notch filter works by having two separate paths from VIN to the input of the amplifier. A low-frequency
path through the series input resistors and another separate high-frequency path through the series input
capacitors. However, at frequencies around the notch frequency, the two paths have opposing phase angles,
and the two signals tend to cancel at the input of the amplifier.
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter must
be as balanced as possible. To obtain circuit balance, while overcoming limitations of available standard resistor
and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements for the filter
components that connect to ground.
To make sure passive component values stay as expected, clean the board with alcohol, rinse with deionized
water, and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which
may increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
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Typical Application: 60-Hz Twin T Notch Filter (continued)
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op-amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 36 can be done over a bandwidth of 2 kHz,
which takes the conservative approach of overestimating the bandwidth (TLV8544 typical GBW/AV is lower,
where AV is the gain of the system). The total noise at the output is approximately 800 µVpp, which is excellent
considering the total consumption of the circuit is only 500 nA per channel. The dominant noise terms are opamp voltage noise, current noise through the feedback network (430 µVp-p), and current noise through the notch
filter network (280 µVp-p). Thus the total noise of the circuit is below 1/2 LSB of a 10-bit system with a 2-V
reference, which is 1 mV.
9.3.3 Application Curve
Figure 37. 60-Hz Notch Filter Waveform
9.4 Dos and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, multiplexers, and ADC
inputs.
Do add series current limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 KΩ per volt).
10 Power Supply Recommendations
The TLV854x is specified for operation from 1.7 V to 3.6 V (±0.85 V to ±1.8 V) over a –40°C to +125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 3.6 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 100-nF capacitors be placed as close as possible to the op-amp power supply pins. For single
supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor between V+
and ground and one capacitor between V– and ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against highfrequency switching supplies and other 1-kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
The V+ pin must be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground.
Connect the ground pin to the PCB ground plane at the pin of the device.
Place the feedback components as close as possible to the device to minimize stray impedance.
11.2 Layout Example
VOUTA
Place components close to
device and to each other to
reduce parasitic error
xx
RG
RF
A
GND
VIN
Run the input traces as
far away from the supply
lines as possible
Place low-ESR ceramic
bypass capacitor close to
device
OUTA 1
V+
+
+
14
OUTD
13
-IND
D
-INA
2
+INA
3
12
+IND
V+
4
11
V-
+INB
5
10
+INC
-INB
6
9
-INC
OUTB
7
8
OUTC
x
x
GND
x
x
B
x
GND
+
+
C
Figure 38. Layout Example of a Typical Dual Channel Package (Top View)
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
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TLV8544, TLV8542, TLV8541
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program
DIP Adapter Evaluation Module
TI Universal Operational Amplifier Evaluation Module
TI FilterPro Filter Design Software
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• AN-1798 Designing with Electro-Chemical Sensors
• AN-1803 Design Considerations for a Transimpedance Amplifier
• AN-1852 Designing With pH Electrodes
• Compensate Transimpedance Amplifiers Intuitively
• Transimpedance Considerations for High-Speed Operational Amplifiers
• Noise Analysis of FET Transimpedance Amplifiers
• Circuit Board Layout Techniques
• Handbook of Operational Amplifier Applications
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV8544
Click here
Click here
Click here
Click here
Click here
TLV8542
Click here
Click here
Click here
Click here
Click here
TLV8541
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
22
Submit Documentation Feedback
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
TLV8544, TLV8542, TLV8541
www.ti.com
SNOSD29E – DECEMBER 2016 – REVISED APRIL 2018
12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TLV8544 TLV8542 TLV8541
Submit Documentation Feedback
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV8541DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1D5L
TLV8542DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL8542
TLV8542RUGR
ACTIVE
X2QFN
RUG
8
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AR
TLV8544DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV8544
TLV8544DT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV8544
TLV8544PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL8544
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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