TLV9022DR

TLV9022, TLV9032, TLV9024, TLV9034 SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 TLV902x and TLV903x High-Precision Dual and Quad Comparators These comparators also feature no output phase inversion with fault-tolerant inputs that can go up to 6-V without damage. This makes this family of comparators well suited for precision voltage monitoring in harsh, noisy environments. 1 Features • • • • • • • • • • • 1.65 V to 5.5 V supply range Precision input offset voltage 300 μV Power-on Reset (POR) for known start-up Rail-to-Rail input with fault-tolerance 100 ns typical propagation delay Low quiescent current 16 μA per channel Low input bias current 5 pA Open-drain output option (TLV902x) Push-pull output option (TLV903x) Full -40°C to +125°C temperature range 2 kV ESD protection The TLV902x comparators have an open-drain output stage that can be pulled below or beyond the supply voltage, making it appropriate for low voltage logic and level translators. The TLV903x comparators have a push-pull output stage capable of sinking and sourcing milliamps of current when controlling an LED or driving a capacitive load such as a MOSFET gate. 2 Applications • • • • • The TLV902x and TLV903x are specified for the Industrial temperature range of -40°C to +125°C and are available in a standard leaded and leadless packages. Appliances Building automation Factory automation & control Motor drives Infotainment & cluster Device Information PACKAGE (1) PART NUMBER 3 Description The TLV902x and TLV903x are a family of dual and quad channel comparators. The family offers low input offset voltage, integrated Power-On Reset (POR) circuitry, and fault-tolerant inputs with an excellent speed-to-power combination with a propagation delay of 100 ns. Operating voltage range of 1.65 V to 5.5 V with a quiescent supply current of 18 μA per channel. This device family also includes a Power-on Reset (POR) feature that ensures the output is in a known state until the minimum supply voltage has been reached and a small time period passed before the output starts responding to the inputs. This prevents output transients during system power-up and powerdown. TLV9022, TLV9032 (Dual) TLV9024, TLV9034 (Quad) (1) BODY SIZE (NOM) SOIC (8) 3.91 mm × 4.90 mm TSSOP (8) 3.00 mm × 4.40 mm VSSOP (8) 3.00 mm × 3.00 mm WSON (8) 2.00 mm × 2.00 mm SOT-23 (8) (Preview) 1.60 mm × 2.90 mm SOIC (14) (Preview) 3.91 mm × 8.65 mm TSSOP (14) 4.40 mm × 5.00 mm SOT-23 (14) (Preview) 4.20 mm x 2.00 mm WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. V+ V+ V+ IN+ + IN- - V+ Output Control SNAPBACK ESD CLAMPS V- IN+ + IN- - OUT V- Power-On-Reset (POR) Bias Output Control SNAPBACK ESD CLAMPS VV- V- V+ V- V- V- OUT Power-On-Reset (POR) Bias V- V- TLV9022 and TLV9024 Block Diagram TLV9032 and TLV9034 Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions: TLV90x2.................................................... 3 Pin Functions: TLV90x4.................................................... 4 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings ....................................... 5 6.2 ESD Ratings .............................................................. 5 6.3 Recommended Operating Conditions ........................5 6.4 Thermal Information, TLV90x2 ...................................6 6.5 Thermal Information, TLV90x4 ...................................6 6.6 Electrical Characteristics, TLV90x2 ........................... 7 6.7 Switching Characteristics, TLV90x2 ...........................8 6.8 Electrical Characteristics, TLV90x4 ........................... 9 6.9 Switching Characteristics, TLV90x4 .........................10 6.10 Typical Characteristics............................................ 11 7 Detailed Description......................................................17 7.1 Overview................................................................... 17 7.2 Functional Block Diagram......................................... 17 7.3 Feature Description...................................................17 7.4 Device Functional Modes..........................................17 8 Application and Implementation.................................. 20 8.1 Application Information............................................. 20 8.2 Typical Applications.................................................. 23 8.3 Power Supply Recommendations.............................30 9 Layout.............................................................................31 9.1 Layout Guidelines..................................................... 31 9.2 Layout Example........................................................ 31 10 Device and Documentation Support..........................32 10.1 Documentation Support.......................................... 32 10.2 Receiving Notification of Documentation Updates..32 10.3 Support Resources................................................. 32 10.4 Trademarks............................................................. 32 10.5 Electrostatic Discharge Caution..............................32 10.6 Glossary..................................................................32 11 Mechanical, Packaging, and Orderable Information.................................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2021) to Revision D (August 2021) Page • Removed TLV9032 VSSOP, TSSOP and WSON preview status in Device Info table....................................... 1 Changes from Revision B (November 2020) to Revision C (August 2021) Page • Added status to Device Info table....................................................................................................................... 1 Changes from Revision A (September 2020) to Revision B (November 2020) Page • Added Quad Devices..........................................................................................................................................1 • Updated tables for Quad.....................................................................................................................................5 Changes from Revision * (June 2020) to Revision A (December 2020) Page • Initial release.......................................................................................................................................................1 • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added Typical Graphs.......................................................................................................................................11 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 5 Pin Configuration and Functions OUT1 IN1± 1 8 2 7 V+ OUT1 1 IN1± 2 IN1+ 3 V± 4 OUT2 IN1+ 3 6 IN2± V± 4 5 IN2+ Figure 5-1. D, DGK, PW, DDF Packages 8-Pin SOIC, VSSOP, TSSOP, SOT-23-8 Top View Exposed Thermal Die Pad on Underside 8 V+ 7 OUT2 6 IN2± 5 IN2+ NOTE: Connect exposed thermal pad directly to V- pin. Figure 5-2. DSG Package, 8-Pad WSON With Exposed Thermal Pad, Top View Pin Functions: TLV90x2 PIN NAME NO. I/O DESCRIPTION OUT1 1 O Output pin of the comparator 1 IN1– 2 I Inverting input pin of comparator 1 IN1+ 3 I Noninverting input pin of comparator 1 V– 4 — IN2+ 5 I Noninverting input pin of comparator 2 IN2– 6 I Inverting input pin of comparator 2 OUT2 7 O Output pin of the comparator 2 V+ 8 — Positive supply Thermal Pad — — Connect directly to V- pin Negative (low) supply Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 3 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 IN2± 6 9 IN3+ IN2+ 7 8 IN3± Figure 5-3. D, PW, DYY Package, 14-Pin SOIC, TSSOP, SOT-23, Top View OUT4 10 IN4± 13 5 2 12 V± 11 IN4+ 10 NC Thermal NC 3 IN1+ 4 Pad 9 8 IN1+ IN1± IN3+ 11 IN4+ OUT3 4 1 14 IN1± V+ 7 12 V± IN3± 3 OUT2 V+ 15 13 OUT4 6 2 IN2+ OUT1 OUT1 14 OUT3 5 1 IN2± OUT2 16 Pin Functions: TLV90x4 IN4± Not to scale NOTE: Connect exposed thermal pad directly to V- pin. Figure 5-4. RTE Package, 16-Pad WQFN With Exposed Thermal Pad, Top View Table 5-1. Pin Functions: TLV90x4 PIN NAME(1) DESCRIPTION WQFN OUT2 1 15 Output Output pin of the comparator 2 OUT1 2 16 Output Output pin of the comparator1 V+ 3 1 — IN1– 4 2 Input Negative input pin of the comparator 1 IN1+ 5 4 Input Positive input pin of the comparator 1 IN2– 6 5 Input Negative input pin of the comparator 2 IN2+ 7 6 Input Positive input pin of the comparator 2 IN3– 8 7 Input Negative input pin of the comparator 3 IN3+ 9 8 Input Positive input pin of the comparator 3 IN4– 10 9 Input Negative input pin of the comparator 4 IN4+ 11 11 Input Positive input pin of the comparator 4 V– 12 12 — OUT4 13 13 Output Output pin of the comparator 4 OUT3 14 14 Output Output pin of the comparator 3 NC — 3 — No Internal Connection - Leave floating or GND NC — 10 — No Internal Connection - Leave floating or GND Thermal Pad — PAD — Connect directly to V- pin. (1) 4 I/O SOIC Positive supply Negative supply Some manufacturers transpose the names of channels 1 & 2. Electrically the pinouts are identical, just a difference in channel naming convention. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Supply voltage: VS = (V+) – (V–) Input pins (IN+, IN–) from V–(2) MIN MAX –0.3 6 UNIT V –0.3 6 V Current into Input pins (IN+, IN–) –10 10 mA Output (OUT) from V–, open drain only(3) –0.3 6 V Output (OUT) from V–, push-pull only –0.3 (V+) + 0.3 V 10 s 150 °C 150 °C Output short circuit duration(4) Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to (V–). Input signals that can swing more than 0.3 V beyond the supply rails must be current-limited to 10 mA or less. Additionally, Inputs (IN+, IN–) can be greater than V+ and OUT as long as it is within the –0.3 V to 6 V range Output (OUT) for open drain can be greater than V+ and inputs (IN+, IN–) as long as it is within the –0.3 V to 6 V range Short-circuit to V– or V+. Short circuits from outputs can cause excessive heating and eventual destruction. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage: VS = (V+) – (V–) 1.65 5.5 Input voltage range (IN+, IN–) from (V–) –0.2 5.7 V Ambient temperature, TA –40 125 °C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 UNIT V Submit Document Feedback 5 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.4 Thermal Information, TLV90x2 TLV90x2 THERMAL METRIC (1) D (SOIC) PW DGK (TSSOP) (VSSOP) DSG (WSON) DDF (SOT-23) 8 PINS 8 PINS 8 PINS 8 PINS 8 PINS UNIT RqJA Junction-to-ambient thermal resistance 167.7 221.7 215.8 175.2 240.0 °C/W RqJC(top) Junction-to-case (top) thermal resistance 107.0 109.1 105.2 178.1 151.0 °C/W RqJB Junction-to-board thermal resistance 111.2 152.5 137.5 139.5 157.0 °C/W yJT Junction-to-top characterization parameter 53.1 36.4 39.6 47.2 32.8 °C/W yJB Junction-to-board characterization parameter 110.4 150.7 135.9 138.9 155.4 °C/W RqJC(bot) Junction-to-case (bottom) thermal resistance – – – 127.3 – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Thermal Information, TLV90x4 TLV90x4 THERMAL METRIC(1) PW (TSSOP) RTE (WQFN) DYY (SOT-23) UNIT 14 PINS 14 PINS 16 PINS 14 PINS RqJA Junction-to-ambient thermal resistance 136.0 155.0 134.1 – °C/W RqJC(top) Junction-to-case (top) thermal resistance 91.2 82.0 122.6 – °C/W RqJB Junction-to-board thermal resistance 92.0 98.5 109.3 – °C/W yJT Junction-to-top characterization parameter 46.9 25.7 30.9 – °C/W yJB Junction-to-board characterization parameter 91.6 97.6 108.3 – °C/W RqJC(bot) Junction-to-case (bottom) thermal resistance – – 98.7 – °C/W (1) 6 D (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.6 Electrical Characteristics, TLV90x2 For VS (Total Supply Voltage) = (V+) – (V– ) = 5 V, VCM = (V– ) at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX –1.5 ±0.3 1.5 UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 1.8 V and 5 Vx VOS Input offset voltage VS = 1.8 V and 5 V, TA = –40°C to +125°C dVIO/dT Input offset voltage drift VS = 1.8 V and 5 V, TA = –40°C to +125°C –2 2 ±0.5 mV µV/°C POWER SUPPLY IQ Quiescent current per comparator VS = 1.8 V and 5 V, No Load, Output Low IQ Quiescent current per comparator VS = 1.8 V and 5 V, No Load, Output Low, TA = –40°C to +125°C PSRR Power-supply rejection ratio VS = 1.8 V to 5 V, TA = –40°C to +125°C, (pushpull verison) 75 95 dB PSRR Power-supply rejection ratio VS = 1.8 V to 5 V, TA = –40°C to +125°C (open drain version) 80 95 dB 16 30 µA 35 INPUT BIAS CURRENT IB Input bias current VCM = VS/2 5 pA IOS Input offset current VCM = VS/2 1 pA INPUT CAPACITANCE CID Input Capacitance, Differential VCM = VS/2 2 pF CIC Input Capacitance, Common Mode VCM = VS/2 3 pF INPUT VOLTAGE RANGE VCM-Range Common-mode voltage range VS = 1.8 V and 5 V, TA = –40°C to +125°C CMRR Common-mode rejection ratio VS = 5 V, (V–) – 0.2 V < VCM < (V+) + 0.2 V, TA = –40°C to +125°C 60 70 dB CMRR Common-mode rejection ratio VS = 1.8 V, (V–) – 0.2 V < VCM < (V+) + 0.2 V, TA = –40°C to +125°C 50 60 dB For open drain version only 50 200 V/mV (V–) – 0.2 (V+) + 0.2 V OPEN-LOOP GAIN AVD Large signal differential voltage amplification OUTPUT VOL Voltage swing from (V–) ISINK = 4 mA, TA = 25°C VOL Voltage swing from (V–) ISINK = 4 mA, TA = –40°C to +125°C VOH Voltage swing from (V+) ISOURCE = 4 mA, TA = 25°C (push-pull only) VOH Voltage swing from (V+) ISOURCE = 4 mA, TA = –40°C to +125°C (pushpull only) ILKG Open-drain output leakage current VPULLUP = (V+), TA = 25°C (open drain only) ISC Short-circuit current VS = 5 V, Sinking ISC Short-circuit current VS = 5 V, Sourcing (push-pull only) 75 75 125 mV 175 mV 125 mV 175 mV 100 pA 90 100 mA 90 100 mA Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 7 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.7 Switching Characteristics, TLV90x2 For VS (Total Supply Voltage) = (V+) – (V– ) = 5 V, VCM = VS / 2, CL = 15 pF at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT TPD-HL Propagation delay time, highto-low TPD-LH VID = –100 mV; Delay from mid-point of input to mid-point of output (RP = 2.5 KΩ for open drain only) 100 ns VID = 100 mV; Delay from mid-point of Propagation delay time, low-toinput to mid-point of output (for push-pull high only) 115 ns TPD-LH VID = 100 mV; Delay from mid-point of Propagation delay time, low-toinput to mid-point of output (RP = 2.5 KΩ high for open drain only) 150 ns TFALL 5V Output Fall Time, 80% to 20% VID = –100 mV 3 ns TRISE 5V Output Rise Time, 20% to 80% VID = 100 mV (for push-pull only) 3 ns FTOGGLE 5V, Toggle Frequency VID = 100 mV (RP = 2.5 KΩ for open drain only) 3 MHz 20 µs POWER ON TIME PON 8 Power on-time Submit Document Feedback VS = 1.8 V and 5 V, VCM = (V–), VID = –0.1 V, VPULL-UP = VS / 2, Delay from VS / 2 to VOUT = 0.1 x VS / 2 (RP = 2.5 KΩ for open drain only) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.8 Electrical Characteristics, TLV90x4 For VS (Total Supply Voltage) = (V+) – (V– ) = 5 V, VCM = (V– ) at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX –1.5 ±0.3 1.5 UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 1.8 V and 5 Vx VOS Input offset voltage VS = 1.8 V and 5 V, TA = –40°C to +125°C dVIO/dT Input offset voltage drift VS = 1.8 V and 5 V, TA = –40°C to +125°C –2 2 ±0.5 mV µV/°C POWER SUPPLY IQ Quiescent current per comparator VS = 1.8 V and 5 V, No Load, Output Low IQ Quiescent current per comparator VS = 1.8 V and 5 V, No Load, Output Low, TA = –40°C to +125°C PSRR Power-supply rejection ratio VS = 1.8 V to 5 V, TA = –40°C to +125°C, (pushpull version) PSRR Power-supply rejection ratio VS = 1.8 V to 5 V, TA = –40°C to +125°C, (pushpull version) PSRR Power-supply rejection ratio VS = 1.8 V to 5 V, TA = –40°C to +125°C, (open drain version) PSRR Power-supply rejection ratio VS = 1.8 V to 5 V, TA = –40°C to +125°C, (open drain version) 16 30 µA 35 177.8 75 95 dB 100 80 µV/V µV/V 95 dB INPUT BIAS CURRENT IB Input bias current VCM = VS/2 5 pA IOS Input offset current VCM = VS/2 1 pA INPUT CAPACITANCE CID Input Capacitance, Differential VCM = VS/2 2 pF CIC Input Capacitance, Common Mode VCM = VS/2 3 pF INPUT VOLTAGE RANGE VCM-Range Common-mode voltage range VS = 1.8 V and 5 V, TA = –40°C to +125°C CMRR Common-mode rejection ratio VS = 5 V, (V–) – 0.2 V < VCM < (V+) + 0.2 V, TA = –40°C to +125°C 60 70 dB CMRR Common-mode rejection ratio VS = 1.8 V, (V–) – 0.2 V < VCM < (V+) + 0.2 V, TA = –40°C to +125°C 50 60 dB For push-pull version only 50 200 V/mV (V–) – 0.2 (V+) + 0.2 V OPEN-LOOP GAIN AVD Large signal differential voltage amplification OUTPUT VOL Voltage swing from (V–) ISINK = 4 mA, TA = 25°C VOL Voltage swing from (V–) ISINK = 4 mA, TA = –40°C to +125°C VOH Voltage swing from (V+) ISOURCE = 4 mA, TA = 25°C (push-pull only) VOH I = 4 mA, TA = –40°C to +125°C (pushVoltage swing from (V+) SOURCE pull only) ILKG Open-drain output leakage current VPULLUP = (V+), TA = 25°C (open drain only) ISC Short-circuit current VS = 5 V, Sinking ISC Short-circuit current VS = 5 V, Sourcing (push-pull only) 75 75 125 mV 175 mV 125 mV 175 mV 100 pA 90 100 mA 90 100 mA Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 9 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.9 Switching Characteristics, TLV90x4 For VS (Total Supply Voltage) = (V+) – (V– ) = 5 V, VCM = VS / 2, CL = 15 pF at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT TPD-HL Propagation delay time, highto-low VID = –100 mV; Delay from mid-point of input to mid-point of output (RP = 2.5 KΩ for open drain only) 100 ns TPD-LH VID = 100 mV; Delay from mid-point of Propagation delay time, low-toinput to mid-point of output (for push-pull high only) 115 ns TPD-LH VID = 100 mV; Delay from mid-point of Propagation delay time, low-toinput to mid-point of output (RP = 2.5 KΩ high for open drain only) 150 ns TFALL 5V Output Fall Time, 80% to 20% VID = –100 mV 3 ns TRISE 5V Output Rise Time, 20% to 80% VID = 100 mV, for push-pull only 3 ns FTOGGLE 5V, Toggle Frequency VID = 100 mV (RP = 2.5 KΩ for open drain only) 3 MHz VS = 1.8 V and 5 V, VCM = (V–), VID = –0.1 V, VPULL-UP = VS / 2, Delay from VS / 2 to VOUT = 0.1 x VS / 2 (RP = 2.5 KΩ for open drain only) 30 µs POWER ON TIME PON 10 Power on-time Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.10 Typical Characteristics TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise noted. 22 27 Supply Current Per Channel (PA) Supply Current Per Channel (PA) 30 24 21 18 15 12 9 125°C 85°C 25°C -40°C 6 3 0 1.5 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 20 18 16 14 1.8V 3.3V 5V 12 10 -40 5.5 30 30 27 27 24 21 18 15 12 9 125°C 85°C 25°C -40°C 6 3 VS=1.8V 0 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Input Voltage (V) 1.4 1.6 1.8 2 Figure 6-3. Supply Current vs. Input Voltage, 1.8V 5 20 35 50 65 Temperature (°C) 80 95 110 125 24 21 18 15 12 9 125°C 85°C 25°C -40°C 6 3 VS=3.3V 0 -0.2 0.2 0.6 1 1.4 1.8 2.2 Input Voltage (V) 2.6 3 3.4 Figure 6-4. Supply Current vs. Input Voltage, 3.3V 30 1000 27 24 21 18 15 12 9 125°C 85°C 25°C -40°C 6 3 0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 Input Voltage (V) 4 4.5 Figure 6-5. Supply Current vs. Input Voltage, 5V 5 5.5 Input Bias Current (pA) Supply Current Per Channel (PA) -10 Figure 6-2. Supply Current vs. Temperature Supply Current Per Channel (PA) Supply Current Per Channel (PA) Figure 6-1. Supply Current vs. Supply Voltage -25 100 10 1 0.1 VS = 5V VIN = VS/2 0.01 0.002 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 6-6. Input Bias Current vs. Temperature Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 11 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.10 Typical Characteristics (continued) TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise noted. 10 10 1 100m 125°C 85°C 25°C -40°C 10m 1m 100P 1m 10m Output Sinking Current (A) Output Voltage from V+ (V) Output Voltage to V- (V) P-P Output Only 100m 125°C 85°C 25°C -40°C 10m 1m 100P 100m Figure 6-7. Output Sinking Current vs. Output Voltage, 1.8V 1 1m 10m Output Sourcing Current (A) 100m Figure 6-8. Output Sourcing Current vs. Output Voltage, 1.8V 10 10 1 100m 125°C 85°C 25°C -40°C 10m 1m 100P 1m 10m Output Sinking Current (A) Output Voltage to V+ (V) Output Voltage to V- (V) P-P Output Only 100m 125°C 85°C 25°C -40°C 10m 1m 100P 100m Figure 6-9. Output Sinking Current vs. Output Voltage, 3.3V 1 1m 10m Output Sourcing Current (A) 100m Figure 6-10. Output Sourcing Current vs. Output Voltage, 3.3V 10 10 1 100m 125°C 85°C 25°C -40°C 10m 1m 100P 1m 10m Output Sinking Current (A) 100m Figure 6-11. Output Sinking Current vs. Output Voltage, 5V 12 Submit Document Feedback Output Voltage to V+ (V) Output Voltage to V- (V) P-P Output Only 1 100m 125°C 85°C 25°C -40°C 10m 1m 100P 1m 10m Output Sourcing Current (A) 100m Figure 6-12. Output Sourcing Current vs. Output Voltage, 5V Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.10 Typical Characteristics (continued) 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -40 5V 3.3V 1.8 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 Sourcing Short Circuit Current (mA) Sinking Short Circuit Current (mA) TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise noted. 110 125 Figure 6-13. Sinking Short Circuit Current vs. Temperature 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 5V 3.3V 1.8 80 95 110 125 Figure 6-14. Sourcing Short Circuit Current vs. Temperature 1k 1k VS = 5V VS = 5V 100 Falltime (ns) Risetime (ns) Push-Pull Output Only 10 125°C 85°C 25°C -40°C 1 10p 100p 1n Output Capacittive Load (F) 10n Figure 6-15. Risetime vs. Capacitive Load 100 10 125°C 85°C 25°C -40°C 1 10p 100p 1n Output Capacittive Load (F) 10n Figure 6-16. Falltime vs. Capacitive Load Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 13 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.10 Typical Characteristics (continued) 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 VS = 1.8V 5 6 7 8 10 -40°C 25°C 85°C 125°C 20 30 4050 70 100 200 300 500 Input Overdrive (mV) Propagation Delay, Low to High (ns) Propagation Delay, High to Low (ns) TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise noted. 1000 5 6 7 8 10 125°C 85°C 25°C -40°C 20 30 4050 70 100 200 300 500 Input Overdrive (mV) 5 6 7 8 10 Figure 6-21. Propagation Delay, High to Low, 5V 14 Submit Document Feedback 1000 -40°C 25°C 85°C 125°C 20 30 4050 70 100 200 300 500 Input Overdrive (mV) 1000 Figure 6-20. Propagation Delay, Low to High, 3.3V -40°C 25°C 85°C 125°C 20 30 4050 70 100 200 300 500 Input Overdrive (mV) VS = 3.3V 5 6 7 8 10 1000 Propagation Delay, Low to High (ns) Propagation Delay, High to Low (ns) VS = 5V 20 30 4050 70 100 200 300 500 Input Overdrive (mV) 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 1000 Figure 6-19. Propagation Delay, High to Low, 3.3V 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -40°C 25°C 85°C 125°C Figure 6-18. Propagation Delay, Low to High, 1.8V Propagation Delay, Low to High (ns) Propagation Delay, High to Low (ns) VS = 3.3V VS = 1.8V 5 6 7 8 10 Figure 6-17. Propagation Delay, High to Low, 1.8V 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 VS = 5V 5 6 7 8 10 -40°C 25°C 85°C 125°C 20 30 4050 70 100 200 300 500 Input Overdrive (mV) 1000 Figure 6-22. Propagation Delay, Low to High, 5V Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.10 Typical Characteristics (continued) TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise noted. 2 2 TA = 125°C 1.6 1.2 Input Offset Voltage (mV) Input Offset Voltage (mV) 1.6 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 -2 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Input Voltage (V) 1.4 1.6 1.8 0.4 0 -0.4 Unit 1 Unit 2 Unit 3 Unit 4 -0.8 -1.2 0 0.5 1 1.5 2 2.5 3 3.5 Input Voltage (V) 4 4.5 5 5.5 Figure 6-24. Offset Voltage vs. Input Votlage at 125°C, 5V 2 TA = 25°C 1.6 1.2 Input Offset Voltage (mV) Input Offset Voltage (mV) 0.8 -2 -0.5 2 2 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 -2 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Input Voltage (V) 1.4 1.6 1.8 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 0 0.5 1 1.5 2 2.5 3 3.5 Input Voltage (V) 4 4.5 5 5.5 Figure 6-26. Offset Voltage vs. Input Votlage at 25°C, 5V 2 TA = -40°C 1.6 Input Offset Voltage (mV) 1.2 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 -2 -0.2 1.2 -2 -0.5 2 2 1.6 TA = 25°C -1.6 Figure 6-25. Offset Voltage vs. Input Votlage at 25°C, 1.8V Input Offset Voltage (mV) 1.2 -1.6 Figure 6-23. Offset Voltage vs. Input Votlage at 125°C, 1.8V 1.6 TA = 125°C 0 0.2 TA = -40°C 1.2 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 0.4 0.6 0.8 1 1.2 Input Voltage (V) 1.4 1.6 1.8 2 Figure 6-27. Offset Voltage vs. Input Votlage at -40°C, 1.8V -2 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 Input Voltage (V) 4 4.5 5 5.5 Figure 6-28. Offset Voltage vs. Input Votlage at -40°C, 5V Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 15 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 6.10 Typical Characteristics (continued) TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise noted. 2 2 TA = 125°C Vin = V+ 1.6 1.2 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 -2 1.5 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 Input Offset Voltage (mV) Input Offset Voltage (mV) 1.6 0.4 0 -0.4 -0.8 -1.2 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 5.5 Unit 1 Unit 2 Unit 3 Unit 4 TA = -40°C Vin = V- 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -2 1.5 5.5 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 5.5 Figure 6-32. Offset Voltage vs. Supply Voltage at 25°C, VIN=V- 2 2 TA = -40°C Vin = V+ 1.6 1.2 0.8 0.4 0 -0.4 -0.8 Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 5.5 Figure 6-33. Offset Voltage vs. Supply Voltage at -40°C, VIN=V+ Submit Document Feedback Input Offset Voltage (mV) Input Offset Voltage (mV) Unit 1 Unit 2 Unit 3 Unit 4 -1.2 -1.6 Figure 6-31. Offset Voltage vs. Supply Voltage at 25°C, VIN=V+ 16 -0.8 1.6 -1.6 -2 1.5 0 -0.4 Figure 6-30. Offset Voltage vs. Supply Voltage at 125°C, VIN=V- Input Offset Voltage (mV) Input Offset Voltage (mV) 0.8 1.6 0.4 2 Unit 1 Unit 2 Unit 3 Unit 4 TA = 25°C Vin = V+ 1.2 -2 1.5 0.8 -2 1.5 2 1.6 1.2 -1.6 5.5 Figure 6-29. Offset Voltage vs. Supply Voltage at 125°C, VIN=V+ TA = 125°C Vin = V- Unit 1 Unit 2 Unit 3 Unit 4 TA = -40°C Vin = V- 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 1.5 2 2.5 3 3.5 4 Supply Voltage (V) 4.5 5 5.5 Figure 6-34. Offset Voltage vs. Supply Voltage at -40°C, VIN=V- Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 7 Detailed Description 7.1 Overview The TLV902x and TLV903x devices are dual-channel, micro-power comparators with push-pull and open-drain outputs and low input offset voltage. Operating down to 1.65 V while only consuming only 16 µA per channel, the TLV902x and TLV903x are ideally suited for portable, automotive and industrial applications. An internal power-on reset circuit ensures that the output remains in a known state during power-up and power-down while fail-safe inputs can tolerate input transients without damage or false outputs. 7.2 Functional Block Diagram V+ V+ * IN+ + IN- SNAPBACK ESD CLAMPS V- V+ * Output Control OUT Power Clamp VV- V- Power-On Reset Bias * Push-Pull Version Only V- 7.3 Feature Description The TLV902x (open-drain output) and TLV903x (push-pull output) devices are micro-power comparators that have low input offset voltages and are capable of operating at low voltages. The TLV90xx family feature a rail-to-rail input stage capable of operating up to 200 mV beyond the power supply rails. The comparators also feature push-pull and open-drain output stage options and Power-on Reset for known start-up conditions. 7.4 Device Functional Modes 7.4.1 Outputs 7.4.1.1 TLV9022 and TLV9024 Open Drain Output The TLV902x features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage from 0 V up to 5.5 V, independent of the comparator supply voltage (VS). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower pull-up resistor values will help increase the rising edge risetime, but at the expense of increasing VOL and higher power dissipation. The risetime will be dependant on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the RC time constant and increase the risetime. Unused open drain outputs must be left floating, or can be tied to the V- pin if floating pins are not allowed. While an individual output can typically sink up to 125 mA, the total combined current for all channels must be less than 200 mA. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 17 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 7.4.1.2 TLV9032 and TLV9034 Push-Pull Output The TLV903x features a push-pull output stage capable of both sinking and sourcing current. This allows driving loads such as LED's and MOSFET gates, as well as eliminating the need for a power-wasting external pull-up resistor. The push-pull output must never be connected to another output. Unused push-pull outputs must be left floating, and never tied to a supply, ground, or another output. While an individual output can typically sink and source up to 100mA, the total combined current for all channels must be less than 200 mA. 7.4.2 Power-On Reset (POR) The TLV90xx has an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions. While the power supply (Vs) is ramping up or ramping down, the POR circuitry will be activated for up to 30µs after the minimum supply voltage threshold of 1.5V is crossed, or immediately when the supply voltage drops below 1.5V. When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the comparator output reflects the state of the differential input (VID). The POR circuit will keep the output high impedance (HI-Z) during the POR period (ton). Power On Reset Time (tON) 0V +1.5V VS VOH / 2 OUT VOL Figure 7-1. Power-On Reset Timing Diagram Note that it the nature of an open collector output that the output will rise with the pull-up voltage during the POR period. For the TL903x push-pull output devices, the output is "floating" during the POR period. A light pull-up (to V+) or pull-down (to V-) resistor can be used to pre-bias the output condition to prevent the output from floating. If output high is the desired start-up condition, then use the open collector TL902x, since a pull-up resistor is already required. 7.4.3 Inputs 7.4.3.1 Rail to Rail Input The TLV90xx input voltage range extends from 200mV below V- to 200 mV above V+. The differential input voltage (VID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when the input pins exceed V+ or V-. 7.4.3.2 Fault Tolerant Inputs The TLV90xx inputs are fault tolerant up to 5.5V independent of VS. Fault tolerant is defined as maintaining the same high input impedance when VS is unpowered or within the recommended operating ranges. The fault tolerant inputs can be any value between 0 V and 5.5 V, even while VS is zero or ramping up or down. This feature avoids power sequencing issues as long as the input voltage range and supply voltage are within the specified ranges. This is possible since the inputs are not clamped to V+ and the input current maintains its value even when a higher voltage is applied to the inputs. As long as one of the input pins remains within the valid input range, and the supply voltage is valid and not in POR, the output state will be correct. The following is a summary of input voltage excursions and their outcomes: 1. When both IN- and IN+ are within the specified input voltage range: a. If IN- is higher than IN+ and the offset voltage, the output is low. b. If IN- is lower than IN+ and the offset voltage, the output is high. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 2. When IN- is outside the specified input voltage range and IN+ is within the specified voltage range, the output is low. 3. When IN+ is higher than the specified input voltage range and IN- is within the specified input voltage range, the output is high 4. When IN- and IN+ are both outside the specified input voltage range, the output is indeterminate (random). Do not operate in this region. Even with the fault tolerant feature, TI strongly recommends keeping the inputs within the specified input voltage range during normal system operation to maintain datasheet specifications. Operating outside the specified input range can cause changes in specifications such as propagation delay and input bias current, which can lead to unpredictable behavior. 7.4.3.3 Input Protection The input bias current is typically 5 pA for input voltages between V+ and V-. The comparator inputs are protected from reverse voltage by the internal ESD diodes connected to V-. As the input voltage goes under V-, or above the input Absolute Maximum ratings the protection diodes become forward biased and begin to conduct causing the input bias current to increase exponentially. Input bias current typically doubles for each 10°C temperature increase. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the clamps conduct. The current should be limited 10 mA or less. This series resistance can be part of any resistive input dividers or networks. 7.4.4 ESD Protection The TLV90xx family incorporates internal ESD protection circuits on all pins. The inputs, and the open-drain output, use a proprietary "snapback" type ESD clamp from each pin to V-, which allows the pins to exceed the supply voltage (V+). While shown as Zener diodes, snapback "short" and go low impedance (like an SCR) when the threshold is exceeded, as opposed to clamping to a defined voltage like a Zener. The TLV902x open-drain output protection also consists of a ESD clamp between the output and V- to allow the output to be pulled above V+ to a maximum of 5.5V. The TLV903x push-pull output protection consists of a ESD clamp between the output and V-, but also includes a ESD diode clamp to V+, as the output must not exceed the supply rails. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents must the clamps conduct. The current must be limited 10 mA or less. This series resistance can be part of any resistive input dividers or networks. TI does not specify the performance of the ESD clamps and external clamping must be added if the inputs or output could exceed the maximum ratings as part of normal operation. 7.4.5 Unused Inputs If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on it's own internal wideband noise. Instead, the inputs must be tied to any available voltage that resides within the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input can be grounded and the other input connected to a reference voltage, or even V+ as long as the input is directly connected to the V+ pin to avoid transients). 7.4.6 Hysteresis The TLV90xx family does not have internal hysteresis. Due to the wide effective bandwidth and low input offset voltage, it is possible for the output to "chatter" (oscillate) when the absolute differential voltage near zero as the comparator triggers on it's own internal wideband noise. This is normal comparator behavior and is expected. TI recommends that the user add external hysteresis if slow moving signals are expected. See Section 8.1.2 in the following section. Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 Submit Document Feedback 19 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Basic Comparator Definitions 8.1.1.1 Operation The basic comparator compares the input voltage (VIN) on one input to a reference voltage (VREF) on the other input. In the Figure 8-1 example below, if VIN is less than VREF, the output voltage (VO) is logic low (VOL). If VIN is greater than VREF, the output voltage (VO) is at logic high (VOH). Table 8-1 summarizes the output conditions. The output logic can be inverted by simply swapping the input pins. Table 8-1. Output Conditions Inputs Condition Output IN+ > IN- HIGH (VOH) IN+ = IN- Indeterminate (chatters - see Hysteresis) IN+ < IN- LOW (VOL) 8.1.1.2 Propagation Delay There is a delay between from when the input crosses the reference voltage and the output responds. This is called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input transitions. This is shown as tpLH and tpHL in Figure 8-1 and is measured from the mid-point of the input to the midpoint of the output. VREF + 200mV V+ Input VIN VOD (+200mV) VREF + 100mV + Output ± VIN VREF + VREF GND ± VREF 5 100mV VOD (-200mV) VREF - 200mV tpLH tpHL VOH 80% Output 80% 50% 50% 20% VOL 20% tR tF Figure 8-1. Comparator Timing Diagram 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9022 TLV9032 TLV9024 TLV9034 TLV9022, TLV9032, TLV9024, TLV9034 www.ti.com SNOSDA3D – JUNE 2020 – REVISED AUGUST 2021 8.1.1.3 Overdrive Voltage The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input peak-to-peak voltage). The overdrive voltage is 100mV as shown in the Figure 8-1 example. The overdrive voltage can influence the propagation delay (tp). The smaller the overdrive voltage, the longer the propagation delay, particularly when