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TPA3221
SLASEE9B – SEPTEMBER 2017 – REVISED DECEMBER 2017
TPA3221 100-W Stereo, 200-W Mono HD-Audio, Analog-Input, Class-D Amplifier
1 Features
3 Description
•
•
•
TPA3221 is a high-power Class-D amplifier that
enables efficient operation at full-power, idle and
standby. The device features closed-loop feedback
with a bandwidth up to 100 kHz, which provides low
distortion across the audio band and delivers
excellent sound quality. The device operates with
either AD or low idle-current HEAD (High Efficient AD
mode) modulation, and can drive up to 2 x 105 W into
4-Ω load or 1 x 208 W into 2-Ω load.
1
•
•
•
•
•
•
•
•
Wide 7-V to 30-V Supply Voltage Operation
Stereo (2 x BTL) and Mono (1 x PBTL) Operation
Output Power at 10% THD+N
– 105-W Stereo into 4 Ω in BTL Configuration
– 112-W Stereo into 3 Ω in BTL Configuration
– 208-W Mono into 2 Ω in PBTL Configuration
Output Power at 1% THD+N
– 88-W Stereo into 4 Ω in BTL Configuration
– 100-W Stereo into 3 Ω in BTL Configuration
– 170-W Mono into 2 Ω in PBTL Configuration
5-V Gate Drive or Built-in LDO for Optional SingleSupply Operation
Closed-Loop Feedback Design
– Signal Bandwidth up to 100 kHz for HighFrequency Content From HD Sources
– 0.02% THD+N at 1 W into 4 Ω
– 60-dB PSRR (BTL, No Input Signal)
– 108-dB SNR (A-Weighted)
– AD or HEAD Modulation Schemes
Low-Power Operating Modes
– Standby Modes: Mute and < 1 mA Shutdown
– Low Idle-Current HEAD Modulation Scheme
– Single-Channel BTL Operation
Multiple Input Options to Simplify Pre-Amp Design
– Differential or Single-Ended Analog Inputs
– Selectable Gains: 18 dB, 24 dB, 30 dB, 34 dB
Integrated Protection: Undervoltage, Overvoltage,
Cycle-by-cycle Current Limit, Short Circuit,
Clipping Detection, Overtemperature Warning and
Shutdown, and DC Speaker Protection
90% Efficient Class-D Operation (4 Ω)
Pin-Compatible Family of Devices with Voltage
and Power-Level Options
The TPA3221 features a single-ended or differential
analog-input interface that supports up to 2 VRMS with
four selectable gains: 18 dB, 24 dB, 30 dB and 34
dB. The TPA3221 also achieves >90% efficiency, low
idle power ( 7 V)
IVDD
IAVDD
IGVDD
Total PVDD idle current, AD-mode
modulation, BTL
IPVDD
Total PVDD idle current, HEAD-mode
modulation, BTL
µA
mA
mA
ANALOG INPUTS
VIN
Maximum input voltage swing
IIN
Maximum input current
±2.8
-1
Inverting voltage Gain, VOUT/VIN(Master
Mode)
G
Inverting voltage Gain, VOUT/VIN(Slave Mode)
RIN
Input resistance
1
R1 = 5.6 kΩ, R2 = OPEN
18
R1 = 20 kΩ, R2 = 100 kΩ
24
R1 = 39 kΩ, R2 = 100 kΩ
30
R1 = 47 kΩ, R2 = 75 kΩ
34
R1 = 51 kΩ, R2 = 51 kΩ
18
R1 = 75 kΩ, R2 = 47 kΩ
24
R1 = 100 kΩ, R2 = 39 kΩ
30
R1 = 100 kΩ, R2 = 16 kΩ
34
G = 18 dB
48
G = 24 dB
24
G = 30 dB
12
G = 34 dB
7.7
V
mA
dB
kΩ
OSCILLATOR
Nominal, Master Mode
3.45
3.6
3.75
3.06
3.198
3.33
AM2, Master Mode
2.76
2.88
3
VIH
High level input voltage
1.88
VIL
Low level input voltage
fOSC(IO)
(1)
AM1, Master Mode
FPWM × 6
MHz
V
1.65
V
3.78
MHz
EXTERNAL OSCILLATOR (Slave Mode)
fOSC(IO)
CLK input on OSCM/OSCP (Slave Mode)
2.3
OUTPUT-STAGE MOSFETs
RDS(on)
(1)
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
TJ = 25 °C, Excludes metallization resistance,
GVDD = 5 V
70
mΩ
70
mΩ
Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4 : 4.5 : 5
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TPA3221
SLASEE9B – SEPTEMBER 2017 – REVISED DECEMBER 2017
www.ti.com
Electrical Characteristics (continued)
PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, TC (Case temperature) = 75 °C, fS = 600 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I/O PROTECTION
Vuvp,AVDD
Undervoltage protection limit, AVDD
Vuvp,AVDD,hyst
(2)
Vuvp,PVDD
Vuvp,PVDD,hyst
(2)
Vovp,PVDD
V
0.1
V
Undervoltage protection limit, PVDD_x
6.4
V
Undervoltage protection hysteresis, PVDD_x
0.45
V
34
V
Overvoltage protection limit, PVDD_x
Vovp,PVDD,hyst
(2)
OTW
OTWhyst
4
Undervoltage protection hysteresis, AVDD
Overvoltage protection hysteresis, PVDD_x
Overtemperature warning, OTW_CLIP
(2)
OTE (2)
0.45
(2)
115
Temperature drop needed below OTW
temperature for OTW_CLIP to be inactive
after OTW event.
125
V
135
20
Overtemperature error
145
155
°C
°C
165
°C
A reset needs to occur for FAULT to be
released following an OTE event
20
°C
OTE-OTW(differential)
OTE-OTW differential
25
°C
OLPC
Overload protection counter
1.7
ms
IOC,
BTL
10
A
IOC,
PBTL
Overcurrent limit protection, speaker output
current
20
A
BTL current imbalance threshold
1.8
A
PBTL current imbalance threshold
3.6
A
150
ns
3
mA
OTEhyst
(2)
(2)
IDCspkr, BTL
IDCspkr, PBTL
fPWM = 600 kHz (1024 PWM cycles)
DC Speaker Protection Current Threshold
Nominal peak current in 1Ω load
IOCT
Overcurrent response time
Time from switching transition to flip-state induced
by overcurrent.
IPD
Output pulldown current of each half
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
1.9
V
HEAD, OSCM, OSCP,CMUTE, RESET
0.8
V
100
μA
32
kΩ
OTW/SHUTDOWN (FAULT)
RINT_PU
Internal pullup resistance, OTW_CLIP to
AVDD, FAULT to AVDD
VOH
High level output voltage
Internal pullup resistor
3.3
3.6
V
VOL
Low level output voltage
IO = 4 mA
200
500
mV
Device fanout
OTW_CLIP, FAULT
No external pullup
30
(2)
8
20
3
26
devices
Specified by design.
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SLASEE9B – SEPTEMBER 2017 – REVISED DECEMBER 2017
7.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
VDD = 5 V, GVDD = 5 V, RL = 4 Ω, fS = 600 kHz, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, AD-Modulation,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 3 Ω, 10% THD+N
112
RL = 4 Ω, 10% THD+N
105
RL = 3 Ω, 1% THD+N
100
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded, Gain = 18 dB
|VOS|
Output offset voltage
Inputs AC coupled to GND
20
SNR
Signal-to-noise ratio (1)
A-weighted, Gain = 18 dB
108
dB
DNR
Dynamic range
A-weighted, Gain = 18 dB
109
dB
PO = 0, all outputs switching, AD-modulation,
TC = 25°C (2)
0.37
W
PO = 0, all outputs switching, HEADmodulation, TC = 25°C (2)
0.25
W
RL = 4 Ω, 1% THD+N
Pidle
(1)
(2)
Power dissipation due to idle losses (IPVDD_X)
W
88
0.02
%
75
μV
60
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
7.7 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
VDD = 5 V, GVDD = 5 V, RL = 2 Ω, fS = 600 kHz, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, Pre-Filter PBTL, ADModulation, AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
RL = 2 Ω, 10% THD+N
208
RL = 3 Ω, 10% THD+N
155
RL = 4 Ω, 10% THD+N
120
RL = 2 Ω, 1% THD+N
170
RL = 3 Ω, 1% THD+N
125
RL = 4 Ω, 1% THD+N
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
|VOS|
Output offset voltage
SNR
Signal to noise ratio
DNR
Dynamic range
Pidle
(1)
(2)
(1)
Power dissipation due to idle losses (IPVDD_X)
TYP MAX
UNIT
W
98
0.02
%
A-weighted, AES17 filter, Input Capacitor
Grounded, Gain = 18 dB
75
μV
Inputs AC coupled to GND
20
A-weighted, Gain = 18 dB
108
dB
A-weighted, Gain = 18 dB
110
dB
PO = 0, all outputs switching, ADmodulation, TC = 25°C (2)
0.20
W
PO = 0, all outputs switching, HEADmodulation, TC = 25°C (2)
0.17
W
60
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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TPA3221
SLASEE9B – SEPTEMBER 2017 – REVISED DECEMBER 2017
www.ti.com
7.8 Typical Characteristics, BTL Configuration, AD-mode
10
3:
4:
8:
1
0.1
0.01
TC = 75qC
0.001
10m
100m
1
10
Po - Output Power - W
100 200
10
1
0.1
0.01
0.001
0.0005
20
100
1k
f - Frequency - Hz
20k
D002
120
10
AUX-0025 Filter
80 kHz analyzer BW
RL = 4:, TC = 75qC
3:
3: - CB3C Limited
4:
8:
100
PO - Output Power - W
1W
10W
50W
1
0.1
0.01
80
60
40
20
THD+N = 10%
TC = 75qC
0
0.001
20
100
1k
f - Frequency - Hz
10k
5
40k
10
15
20
25
PVDD - Supply Voltage - V
30
35
D004
D003
Figure 4. Output Power vs Supply Voltage, AD-mode
120
100
3:
3: - CB3C Limited
4:
8:
100
3:
4:
8:
80
Efficiency - %
PO - Output Power - W
10k
Figure 2. Total Harmonic Distortion+Noise vs Frequency,
AD-mode
Figure 3. Total Harmonic Distortion+Noise vs Frequency,
AD-mode
60
40
20
10
THD+N = 1%
TC = 75qC
TC = 75qC
PVDD = 30V
0
5
10
15
20
25
PVDD - Supply Voltage - V
30
35
1
10m
D005
Figure 5. Output Power vs Supply Voltage, AD-mode
10
RL = 4:
TC = 75qC
1W
10W
50W
D001
Figure 1. Total Harmonic Distortion + Noise vs Output
Power, AD-mode
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, RL = 4 Ω, fS =
600 kHz, 18 dB, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, AD-Modulation, AES17 + AUX-0025
measurement filters, unless otherwise noted.
100m
1
10
2 Channel Output Power - W
100
300
D006
Figure 6. System Efficiency vs Output Power, AD-mode
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Typical Characteristics, BTL Configuration, AD-mode (continued)
100
100
Efficiency - %
Efficiency - %
3:
4:
8:
10
10
3:
4:
8:
TC = 75qC
PVDD = 24V
1
10m
100m
1
10
2 Channel Output Power - W
1
10m
100 200
50
D008
150
3:
4:
8:
125
PO - Output Power - W
Power Loss - W
10
Figure 8. System Efficiency vs Output Power, AD-mode
75
50
25
100
75
50
3:
4:
8:
25
TC = 75qC
PVDD = 30V
0
THD+N = 10%
0
0
25
50
75 100 125 150 175 200
2 Channel Output Power - W
225
250
0
25
D009
Figure 9. System Power Loss vs Output Power, AD-mode
50
75
TC - Case Temperature - qC
100
D010
Figure 10. Output Power vs Case Temperature, AD-mode
0
0
TC = 75qC
Vref = 21.21 V
FFT size = 16384
AUX-0025 filter
80kHz Analyzer BW
-40
-60
-80
-100
-120
-40
-60
-80
-100
-140
-120
-160
-140
0
5k
10k
15k
20k 25k 30k
f - Frequency - Hz
35k
40k
TC = 75qC
Pout = 1W/channel
FFT size = 16384
4:
-20
18kHz + 19kHz 1:1
4:
-20
Noise Amplitude - dB
100m
1
2 Channel Output Power - W
D007
Figure 7. System Efficiency vs Output Power, AD-mode
TC = 75qC
PVDD = 12V
45k48k
AUX-0025 filter
80kHz Analyzer BW
0
5k
D011
10k
15k
20k
25k
f - Frequency - Hz
18 kHz + 19 kHz
Figure 11. Noise Amplitude vs Frequency, AD-mode
30k
35k
40k
D012
Ratio 1 : 1
Figure 12. CCIF Intermodulation, AD-mode
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Typical Characteristics, BTL Configuration, AD-mode (continued)
0
0
TC = 75qC
Pout = 25W/channel
FFT size = 16384
4:
-40
-40
-60
-80
-60
-80
-100
-100
-120
AUX-0025 filter
80kHz Analyzer BW
-140
-120
0
5k
10k
15k
20k
25k
f - Frequency - Hz
30k
35k
40k
20
100
D013
18 kHz + 19 kHz
1k
f - Frequency - Hz
20k
D014
Figure 14. Power Supply Rejection Ratio vs Frequency, ADmode
15
0
RL = 4:, TC = 75qC
Aggressor Amplitude = 2VRMS (1W)
IPVDD - PVDD Idle Current - mA
CH2 to CH1
CH1 to CH2
-20
-40
-60
-80
-100
AD Mode
HEAD Mode
10
5
RL = 4:
TC = 25qC
-120
20
100
1k
f - Frequency - Hz
10k
20k
D015
0
5
Figure 15. Channel to Channel Crosstalk vs Frequency, ADmode
12
10k
Ratio 1 : 1
Figure 13. CCIF Intermodulation, AD-mode
Crosstalk - dBr
TC = 75qC
PSU Ripple - 250mVp-p
CH1
CH2
-20
PSRR - dB
18kHz + 19kHz 1:1
-20
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10
15
20
25
PVDD - Supply Voltage - V
30
35
D026
Figure 16. Idle Current vs Supply Voltage
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SLASEE9B – SEPTEMBER 2017 – REVISED DECEMBER 2017
7.9 Typical Characteristics, PBTL Configuration, AD-mode
10
2:
3:
4:
1
0.1
0.01
TC = 75qC
0.001
10m
100m
1
10
Po - Output Power - W
100
300
10
1
0.1
0.01
0.001
0.0005
20
100
1k
f - Frequency - Hz
10k
20k
D017
Figure 18. Total Harmonic Distortion + Noise vs Frequency,
AD-mode
225
10
AUX-0025 Filter
80 kHz analyzer BW
RL = 2:, TC = 75qC
2:
2: - CB3C Limited
3:
4:
200
PO - Output Power - W
1W
25W
100W
1
0.1
0.01
175
150
125
100
75
50
THD+N = 10%
TC = 75qC
25
0
0.001
20
100
1k
f - Frequency - Hz
10k
5
40k
10
15
20
25
PVDD - Supply Voltage - V
30
35
D019
D018
Figure 20. Output Power vs Supply Voltage, AD-mode
Figure 19. Total Harmonic Distortion+Noise vs Frequency,
AD-mode
200
100
2:
3:
4:
175
2:
3:
4:
150
Efficiency - %
PO - Output Power - W
RL = 2:
TC = 75qC
1W
25W
100W
D016
Figure 17. Total Harmonic Distortion+Noise vs Output
Power, AD-mode
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, RL = 2 Ω, fS =
600 kHz, 18 dB, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, Pre-Filter PBTL, AD Modulation, AES17 +
AUX-0025 measurement filters, unless otherwise noted.
125
100
75
10
50
25
THD+N = 1%
TC = 75qC
TC = 75qC
PVDD = 30V
0
5
10
15
20
25
PVDD - Supply Voltage - V
30
35
1
10m
D020
Figure 21. Output Power vs Supply Voltage, AD-mode
100m
1
10
2 Channel Output Power - W
100
300
D021
Figure 22. System Efficiency vs Output Power, AD-mode
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Typical Characteristics, PBTL Configuration, AD-mode (continued)
40
250
2:
3:
4:
200
PO - Output Power - W
Power Loss - W
30
20
10
150
100
50
2:
3:
4:
TC = 75qC
PVDD = 30V
0
25
50
75
100 125 150 175
2 Channel Output Power - W
200
225
0
50
75
TC - Case Temperature - qC
100
D023
Figure 24. Output Power vs Case Temperature, AD-mode
0
0
TC = 75qC
Pout = 1W/channel
FFT size = 16384
2:
-20
-40
-60
-80
-100
-120
TC = 75qC
Pout = 50W/channel
FFT size = 16384
2:
-20
18kHz + 19kHz 1:1
18kHz + 19kHz 1:1
25
D022
Figure 23. System Power Loss vs Output Power, AD-mode
-40
-60
-80
-100
-120
AUX-0025 filter
80kHz Analyzer BW
-140
AUX-0025 filter
80kHz Analyzer BW
-140
0
5k
18 kHz + 19 kHz
10k
15k
20k
25k
f - Frequency - Hz
30k
35k
40k
0
5k
D024
Ratio 1 : 1
18 kHz + 19 kHz
Figure 25. CCIF Intermodulation vs Frequency, AD-mode
14
THD+N = 10%
0
0
10k
15k
20k
25k
f - Frequency - Hz
30k
35k
40k
D025
Ratio 1 : 1
Figure 26. CCIF Intermodulation vs Frequency, AD-mode
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
9 Detailed Description
9.1 Overview
TPA3221 is designed as a feature-enhanced cost efficient high power Class-D audio amplifier. It has built-in
advanced protection circuitry to ensure maximum product robustness as well as a flexible feature set including
built in LDO for easy supply of low voltage circuitry, selectable gain, switching frequency, master/slave
synchronization of multiple devices, selectable PWM modulation scheme, mute function, temperature and
clipping status signals. TPA3221 has a bandwidth up to 100 kHz and low output noise designed for high
resolution audio applications and accepts both differential and single ended analog audio inputs at levels from 1
VRMS to 2 VRMS. With its closed loop operation TPA3221 is designed for high audio performance with a system
power supply between 7 V and 30 V.
To facilitate system design, the TPA3221 needs only a (typical) 30 V power stage supply. The TPA3221 has an
internal voltage regulator supplied from the VDD pin for the analog and digital system blocks and the output
stage gate drive respectively. The VDD pin can be connected directly to PVDD in case of only this power supply
rail available.
To reduce device power losses external 5 V supplies can be used for the AVDD and VDD supply pins. The
internal voltage regulator connected to the VDD pin is automatically turned off if using external 5 V supply for this
pin. Although supplied from the same 5 V source, separating AVDD and VDD on the printed-circuit board (PCB)
by RC filters (see application diagram for details) is recommended. These RC filters provide the recommended
high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their
associated pins as possible. In general, the physical loop with the power supply pins, decoupling capacitors and
GND return path to the device pins must be kept as short as possible and with as little area as possible to
minimize induction (see Layout Examples for additional information).
The floating supplies for the output stage high side gate drives are supplied by built-in bootstrap circuitry
requiring only an external capacitor for each half-bridge.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33 nF ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 33 nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Special attention should be paid to the power stage power supply; this includes component selection, PCB
placement, and routing.
For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X
node is decoupled with 1 μF ceramic capacitors placed as close as possible to the PVDD supply pins. It is
recommended to follow the PCB layout of the TPA3221 reference design. For additional information on
recommended power supply and required components, see the application diagrams in this data sheet.
If using external power supply for the AVDD and VDD internal regulators, this supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the 30 V power stage supply is assumed to have low output
impedance throughout the entire audio band, and low noise. The power supply sequence is not critical as
facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power supply
is settled for minimum turn on audible artefacts. Moreover, the TPA3221 is fully protected against erroneous
power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within
the specified range (see the Recommended Operating Conditions table of this data sheet).
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9.2 Functional Block Diagrams
AVDD
VDD
REGULATOR
(Auto Bypass)
RESET
VDD
AVDD
GVDD
ERROR
HANDLING
OTW_CLIP
GVDD
DIFFOC
FAULT
OVER-LOAD
PROTECTION
CURRENT
SENSE
GAIN/SLV
IOUT1_M
IOUT1_P
IOUT2_M
IOUT2_P
CB3C
PWM ACTIVITY
DETECTOR
PVDD
PPSC
HEAD
TEMP
SENSE
I/O LOGIC
CMUTE
STARTUP
CONTROL
PVDD
UVP
STARTUP & CONTROL
FREQ_ADJ
OSCM
OUT_X
POWER-UP
RESET
AVDD
OVP
OSCILLATOR
PVDD
OUTPUT DC
CONTROL
OSCP
PROTECTION
GVDD
BST1_M
PVDD
GATE-DRIVE
IN1_P
IN1_M
ANALOG
LOOP
FILTER
OUT1_M
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GND
+
OUT_1_P
GATE-DRIVE
-
PVDD
BST1_P
GVDD
CHANNEL 1
GVDD
BST2_M
PVDD
GATE-DRIVE
IN2_P
IN2_M
ANALOG
LOOP
FILTER
OUT2_M
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GND
+
OUT2_P
GATE-DRIVE
-
PVDD
GVDD
BST2_P
CHANNEL 2
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Functional Block Diagrams (continued)
FAULT
OTW_CLIP
RESET
CMUTE
System
microcontroller or
Analog circuitry
BST1_P
OSCM
Oscillator
Synchronization
BST1_M
OSCP
OUT1_P
Input
H-Bridge 1
IN1_P
Hardwire PWM
Frame Adjust
& Master/Slave
Mode
FREQ_ADJ
PVDD
GND
OUT2_M
PBTL
Detect
PVDD
2nd Order
L-C Output
Filter for
each
H-Bridge
VDD, AVDD
& GVDD
Power Supply
Decoupling
OC_ADJ
AVDD
GVDD
VDD
BST2_P
GND
HEAD
Power Supply
Decoupling
SYSTEM
Power
Supplies
Output
H-Bridge 2
Input
H-Bridge 2
IN2_P
Hardwire
Mode
Control
30 V
OUT2_P
PVDD
ANALOG_IN2_P
OUT1_M
2nd Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
IN2_M
Input DC
Blocking
Caps
ANALOG_IN2_M
GND
ANALOG_IN1_P
Output
H-Bridge 1
IN1_M
Input DC
Blocking
Caps
ANALOG_IN1_M
Bootstrap
Capacitors
BST2_M
Bootstrap
Capacitors
Hardwire
OverCurrent
Limit
GND
5 V or 7-30 V
VDD (5 V or 7-30 V)
VAC
*NOTE1: Logic AND in or outside microcontroller
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Figure 27. System Block Diagram
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9.3 Feature Description
9.3.1 Internal LDO
TPA3221 has a built in optional LDO (Low dropout voltage regulator) to supply the analog and digital circuits as
well as the gate drive for the output stages. The LDO can be used in systems where only the high voltage power
rail is available, hence no additional power supply rails need to be generated for the TPA3221 to operate. As
being a linear regulator, the LDO will add to the power losses of the device due to the (PVDD-5V) voltage drop
and the supply current for AVDD and GVDD given in the Electrical Characteristics table.
VDD
+7V”PVDD
470uF
100nF
GND
AVDD
3R3
1µF
5V LDO
GVDD
TPA322x
1µF
Figure 28. Internal LDO for Single Supply Systems
When using the internal LDO in TPA3221 the VDD terminal should be connected to a voltage source between
7V and PVDD. In a single supply system the VDD terminal should be connected directly to the PVDD terminal.
The LDO output is connected to the AVDD terminal, and can be used to supply the gate drive by supplying the
GVDD from AVDD through a RC filter for best noise performance as shown in Figure 28.
+5V
VDD
470uF
100nF
GND
5V LDO
AVDD
3R3
1µF
GVDD
TPA322x
1µF
Figure 29. Internal LDO Bypass for Highest Power Efficiency
For highest system power efficiency the LDO can be bypassed by connecting VDD to an external 5 V supply. In
this configuration AVDD and GVDD should be supplied by 5 V from the external power supply. GVDD should be
supplied through a RC filter for best noise performance as shown in Figure 29.
9.3.1.1 Input Configuration, Gain Setting And Master / Slave Operation
TPA3221 is designed to accept either a differential or a single-ended audio input signal. To accept a wide range
of system front ends TPA3221 has selectable input gain that allows full scale output with a wide range of input
signal levels.
Best system noise performance is obtained with balanced audio interface. However, to be used in systems with
only a single ended audio input signal available, one input terminal can be connected to AC ground, to accept
single ended audio input signals.
IN1_P
IN1_M
IN2_P
IN2_M
IN1_P
IN1_M
IN2_P
IN2_M
+
-
+
-
TPA322x
Figure 30. Balanced Audio Input Configuration
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Feature Description (continued)
In systems with single ended audio inputs the device gain will typically need to be set higher than for systems
with balanced audio input signals.
IN1_P
IN1
IN1_M
IN2_P
IN2
IN2_M
+
-
+
-
TPA322x
Figure 31. Single Ended Audio Input Configuration
9.3.2 Gain Setting And Master / Slave Operation
The gain of TPA3221 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode
is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets
the GAIN in Master mode in gains of 18, 24, 30, 34 dB respectively, while the next four stages sets the GAIN in
Slave mode in gains of 18, 24, 30, 34 dB respectively. The gain setting is latched when RESET goes high and
cannot be changed while RESET is high. Table 2 shows the recommended resistor values, the state and gain:
Table 2. Gain and Master / Slave
Master / Slave
Mode
Gain
R1 (to GND)
R2 (to AVDD)
Differential Input Signal Level
(each input pin)
Single Ended Input Signal
Level
Master
18 dB
Master
24 dB
5.6 kΩ
OPEN
2 VRMS
2 VRMS
20 kΩ
100 kΩ
1 VRMS
Master
2 VRMS
30 dB
39 kΩ
100 kΩ
0.5 VRMS
1 VRMS
Master
34 dB
47 kΩ
75 kΩ
0.32 VRMS
0.63 VRMS
Slave
18 dB
51 kΩ
51 kΩ
2 VRMS
2 VRMS
Slave
24 dB
75 kΩ
47 kΩ
1 VRMS
2 VRMS
Slave
30 dB
100 kΩ
39 kΩ
0.5 VRMS
1 VRMS
Slave
34 dB
100 kΩ
16 kΩ
0.32 VRMS
0.63 VRMS
AVDD
AVDD
R2
GAIN/SLV
TPA322x
R1
GND
Figure 32. Gain and Master / Slave Setup
For easy multi-channel system design TPA3221 has a Master / Slave feature that allows automatic
synchronization of multiple slave devices operated at the PWM switching frequency of a master device. This
benefits system noise performance by eliminating spurious crosstalk sum and difference tones due to
unsynchronized channel-to-channel switching frequencies. Furthermore the Master / Slave scheme is designed
to interleave switching of the individual channels in a multi-channel system such that the power supply current
ripple frequency is moved to a higher frequency which reduces the RMS ripple current in the power supply bulk
capacitors.
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The Master / Slave scheme and the interleaving of the output stage switching is automatically configured by
connecting the OSCx pins between a master and multiple slave devices. Connect the OSCx pins in either
positive or negative polarity to configure either a Slave1 or Slave2 device. Connect the OSCM of the Master
device to the OSCM of a slave device to configure for Slave1 or OSCP to configure for Slave2. Then connect the
remaining OSCx pins between the master and slave devices. The Master, Slave1 and Slave2 PWM switching will
be 30 degrees out of phase with each other. All switching channels are automatically synchronized by releasing
/RESET on all devices at the same time.
AVDD
47k
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
47k
OSCM
OSCP
OSCM
OSCP
OSCM
OSCP
TPA322x
TPA322x
TPA322x
TPA322x
TPA322x
TPA322x
TPA322x
SLAVE1
SLAVE2
SLAVE1
MASTER
SLAVE2
SLAVE1
SLAVE2
RESET
RESET
RESET
RESET
RESET
RESET
RESET
Figure 33. Gain and Master PCB Implementation
Placement on the PCB and connection of multiple TPA3221 devices in a multi channel system is illustrated in
Figure 33. Slave devices should be placed on either side of the master device, with a Slave1 device on one side
of the Master device, and a Slave2 device on the other. In systems with more than 3 TPA3221 devices, the
master should be in the middle, and every second slave devices should be a Slave1 or Slave 2 as illustrated in
Figure 33. A 47kΩ pull up resistor to AVDD should be connected to the master device OSCM output and a 47kΩ
pull down resistor to GND should be connected to the master OSCP CLK outputs.
9.3.3 AD-Mode and HEAD-Mode PWM Modulation
TPA3221 has the option of using either AD-Mode or HEAD-Mode PWM modulation scheme. AD mode has
continuous switching of the two half bridge outputs in each BTL output channel. Both half bridge outputs are
switching in HEAD mode, but with reduced duty cycle for idle operation and while playing small signals. With
higher output levels one half bridge stops switching on HEAD mode operation. HEAD benefits both device power
loss and EMI performance, where AD mode is considered to have the highest audio performance.
SPACE
HEAD
HEAD
AVDD
AVDD
TPA322x
TPA322x
Figure 34. AD-Mode Configuration
Figure 35. HEAD-Mode Configuration
OUTP
0V
OUTN
0V
OUTP Current
0A
OUTN Current
0A
Figure 36. AD Mode Output Waveforms, Idle
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OUTP
0V
OUTN
0V
OUTP Current
>0A
OUTN Current
0A
OUTP Current
OUTN Current
1.7 ms)
(1)
CB3C
OC Limiting
Channel
None
Self Clearing
Reduce signal level
or remove short
Stuck at Fault (1)
No OSC_IO activity
in Slave Mode
Global
None
Self Clearing
Resume OSC_IO
activity
Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
TPA3221 can be configured either in stereo BTL, mono BTL or mono PBTL mode depending on output power
conditions and system design.
10.2 Typical Applications
10.2.1 Stereo BTL Application
+5V
470uF
100nF
33nF
1
5.6k
2
3
/OTW_CLIP
4
/FAULT
5
6
7
1µF
8
IN1_P
1µF
IN1_M
9
10
/RESET
11
12
13
50k
14
1µF
15
IN2_P
1µF
IN2_M
16
17
18
CMUTE
CMUTE
19
1k
33nF
20
21
+5V
3R3
1µF
22
VDD
BST1_P
GAIN/SLV
BST1_M
OTW_CLIP
GND
FAULT
GND
GND
OUT1_P
GND
OUT1_P
GND
PVDD
IN1_P
PVDD
IN1_M
PVDD
RESET
HEAD
OSCM
OSCP
OUT1_M
TPA322x
GND
GND
OUT2_P
FREQ_ADJ
PVDD
IN2_P
PVDD
IN2_M
PVDD
CMUTE
OUT2_M
GND
OUT2_M
GND
GND
GND
GND
AVDD
BST2_P
GVDD
BST2_M
1µF
44
10µH
43
10nF
42
33nF
1nF
1µF
41
3R3
40
1µF
39
38
1nF
37
3R3
10nF
1µF
10µH
470uF
36
PVDD
35
34
1µF
GND
33
32
1µF
31
30
10µH
1µF
470uF
10nF
29
1nF
28
1µF
3R3
27
1µF
26
1nF
25
3R3
10nF
33nF
24
10µH
23
33nF
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Figure 50. Typical Differential (2N) AD-Mode BTL Application
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Typical Applications (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters in Table 7.
Table 7. Design Requirements, BTL Application
DESIGN PARAMETER
EXAMPLE
ExternalLow Power Supply
5V
High Power Supply
7 - 30 V
IN1_M = ±2.8V (peak, max)
IN1_P = ±2.8V (peak, max)
Analog Inputs
IN2_M = ±2.8V (peak, max)
IN2_P = ±2.8V (peak, max)
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
3-8Ω
10.2.1.2 Detailed Design Procedures
A rising-edge transition on RESET input allows the device to execute the startup sequence and starts switching.
A toggling OTW_CLIP signal is indicating that the output is approaching clipping. The signal can be used either
to decrease audio volume or to control an intelligent power supply nominally operating at a low rail adjusting to a
higher supply rail.
The device inverts the audio signal from input to output.
The AVDD pin is not recommended to be used as a voltage source for external circuitry when internal LDO is
enabled (VDD ≥ 7 V).
10.2.1.2.1 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50 V is required for use with a 30 V power
supply.
10.2.1.2.2 PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 470 μF, 50 V supports most applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.2.3 BST capacitors
To ensure large enough bootstrap energy storage for the high side gate drive to work correctly with all audio
source signals, 33 nF / 50V X7R BST capacitors are recommended.
10.2.1.2.4 PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3221. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
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10.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
TPA3221 can be configured in mono PBTL mode by paralleling the outputs before the LC filter or after the LC
filter (see Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)). Paralleled
outputs before the LC filter is recommended for better performance and limiting the number of output LC filter
inductors,
+5V
470uF
100nF
33nF
1
5.6k
2
3
/OTW_CLIP
4
/FAULT
5
6
7
1µF
8
IN1_P
1µF
IN1_M
9
10
/RESET
11
12
13
50k
14
15
16
17
18
CMUTE
CMUTE
19
1k
33nF
20
21
+5V
3R3
1µF
22
VDD
BST1_P
GAIN/SLV
BST1_M
OTW_CLIP
GND
FAULT
GND
GND
OUT1_P
GND
OUT1_P
GND
PVDD
IN1_P
PVDD
IN1_M
PVDD
RESET
HEAD
OSCM
OUT1_M
TPA322x
OSCP
GND
GND
OUT2_P
FREQ_ADJ
PVDD
IN2_P
PVDD
IN2_M
PVDD
CMUTE
OUT2_M
GND
OUT2_M
GND
GND
GND
GND
AVDD
BST2_P
GVDD
BST2_M
1µF
44
43
42
33nF
41
40
39
38
PVDD
1µF
37
470uF
10µH
36
10nF
1nF
35
1µF
34
470nF
470nF
470nF
470nF
3R3
33
1nF
1µF
32
3R3
10nF
31
10µH
30
1µF
470uF
29
GND
28
27
26
25
33nF
24
23
33nF
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Figure 51. Typical Differential (2N) AD-Mode PBTL Application
10.2.2.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 8. Design Requirements, PBTL Application
DESIGN PARAMETER
EXAMPLE
Low Power Supply
5V
High Power Supply
7 - 30 V
IN1_M = ±2.8 V (peak, max)
IN1_P = ±2.8 V (peak, max)
Analog Inputs
IN2_M = Grounded
IN2_P = Grounded
32
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
2-4Ω
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10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
TPA3221 can be configured in mono PBTL mode by paralleling the outputs before the LC filter (see Typical
Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)) or after the LC filter.
Paralleled outputs after the LC filter may be preferred if: a single board design must support both PBTL and BTL,
or in the case multiple, smaller paralleled inductors are preferred due to size or cost. Paralleling after the LC filter
requires four inductors, one for each OUT_x. This section shows an example of paralleled outputs after the LC
filter.
+5V
470uF
100nF
33nF
1
5.6k
2
3
/OTW_CLIP
4
/FAULT
5
6
7
1µF
8
IN1_P
1µF
IN1_M
9
10
/RESET
11
12
13
50k
14
15
16
17
18
CMUTE
CMUTE
19
1k
33nF
20
21
+5V
3R3
1µF
22
VDD
BST1_P
GAIN/SLV
BST1_M
OTW_CLIP
GND
FAULT
GND
GND
OUT1_P
GND
OUT1_P
GND
PVDD
IN1_P
PVDD
IN1_M
PVDD
RESET
HEAD
OUT1_M
TPA322x
OSCM
OSCP
GND
GND
OUT2_P
FREQ_ADJ
PVDD
IN2_P
PVDD
IN2_M
PVDD
CMUTE
OUT2_M
GND
OUT2_M
GND
GND
GND
GND
AVDD
BST2_P
GVDD
BST2_M
1µF
44
10µH
43
42
33nF
41
40
39
38
PVDD
1µF
37
10µH
470uF
36
10nF
1nF
35
34
1µF
1µF
3R3
33
32
1µF
1nF
1µF
3R3
10nF
31
30
10µH
1µF
470uF
29
GND
28
27
26
25
33nF
24
10µH
23
33nF
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Figure 52. Typical Differential (2N) AD-Mode PBTL Application
10.2.3.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 9. Design Requirements, PBTL Application
DESIGN PARAMETER
EXAMPLE
Low Power Supply
5V
High Power Supply
7 - 30 V
IN1_M = ±2.8 V (peak, max)
IN1_P = ±2.8 V (peak, max)
Analog Inputs
IN2_M = Grounded
IN2_P = Grounded
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
2-4Ω
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11 Power Supply Recommendations
11.1 Power Supplies
The TPA3221 device requires a single external power supply for proper operation. A high-voltage supply, PVDD,
is required to power the output stage of the speaker amplifier and its associated circuitry. PVDD can be used to
supply an internal LDO to supply 5 V to AVDD and GVDD (connect VDD to PVDD).
Additionally, in LDO bypass mode an external power supply should be connected to VDD, AVDD and GVDD to
power the gate-drive and other internal digital and analog circuit blocks in the device.
The allowable voltage range for both the PVDD and VDD/AVDD/GVDD supplies are listed in the Recommended
Operating Conditions table. Ensure both the PVDD and the VDD/AVDD/GVDD supplies can deliver more current
than listed in the Electrical Characteristics table.
11.1.1 VDD Supply
VDD can be connected to PVDD in systems using only a single power supply. VDD is connected to an internal
LDO that is then used to supply AVDD and GVDD for digital and analog circuits as well as to supply the gate
drive.
To reduce device power consumption, the internal LDO can be bypassed by connecting VDD, AVDD and GVDD
to an external 5 V power supply.
Proper connection, routing, and decoupling techniques are highlighted in the TPA3221 device EVM User's Guide
(as well as the Application Information section and Layout Examples section) and must be followed as closely as
possible for proper operation and performance. Deviation from the guidance offered in the TPA3221 device EVM
User's Guide, which followed the same techniques as those shown in the Application Information section, may
result in reduced performance, errant functionality, or even damage to the TPA3221 device. To simplify the
power supply requirements for the system, the TPA3221 device includes a integrated low-dropout (LDO) linear
regulator to create a 5V rail for AVDD and GVDD supplies. The linear regulator is internally connected to the
VDD supply and its output is present on the AVDD pin, providing a connection point for an external bypass
capacitors. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuitry. Additional loading on these pins could cause the voltage to sag and increase noise injection, which
negatively affects the performance and operation of the device.
11.1.2 AVDD and GVDD Supplies
AVDD and GVDD can be supplied either through the internal LDO or from external 5 V power supply to power
internal analog and digital circuits and the gate-drives for the output H-bridges. Proper connection, routing, and
decoupling techniques are highlighted in the TPA3221 device EVM User's Guide (as well as the Application
Information section and Layout Examples section) and must be followed as closely as possible for proper
operation and performance. Deviation from the guidance offered in the TPA3221 device EVM User's Guide,
which followed the same techniques as those shown in the Application Information section, may result in reduced
performance, errant functionality, or even damage to the TPA3221 device.
11.1.3 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3221 device EVM User's Guide (as well as the Application Information section and Layout
Examples section) and must be followed as closely as possible for proper operation and performance. Due the
high-voltage switching of the output stage, it is particularly important to properly decouple the output power
stages in the manner described in the TPA3221 device EVM User's Guide. The lack of proper decoupling, like
that shown in the EVM User's Guide, can results in voltage spikes which can damage the device, or cause poor
audio performance and device shutdown faults.
34
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Power Supplies (continued)
11.1.4 BST Supply
TPA3221 has built-in bootstrap supply for each half bridge gate drive to supply the high side MOSFETs, only
requiring a single capacitor per half bridge. The capacitors are connected to each half bridge output, and are
charged by the GVDD supply via an internal diode while the PWM outputs are in low state. The high side gate
drive is supplied by the voltage across the BST capacitor while the output PWM is high. It is recommended to
place the BST capacitors close to the TPA3221 device, and to keep PCB routing traces at minimum length.
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
PCB layout, audio performance and EMI are linked closely together.
Routing the audio input should be kept short and together with the accompanied audio source ground.
The small bypass capacitors on the PVDD lines should be placed as close the PVDD pins as possible.
A local ground area underneath the device is important to keep solid to minimize ground bounce.
Orient the passive component so that the narrow end of the passive component is facing the TPA3221
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
Avoid placing other heat producing components or structures near the TPA3221 device.
Avoid cutting off the flow of heat from the TPA3221 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in Figure 53.
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12.2 Layout Examples
12.2.1 BTL Application Printed Circuit Board Layout Example
T3
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
T2
20
25
21
24
22
23
T2
T2
T2
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 53. BTL Application Printed Circuit Board - Composite
36
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Layout Examples (continued)
12.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
T3
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
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13
32
14
31
15
30
16
29
17
28
18
27
19
26
T2
T2
T2
20
25
21
24
22
23
T2
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 54. PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board - Composite
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Layout Examples (continued)
12.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
T3
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T2
T2
T2
T2
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
ote T3: Heat sink needs to have a good connection to PCB ground.
Figure 55. PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board - Composite
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13 Device and Documentation Support
13.1 Documentation Support
TPA3221 Evaluation Module User's Guide
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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39
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA3221DDV
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
3221
TPA3221DDVR
ACTIVE
HTSSOP
DDV
44
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
3221
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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