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TPA3255
SLASEA8A – FEBRUARY 2016 – REVISED OCTOBER 2016
TPA3255 315-W Stereo, 600-W Mono PurePath™ Ultra-HD Analog-Input
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Differential Analog Inputs
Total Output Power at 10%THD+N
– 315-W Stereo into 4 Ω in BTL Configuration
– 185-W Stereo into 8 Ω in BTL Configuration
– 600-W Mono into 2 Ω in PBTL Configuration
Total Output Power at 1%THD+N
– 260-W Stereo into 4 Ω in BTL Configuration
– 150-W Stereo into 8 Ω in BTL Configuration
– 480-W Mono into 2 Ω in PBTL Configuration
Advanced Integrated Feedback Design with Highspeed Gate Driver Error Correction
(PurePath™ Ultra-HD)
– Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources
– Ultra Low 0.006% THD+N at 1 W into 4 Ω and
65 dB PSRR (BTL, 1 kHz, No Input Signal)
– 111 dB (A Weighted) SNR
Multiple Configurations Possible:
– Stereo, Mono, 2.1 and 4xSE
Click and Pop Free Startup and Stop
90% Efficient Class-D Operation (4 Ω)
Wide 18-V to 53.5V Supply Voltage Operation
Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short Circuit
Protection) With Error Reporting
EMI Compliant When Used With Recommended
System Design
Blu-Ray Disc™ / DVD Receivers
High End HTiB Systems
AV Receivers
High End Soundbar
Mini Combo Systems
Active Speakers and Subwoofers
3 Description
TPA3255 is a high performance class-D power
amplifier that enables true premium sound quality
with class-D efficiency. It features an advanced
integrated feedback design and proprietary highspeed gate driver error correction (PurePath™ UltraHD). This technology allows ultra low distortion
across the audio band and superior audio quality.
The device is operated in AD-mode, and can drive up
to 2 x 315 W into 4-Ω load at 10% THD and 2 x 150
W unclipped into 8-Ω load and features a 2 VRMS
analog input interface that works seamlessly with high
performance DACs such as TI's PCM5242. In
addition to excellent audio performance, TPA3255
achieves both high power efficiency and very low
power stage idle losses below 2.5W. This is achieved
through the use of 85 mΩ MOSFETs and an
optimized gate driver scheme that achieves
significantly lower idle losses than typical discrete
implementations.
Device Information(1)
PART NUMBER
TPA3255
Audio
Source
And Control
LC
Filter
TAS5630
LEFT
/CLIP_OTW
LC
Filter
/RESET
/FAULT
12V
Operation Mode Select
Switching Frequency Select
Master/Slave Synchronization
6.10 mm x 14.00 mm
Total Harmonic Distortion
M1:M2
Power Supply
FREQ_ADJ
51V
OSC_IO
110VAC->240VAC
Copyright © 2016, Texas Instruments Incorporated
THD+N - Total Harmonic Distortion + Noise - %
TPA3255D2
HTSSOP (44)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
RIGHT
PACKAGE
10
4:
8:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
1
10
Po - Output Power - W
100
400
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3255
SLASEA8A – FEBRUARY 2016 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
9
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Audio Characteristics (BTL) ...................................... 8
Audio Characteristics (SE) ....................................... 9
Audio Characteristics (PBTL) ................................... 9
Typical Characteristics, BTL Configuration............. 10
Typical Characteristics, SE Configuration............. 12
Typical Characteristics, PBTL Configuration ........ 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagrams ..................................... 15
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Applications .............................................. 22
11 Power Supply Recommendations ..................... 29
11.1
11.2
11.3
11.4
Power Supplies .....................................................
Powering Up..........................................................
Powering Down .....................................................
Thermal Design.....................................................
29
30
31
31
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
12.2 Layout Examples................................................... 34
13 Device and Documentation Support ................. 37
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
14 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Original (February 2016) to Revision A
•
2
Page
Changed the device status From: PRODUCT PREVIEW To: Production Data..................................................................... 1
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SLASEA8A – FEBRUARY 2016 – REVISED OCTOBER 2016
5 Device Comparison Table
DEVICE NAME
DESCRIPTION
TPA3244
40-W Stereo, 100-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
TPA3245
100-W Stereo, 200-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
TPA3250
70-W Stereo, 130-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
TPA3251
175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
6 Pin Configuration and Functions
The TPA3255 is available in a thermally enhanced TSSOP package.
The package type contains a PowerPAD™ that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DDV Package
HTSSOP 44-Pin
(Top View)
GVDD_AB
1
44
BST_A
VDD
2
43
BST_B
M1
3
42
GND
M2
4
41
GND
INPUT_A
5
40
OUT_A
INPUT_B
6
39
OUT_A
OC_ADJ
7
38
PVDD_AB
FREQ_ADJ
8
37
PVDD_AB
OSC_IOM
9
36
PVDD_AB
OSC_IOP
10
35
OUT_B
DVDD
11
Thermal
Pad
34
GND
GND
12
33
GND
GND
13
32
OUT_C
AVDD
14
31
PVDD_CD
C_START
15
30
PVDD_CD
INPUT_C
16
29
PVDD_CD
INPUT_D
17
28
OUT_D
RESET
18
27
OUT_D
FAULT
19
26
GND
VBG
20
25
GND
CLIP_OTW
21
24
BST_C
GVDD_CD
22
23
BST_D
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SLASEA8A – FEBRUARY 2016 – REVISED OCTOBER 2016
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Pin Functions
NAME
NO.
I/O
AVDD
14
P
Internal voltage regulator, analog section
BST_A
44
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B
43
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C
24
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D
23
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW
21
O
Clipping warning and Over-temperature warning; open drain; active low. Do not connect if not used.
C_START
15
O
Startup ramp, requires a charging capacitor to GND
DVDD
11
P
Internal voltage regulator, digital section
FAULT
19
O
Shutdown signal, open drain; active low. Do not connect if not used.
FREQ_ADJ
8
O
Oscillator freqency programming pin
12, 13, 25, 26,
33, 34, 41, 42
P
GVDD_AB
1
P
Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD
22
P
Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A
5
I
Input signal for half bridge A
INPUT_B
6
I
Input signal for half bridge B
INPUT_C
16
I
Input signal for half bridge C
INPUT_D
17
I
Input signal for half bridge D
M1
3
I
Mode selection 1 (LSB)
M2
4
I
Mode selection 2 (MSB)
OC_ADJ
7
I/O
Over-Current threshold programming pin
OSC_IOM
9
I/O
Oscillator synchronization interface. Do not connect if not used.
OSC_IOP
10
O
Oscillator synchronization interface. Do not connect if not used.
OUT_A
39, 40
O
Output, half bridge A
OUT_B
35
O
Output, half bridge B
OUT_C
32
O
Output, half bridge C
OUT_D
27, 28
O
Output, half bridge D
PVDD_AB
36, 37, 38
P
PVDD supply for half-bridge A and B
PVDD_CD
29, 30, 31
P
PVDD supply for half-bridge C and D
RESET
18
I
Device reset Input; active low
VDD
2
P
Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG
20
P
Internal voltage reference requires a 1-µF capacitor to GND for decoupling.
P
Ground, connect to grounded heat sink
GND
PowerPad™
DESCRIPTION
Ground
Table 1. Mode Selection Pins
MODE
PINS (1)
INPUT
MODE (2)
OUTPUT
CONFIGURATION
M2
M1
0
0
2N + 1
2 × BTL
0
1
2N/1N + 1
1 x BTL + 2 x SE
1
(1)
(2)
4
0
1
2.1 BTL + SE mode. Channel AB: BTL, channel C + D: SE
INPUT_C
INPUT_D
0
0
1 x BTL
Mono BTL configuration. BTL channel AB active,
channel CD not switching. Connect INPUT_C to DVDD
and INPUT_D to GND. (1)
1
0
4 x SE
Single ended output configuration
2N + 1
1N +1
Stereo BTL output configuration
Parallelled BTL configuration. Connect INPUT_C and
INPUT_D to GND. (1)
1 x PBTL
1
DESCRIPTION
1 refers to logic high (DVDD level), 0 refers to logic low (GND).
2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control (RESET) input pins.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MIN
MAX
UNIT
BST_X to GVDD_X (2)
–0.3
69
V
VDD to GND
–0.3
13.2
V
GVDD_X to GND (2)
–0.3
13.2
V
PVDD_X to GND (2)
–0.3
69
V
DVDD to GND
–0.3
4.2
V
AVDD to GND
–0.3
8.5
V
VBG to GND
-0.3
4.2
V
(2)
–0.3
69
V
BST_X to GND (2)
–0.3
81.5
V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND
–0.3
4.2
V
RESET, FAULT, CLIP_OTW to GND
–0.3
4.2
V
INPUT_X to GND
–0.3
7
V
9
mA
0
150
°C
–40
150
°C
OUT_X to GND
Interface pins
(1)
Continuous sink current, RESET, FAULT, CLIP_OTW to GND
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
7.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLASEA8A – FEBRUARY 2016 – REVISED OCTOBER 2016
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
51
53.5
18
53.5
56.5
10.8
12
13.2
V
10.8
12
13.2
V
3.4
4
1.7
3
1.7
2
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
VDD
Digital regulator supply voltage
DC supply voltage
RL(BTL)
Output filter inductance within
recommended value range
RL(PBTL)
LOUT(BTL)
Output filter inductance
Minimum output inductance at IOC
5
CPVDD
PWM frame rate programming resistor
Nominal
430
450
470
AM1
475
500
525
AM2
575
600
625
Nominal; Master mode
29.7
30
30.3
AM1; Master mode
19.8
20
20.2
AM2; Master mode
9.9
10
10.1
Resistor tolerance = 5%, RL = 4Ω
22
PVDD close decoupling capacitors
ROC
Over-current programming resistor
ROC(LATCHED)
Over-current programming resistor
V(FREQ_ADJ)
Voltage on FREQ_ADJ pin for slave
mode operation
TJ
Junction temperature
1
kHz
kΩ
μF
30
Resistor tolerance = 5%, RL ≥ 6Ω, PVDD
= 53.5V (1)
kΩ
30
Resistor tolerance = 5%, RL = 4Ω
(1)
μH
5
PWM frame rate selectable for AM
interference avoidance; 1% Resistor
tolerance
R(FREQ_ADJ)
Ω
5
LOUT(PBTL)
FPWM
V
18
GVDD_x
LOUT(SE)
UNIT
DC supply voltage, RL ≥ 6Ω (1)
Half-bridge supply
Load impedance
MAX
DC supply voltage, RL = 4Ω
PVDD_x
RL(SE)
TYP
47
64
Resistor tolerance = 5%, RL ≥ 6Ω, PVDD
= 53.5V (1)
64
Slave mode
3.3
0
kΩ
V
125
°C
For load impedance ≥ 6Ω PVDD can be increased, provided a reduced over-current threshold is set
7.4 Thermal Information
TPA3255
DDV 44-PINS HTSSOP
THERMAL METRIC (1)
JEDEC STANDARD
4 LAYER PCB
FIXED 85°C
HEATSINK
TEMPERATURE (2)
RθJA
Junction-to-ambient thermal resistance
50.7
2.4 (2)
RθJC(top)
Junction-to-case (top) thermal resistance
0.36
0.3
RθJB
Junction-to-board thermal resistance
24.4
n/a
ψJT
Junction-to-top characterization parameter
0.19
0.5
ψJB
Junction-to-board characterization parameter
24.2
n/a
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
(1)
(2)
6
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil
thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the
heatsink.
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7.5 Electrical Characteristics
PVDD_X = 51 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD
Voltage regulator, only used as reference
node
VDD = 12 V
AVDD
Voltage regulator, only used as reference
node
VDD = 12 V
IVDD
VDD supply current
IGVDD_X
Gate-supply current per full-bridge
IPVDD_X
PVDD idle current per full bridge
7.75
V
V
Operating, 50% duty cycle
30
Idle, reset mode
14
50% duty cycle
44
Reset mode
5
50% duty cycle with recommended output filter
24
mA
Reset mode, No switching
5
mA
VDD = 0V, GVDD_X = 0V
1.25
mA
mA
mA
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage swing, peak - peak
20
7
V
IIN
Maximum input current
1
mA
G
Inverting voltage Gain
VOUT/VIN
kΩ
21.5
dB
OSCILLATOR
Nominal, Master Mode
2.58
2.7
2.82
2.85
3
3.15
AM2, Master Mode
3.45
3.6
3.75
VIH
High level input voltage
1.86
VIL
Low level input voltage
fOSC(IO+)
AM1, Master Mode
FPWM × 6
MHz
V
1.45
V
85
100
mΩ
85
100
mΩ
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, Includes metallization resistance,
GVDD = 12 V
I/O PROTECTION
Vuvp,VDD,GVDD
Vuvp,VDD,
GVDD,hyst
V
0.6
V
Undervoltage protection limit, PVDD_x
14.5
V
(1)
1.4
Overtemperature warning, CLIP_OTW (1)
OTW
OTWhyst
8.7
(1)
Vuvp,PVDD
Vuvp,PVDD,hyst
Undervoltage protection limit, GVDD_x and
VDD
(1)
OTE (1)
110
Temperature drop needed below OTW
temperature for CLIP_OTW to be inactive
after OTW event.
120
V
130
20
Overtemperature error
140
150
°C
°C
160
°C
A reset needs to occur for FAULT to be
released following an OTE event
15
°C
OTE-OTW(differential)
(1)
OTE-OTW differential
30
°C
OLPC
Overload protection counter
fPWM = 450 kHz (1024 PWM cycles)
2.3
ms
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 22 kΩ
17
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 30 kΩ
13
Resistor – programmable, peak current in 1Ω load,
ROCP = 47kΩ
17
Resistor – programmable, peak current in 1Ω load,
ROCP = 64kΩ
13
DC Speaker Protection Current Threshold
BTL current imbalance threshold
1.5
A
Overcurrent response time
Time from switching transition to flip-state induced
by overcurrent.
150
ns
OTEhyst
(1)
IOC
Overcurrent limit protection
IOC(LATCHED)
IDCspkr
IOCT
(1)
Overcurrent limit protection
A
A
Specified by design.
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Electrical Characteristics (continued)
PVDD_X = 51 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
IPD
TEST CONDITIONS
MIN
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
Output pulldown current of each half
TYP
MAX
3
UNIT
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
1.9
M1, M2, OSC_IOP, OSC_IOM, RESET
V
0.8
V
100
μA
OTW/SHUTDOWN (FAULT)
RINT_PU
Internal pullup resistance, CLIP_OTW to
DVDD, FAULT to DVDD
VOH
High level output voltage
Internal pullup resistor
VOL
Low level output voltage
Device fanout
CLIP_OTW, FAULT
20
26
32
kΩ
3
3.3
3.6
V
IO = 4 mA
10
500
No external pullup
30
mV
devices
7.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER
PO
Power output per channel
THD+N
TEST CONDITIONS
MIN
TYP MAX
RL = 4 Ω, 10% THD+N
315
RL = 6 Ω, 10% THD+N, PVDD = 53.5V
250
RL = 8 Ω, 10% THD+N, PVDD = 53.5V
195
RL = 4 Ω, 1% THD+N
255
RL = 6 Ω, 1% THD+N, PVDD = 53.5V
200
RL = 8 Ω, 1% THD+N, PVDD = 53.5V
155
UNIT
W
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
|VOS|
Output offset voltage
Inputs AC coupled to GND
SNR
Signal-to-noise ratio (1)
112
dB
DNR
Dynamic range
113
dB
Pidle
Power dissipation due to Idle losses (IPVDD)
2.5
W
(1)
(2)
8
PO = 0, 4 channels switching (2)
0.006%
85
15
μV
60
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
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7.7 Audio Characteristics (SE)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V,
GVDD_X = 12 V, RL = 2 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
MIN
148
RL = 3 Ω, 10% THD+N, PVDD = 53.5V
120
RL = 4 Ω, 10% THD+N, PVDD = 53.5V
Power output per channel
TYP MAX
RL = 2 Ω, 10% THD+N
95
RL = 2 Ω, 1% THD+N
120
RL = 3 Ω, 1% THD+N, PVDD = 53.5V
UNIT
W
98
RL = 4 Ω, 1% THD+N, PVDD = 53.5V
77
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
160
μV
SNR
Signal to noise ratio (1)
A-weighted
101
dB
DNR
Dynamic range
A-weighted
101
dB
Pidle
Power dissipation due to idle losses (IPVDD)
PO = 0, 4 channels switching (2)
2
W
(1)
(2)
0.04%
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
7.8 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V,
GVDD_X = 12 V, RL = 2 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
605
RL = 3 Ω, 10% THD+N, PVDD = 53.5V
500
RL = 4 Ω, 10% THD+N, PVDD = 53.5V
390
RL = 2 Ω, 1% THD+N
495
RL = 3 Ω, 1% THD+N, PVDD = 53.5V
405
RL = 4 Ω, 1% THD+N, PVDD = 53.5V
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
SNR
Signal to noise ratio (1)
DNR
Dynamic range
Pidle
Power dissipation due to idle losses (IPVDD)
(1)
(2)
TYP MAX
RL = 2 Ω, 10% THD+N
UNIT
W
315
0.008%
70
μV
A-weighted
114
dB
A-weighted
114
dB
PO = 0, 4 channels switching (2)
2.5
W
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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7.9 Typical Characteristics, BTL Configuration
10
1
TC = 75qC
1W
25W
150W
0.1
0.01
0.001
0.0003
20
100
RL = 4 Ω
1k
f - Frequency - Hz
10k
20k
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
TC = 75°C
PVDD = 51V
TC = 75qC
0.1
0.01
0.001
100
RL = 8 Ω
1k
f - Frequency - Hz
10k
20k
P = 1W, 25W,
100W
TC = 75°C
4:
6:
8:
1
0.1
0.01
TC = 75°C
100
400
1k
f - Frequency - Hz
PVDD = 51V
10k
40k
D002
TC = 75°C
PVDD = 51V
10
TC = 75qC
1W
25W
100W
1
0.1
0.01
0.001
20
100
1k
f - Frequency - Hz
P = 1W, 25W,
100W
AUX-0025 filter, 80 kHz analyzer BW
10k
40k
D004
TC = 75°C
PVDD = 53.5V
Figure 4. Total Harmonic Distortion+Noise vs Frequency
10
6:
8:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
D005
Figure 5. Total Harmonic Distortion + Noise vs Output
Power
10
100
RL = 8 Ω
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 4 Ω, 6 Ω, 8 Ω
0.001
20
Figure 2. Total Harmonic Distortion+Noise vs Frequency
Figure 3. Total Harmonic Distortion+Noise vs Frequency
1
10
Po - Output Power - W
0.01
D003
PVDD = 53.5V
TA = 75qC
0.001
10m
100m
0.1
P = 1W, 25W,
150W
AUX-0025 filter, 80 kHz analyzer BW
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
0.0002
20
1
RL = 4 Ω
Figure 1. Total Harmonic Distortion+Noise vs Frequency
1
TC = 75qC
1W
25W
150W
D001
P = 1W, 25W,
150W
1W
25W
100W
10
RL = 6 Ω, 8 Ω
1
10
Po - Output Power - W
TC = 75°C
100
300
D006
PVDD = 53.5V
Figure 6. Total Harmonic Distortion + Noise vs Output
Power
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Typical Characteristics, BTL Configuration (continued)
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
300
360
4:
6:
8:
280
240
200
160
120
80
20
25
30
35
40
45
PVDD - Supply Voltage - V
RL = 4 Ω, 6 Ω, 8 Ω
50
200
150
100
50
THD+N = 10%
TC = 75qC
40
0
15
4:
6:
8:
250
PO - Output Power - W
PO - Output Power - W
320
55
THD+N = 1%
TC = 75qC
0
15
60
THD+N = 10%
TC = 75°C
25
30
35
40
45
PVDD - Supply Voltage - V
RL = 4 Ω, 6 Ω, 8 Ω
Figure 7. Output Power vs Supply Voltage
50
55
60
D008
THD+N = 1%
TC = 75°C
Figure 8. Output Power vs Supply Voltage
100
100
4:
6:
8:
4:
6:
8:
80
Power Loss - W
Efficiency - %
20
D007
10
60
40
20
TC = 75qC
TC = 75qC
0
1
10m
100m
1
10
2 Channel Output Power - W
RL = 4 Ω, 6 Ω, 8 Ω
THD+N = 10%
100
0
700
200
300
400
500
2 Channel Output Power - W
D009
TC = 75°C
RL = 4 Ω, 6 Ω, 8 Ω
Figure 9. System Efficiency vs Output Power
600 650
D010
THD+N = 10%
TC = 75°C
Figure 10. System Power Loss vs Output Power
0
350
Noise Amplitude - dB
300
PO - Output Power - W
100
250
200
150
100
4:
6:
8:
50
TC = 75qC
-20 Vref = 36.06 V
FFT size = 16384
-40
4:
-60
-80
-100
-120
-140
THD+N = 10%
-160
0
0
RL = 4 Ω, 6 Ω, 8 Ω
25
50
75
TC - Case Temperature - qC
THD+N = 10%
100
0
D011
TC = 75°C
Figure 11. Output Power vs Case Temperature
5k
10k
15k
20k 25k 30k
f - Frequency - Hz
4 Ω, VREF = 36.06 V
(1% Output power)
AUX-0025 filter, 80 kHz
analyzer BW
35k
40k
45k48k
D012
FFT =
16384
TC = 75°C
Figure 12. Noise Amplitude vs Frequency
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7.10 Typical Characteristics, SE Configuration
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 3 Ω, fS = 450 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
10
2:
3:
4:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
RL = 2Ω, 3Ω, 4Ω
1
10
Po - Output Power - W
100 200
1
0.1
0.01
0.001
20
100
10k
20k
D014
P = 1W, 20W, 50W
TC = 75°C
Figure 14. Total Harmonic Distortion+Noise vs Frequency
180
10
TC = 75qC
2:
3:
4:
160
PO - Output Power - W
1W
20W
50W
1
0.1
0.01
140
120
100
80
60
40
THD+N = 10%
TC = 75qC
20
0
15
0.001
20
100
1k
f - Frequency - Hz
10k 20k 40k
D015
30
35
40
45
PVDD - Supply Voltage - V
50
55
60
D016
THD+N = 10%
TC = 75°C
Figure 16. Output Power vs Supply Voltage
175
2:
3:
4:
PO - Output Power - W
150
100
80
60
40
20
0
15
25
TC = 75°C
140
120
20
RL = 2Ω, 3Ω, 4Ω
Figure 15. Total Harmonic Distortion+Noise vs Frequency
PO - Output Power - W
1k
f - Frequency - Hz
RL = 3Ω
TC = 75°C
RL = 3Ω
P = 1W, 20W, 50W
AUX-0025 filter, 80 kHz analyzer BW
125
100
75
50
2:
3:
4:
25
THD+N = 1%
TC = 75qC
THD+N = 10%
0
20
RL = 2Ω, 3Ω, 4Ω
25
30
35
40
45
PVDD - Supply Voltage - V
THD+N = 1%
50
55
60
0
D017
TC = 75°C
Figure 17. Output Power vs Supply Voltage
12
TC = 75qC
1W
20W
50W
D013
Figure 13. Total Harmonic Distortion+Noise vs Output
Power
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 2Ω, 3Ω, 4Ω
25
50
75
TC - Case Temperature - qC
THD+N = 10%
100
D018
TC = 75°C
Figure 18. Output Power vs Case Temperature
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7.11 Typical Characteristics, PBTL Configuration
10
2:
3:
4:
1
0.1
0.01
TA = 75qC
0.001
10m
100m
RL = 2Ω, 3Ω, 4Ω
1
10
Po - Output Power - W
100
700
10
1
0.1
0.01
0.001
0.0003
20
TC = 75°C
100
RL = 2Ω
1k
f - Frequency - Hz
D020
P = 1W, 50W, 375W
TC = 75°C
2:
3:
4:
PO - Output Power - W
600
1
0.1
0.01
500
400
300
200
100
0.001
20
100
1k
f - Frequency - Hz
10k
0
15
40k
D021
TC = 75°C
THD+N = 10%
TC = 75qC
20
25
RL = 2Ω, 3Ω, 4Ω
30
35
40
45
PVDD - Supply Voltage - V
50
55
60
D022
THD+N = 10%
TC = 75°C
Figure 22. Output Power vs Supply Voltage
Figure 21. Total Harmonic Distortion+Noise vs Frequency
600
700
2:
3:
4:
PO - Output Power - W
600
400
300
200
100
0
15
20k
700
TC = 75qC
1W
50W
375W
500
10k
Figure 20. Total Harmonic Distortion+Noise vs Frequency
10
RL = 2Ω
P = 1W, 50W, 375W
AUX-0025 filter, 80 kHz analyzer BW
PO - Output Power - W
TC = 75qC
1W
50W
375W
D019
Figure 19. Total Harmonic Distortion+Noise vs Output
Power
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51V, GVDD_X = 12 V, RL = 2Ω, fS = 450 kHz, ROC = 22 kΩ,
TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless otherwise
noted.
500
400
300
200
2:
3:
4:
100
THD+N = 1%
TC = 75qC
THD+N = 10%
0
20
RL = 2Ω, 3Ω, 4Ω
25
30
35
40
45
PVDD - Supply Voltage - V
THD+N = 1%
50
55
60
0
D023
TC = 75°C
Figure 23. Output Power vs Supply Voltage
RL = 2Ω, 3Ω, 4Ω
25
50
75
TC - Case Temperature - qC
THD+N = 10%
100
D024
TC = 75°C
Figure 24. Output Power vs Case Temperature
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions,
Typical Characteristics, BTL Configuration, Typical Characteristics, SE Configuration and Typical Characteristics,
PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3255 needs only a 12-V supply in addition to the (typical) 51-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V
source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see
application diagram for details) is recommended. These RC filters provide the recommended high-frequency
isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to
the device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3255 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 51-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power
supply is settled for minimum turn on audible artefacts. Moreover, the TPA3255 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within the specified range (see the Recommended Operating Conditions table of this data sheet).
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9.2 Functional Block Diagrams
/CLIP_OTW
VDD
VBG
POWERUP
RESET
PROTECTION & I/O LOGIC
/FAULT
M1
M2
/RESET
C_START
VREG
AVDD
UVP
DVDD
GND
TEMP
SENSE
GVDD_AB
GND
GVDD_CD
DIFFOC
STARTUP
CONTROL
OVER-LOAD
PROTECTIO
N
CB3C
CURRENT
SENSE
OC_ADJ
OSC_IOM
OSC_IOP
OSCILLATO
R
PPSC
FREQ_ADJ
PVDD_X
OUT_X
GND
GVDD_AB
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_AB
INPUT_A
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND
GVDD_AB
BST_B
PVDD_AB
INPUT_B
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND
GVDD_CD
BST_C
PVDD_CD
INPUT_C
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_C
GND
GVDD_CD
BST_D
PVDD_CD
INPUT_D
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND
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Functional Block Diagrams (continued)
Capacitor for
External
Filtering
and
Startup/Stop
C_START
/CLIP_OTW
/RESET
/FAULT
System
microcontroller or
Analog circuitry
BST_A
OSC_IOP
Oscillator
Synchronization
BST_B
OSC_IOM
OUT_A
INPUT_B
FREQ_ADJ
PVDD
51V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GVDD, VDD,
DVDD and
AVDD
Power Supply
Decoupling
BST_D
Bootstrap
Capacitors
Hardwire
OverCurrent
Limit
GND
GND
12V
OC_ADJ
AVDD
VBG
M2
OUT_D
2nd Order
L-C Output
Filter for
Each
H-Bridge
BST_C
DVDD
M1
Output
H-Bridge 2
VDD
Hardwire
Mode
Control
GVDD_AB, CD
Input
H-Bridge 2
INPUT_D
GND
ANALOG_IN_D
OUT_C
INPUT_C
Input DC
Blocking
Caps
OUT_B
2nd Order
L-C Output
Filter for
Each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
GND
Hardwire PWM
Frame Adjust and
Master/Slave
Mode
ANALOG_IN_C
Input
H-Bridge 1
PVDD_AB, CD
ANALOG_IN_B
Output
H-Bridge 1
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
Bootstrap
Capacitors
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
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Figure 25. System Block Diagram
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9.3 Feature Description
9.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see Table 2).
Table 2. Error Reporting
FAULT
CLIP_OTW
DESCRIPTION
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction
temperature higher than 125°C (overtemperature warning)
0
0
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C
(overtemperature warning)
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
1
0
Junction temperature higher than 125°C (overtemperature warning)
1
1
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.
9.4 Device Functional Modes
9.4.1 Device Protection System
The TPA3255 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TPA3255 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other
than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has
been removed, that is, the supply voltage has increased.
The device will handle errors, as shown in Table 3.
Table 3. Device Protection
BTL MODE
LOCAL
ERROR IN
A
B
C
D
PBTL MODE
TURNS OFF
A+B
C+D
LOCAL
ERROR IN
TURNS OFF
A
B
C
SE MODE
LOCAL
ERROR IN
A
A+B+C+D
D
B
C
D
TURNS OFF
A+B
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).
9.4.1.1 Overload and Short Circuit Current Protection
TPA3255 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side
and low-side FETs. To prevent output current from increasing beyond the programmed threshold, TPA3255 has
the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or
to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C
prevents premature shutdown due to high output current transients caused by high level music transients and a
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drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed
level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,
the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)
state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current
event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next
PWM frame.
PWM_X
RISING EDGE PWM
SETS CB3C LATCH
HS PWM
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
Figure 26. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
R_Latch, max,
Latching OC, min level
R_Latch, min,
Latching OC, max level
R_OC, min,
CB3C, max level
R_OC, max,
CB3C, min level
ROC_ADJ
Figure 27. OC Threshold versus OC_ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
18
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Table 4. Device Protection
OC_ADJ Resistor Value
Protection Mode
OC Threshold
22kΩ
CB3C
17.0A
24kΩ
CB3C
15.7A
27kΩ
CB3C
14.2A
30kΩ
CB3C
12.9A
47kΩ
Latched OC
17.0A
51kΩ
Latched OC
15.7A
56kΩ
Latched OC
14.2A
64kΩ
Latched OC
12.9A
9.4.1.2 Signal Clipping and Pulse Injector
A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3255 is designed to drive unclipped
output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying excessive input
signal voltage, or in case of CB3C current protection being active, the amplifier feedback loop of the audio
channel will respond to this condition with a saturated state, and the output PWM signals would stop if the device
did not have special circuitry implemented to handle this situation. To prevent the output PWM signals from
stopping in a clipping or CB3C situation, narrow pulses are injected to the gate drive to maintain output activity.
The injected narrow pulses are injected at every 4th PWM frame, and thus the effective switching frequency
during this state is reduced to 1/4 of the normal switching frequency.
Signal clipping is signalled on the CLIP_OTW pin and is self clearing when signal level reduces and the device
reverts to normal operation. The CLIP_OTW pulses start at the onset to output clipping, typically at a THD level
around 0.01%, resulting in narrow CLIP_OTW pulses starting with a pulse width of ~500 ns.
Figure 28. Signal Clipping PWM and Speaker Output Signals
9.4.1.3 DC Speaker Protection
The output DC protection scheme protects a speaker from excess DC current in case one terminal of the
speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short
circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current
levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in
the event of the unbalance exceeding a programmed threshold, the overload counter increments until its
maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in SE mode
operation.
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9.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup
does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all
half bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
typical duration is < 15ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will
not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes, and FAULT
is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL
output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection
system it is recommended not to insert a resistive load to GND_X or PVDD_X.
9.4.1.5 Overtemperature Protection OTW and OTE
TPA3255 has a two-level temperature-protection system that asserts an active-low warning signal (CLIP_OTW)
when the device junction temperature exceeds 120°C (typical) and, if the device junction temperature exceeds
155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.
9.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
The UVP and POR circuits of the TPA3255 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit ensures that all circuits are fully operational when the GVDD_X and VDD
supply voltages reach values stated in the Electrical Characteristics table. Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
The device automatically resumes operation when all supply voltages have increased above the UVP threshold.
9.4.1.7 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires
resetting the device by toggling RESET. Deasserting RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the CLIP_OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity
of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present.
20
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Table 5. Error Reporting
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Output FETs
Voltage Fault
Global
FAULT pin
Self Clearing
Increase affected
supply voltage
HI-Z
Power On Reset
Global
FAULT pin
Self Clearing
Allow DVDD to
rise
HI-Z
Voltage Fault
Channel (Half
Bridge)
None
Self Clearing
Allow BST cap to
recharge (lowside HighSide off
ON, VDD 12V)
OTW
Thermal Warning
Global
OTW pin
Self Clearing
Cool below OTW
threshold
Normal operation
OTE
Thermal
Shutdown
Global
FAULT pin
Latched
Toggle RESET
HI-Z
Fault/Event
PVDD_X UVP
VDD UVP
AVDD UVP
POR (DVDD UVP)
BST_X UVP
OLP (CB3C>1.7ms)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
Latched OC
(47kΩ
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