Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPA3251
SLASE40D – MAY 2015 – REVISED APRIL 2016
TPA3251 175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog-Input
Class-D Amplifier
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Differential Analog Inputs
Total Output Power at 10%THD+N
– 175-W Stereo into 4 Ω in BTL Configuration
– 220-W Stereo into 3 Ω in BTL Configuration
– 350-W Mono into 2 Ω in PBTL Configuration
Total Output Power at 1%THD+N
– 140-W Stereo into 4 Ω in BTL Configuration
– 175-W Stereo into 3 Ω in BTL Configuration
– 285-W Mono into 2 Ω in PBTL Configuration
Advanced Integrated Feedback Design with Highspeed Gate Driver Error Correction
(PurePath™ Ultra-HD)
– Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources
– Ultra Low 0.005% THD+N at 1 W into 4 Ω and
400ms
/RESET
AVDD
tAVDD ramp C 100µs
/FAULT
tPrecharge C 220ms
VIN_X
OUT_X
VOUT_X
tStartup ramp
Figure 28. Startup Timing
28
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPA3251
TPA3251
www.ti.com
SLASE40D – MAY 2015 – REVISED APRIL 2016
Powering Up (continued)
When RESET is released to turn on TPA3251, FAULT signal will turn low and AVDD voltage regulator will be
enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the
Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the
input AC coupling capacitors, before the ramp up sequence starts.
11.3 Powering Down
The TPA3251 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by
initiating a controlled ramp down sequence of the output voltage.
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
PCB layout, audio performance and EMI are linked closely together.
Routing the audio input should be kept short and together with the accompanied audio source ground.
The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible.
A local ground area underneath the device is important to keep solid to minimize ground bounce.
Orient the passive component so that the narrow end of the passive component is facing the TPA3251
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
Avoid placing other heat producing components or structures near the TPA3251 device.
Avoid cutting off the flow of heat from the TPA3251 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in Figure 29.
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPA3251
29
TPA3251
SLASE40D – MAY 2015 – REVISED APRIL 2016
www.ti.com
12.2 Layout Examples
12.2.1 BTL Application Printed Circuit Board Layout Example
T3
10k
22k
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T2
T2
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 29. BTL Application Printed Circuit Board - Composite
30
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPA3251
TPA3251
www.ti.com
SLASE40D – MAY 2015 – REVISED APRIL 2016
Layout Examples (continued)
12.2.2 SE Application Printed Circuit Board Layout Example
T3
10k
22k
T1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
T2
T2
20
25
21
24
22
23
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 30. SE Application Printed Circuit Board - Composite
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPA3251
31
TPA3251
SLASE40D – MAY 2015 – REVISED APRIL 2016
www.ti.com
Layout Examples (continued)
12.2.3 PBTL Application Printed Circuit Board Layout Example
T3
10k
22k
T1
Grounded for PBTL
Grounded for PBTL
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
T2
T2
T1
T3
System Processor
Bottom Layer Signal Traces
Bottom to top layer connection via
Pad to top layer ground pour
Top Layer Signal Traces
A.
Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B.
Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat
sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without
going through vias. No vias or traces should be blocking the current path.
C.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
D.
ote T3: Heat sink needs to have a good connection to PCB ground.
Figure 31. PBTL Application Printed Circuit Board - Composite
32
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPA3251
TPA3251
www.ti.com
SLASE40D – MAY 2015 – REVISED APRIL 2016
13 Device and Documentation Support
13.1 Documentation Support
TPA3251EVM User's Guide, SLVUAG8
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
PurePath, E2E are trademarks of Texas Instruments.
Blu-ray Disk is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPA3251
33
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA3251D2DDV
ACTIVE
HTSSOP
DDV
44
35
RoHS & Green
Call TI
Level-3-260C-168 HR
0 to 70
3251
TPA3251D2DDVR
ACTIVE
HTSSOP
DDV
44
2000
RoHS & Green
Call TI
Level-3-260C-168 HR
0 to 70
3251
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
很抱歉,暂时无法提供与“TPA3251D2DDVR”相匹配的价格&库存,您可以联系我们找货
免费人工找货- 国内价格 香港价格
- 2000+37.545002000+4.55024