TPS40055-EP
8
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WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER
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FEATURES
APPLICATIONS
•
•
•
•
•
•
•
1
2
•
•
•
•
•
•
•
Operating Input Voltage 8 V to 40 V
Input Voltage Feed-Forward Compensation
< 1 % Internal 0.7-V Reference
Programmable Fixed-Frequency Up to 1-MHz
Voltage Mode Controller
Internal Gate Drive Outputs for High-Side and
Synchronous N-Channel MOSFETs
16-Pin PowerPAD™ Package (θJC = 25°C/W)
Thermal Shutdown
Externally Synchronizable
Programmable High-Side Sense Short-Circuit
Protection
Programmable Closed-Loop Soft-Start
TPS40055 Source/Sink
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Power Modules
Networking/Telecom
Industrial/Servers
DESCRIPTION
The TPS40055 is a family of high-voltage, wide input
(8 V to 40 V), synchronous, step-down converters.
The TPS40055 family offers design flexibility with a
variety of user programmable functions, including
soft-start, UVLO, operating frequency, voltage feedforward,
high-side
current
limit,
and
loop
compensation.
The TPS40055 are also synchronizable to an external
supply. The TPS40055 incorporates MOSFET gate
drivers for external N-channel high-side and
synchronous rectifier (SR) MOSFETs. Gate drive
logic incorporates anti-cross conduction circuitry to
prevent simultaneous high-side and synchronous
rectifier conduction.
The TPS40055 uses voltage feed-forward control
techniques to provide good line regulation over the
wide (4:1) input voltage range and fast response to
input line transients with near constant gain with input
variation which eases loop compensation. The
externally programmable current limit provides pulseby-pulse current limit, as well as a hiccup mode
operation utilizing an internal fault counter for longer
duration overloads.
Additional temperature ranges available - contact factory
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2012, Texas Instruments Incorporated
TPS40055-EP
SGLS310D – JULY 2005 – REVISED FEBRUARY 2012
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SIMPLIFIED APPLICATION DIAGRAM
TPS40055
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
(3)
(4)
2
TA
APPLICATION (2)
PACKAGE (3) (4)
PART NUMBER
–55°C to 125°C
SOURCE/SINK
Plastic HTSSOP (PWP)
TPS40055MPWPREP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
See Application Information section.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
The PWP package is also available taped and reeled. Add an R suffix to the device type. See the application section of the data sheet
for PowerPAD drawing and layout information.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE / UNIT
VIN
VIN
Input voltage range
45 V
VFB, SS, SYNC
–0.3 V to 6 V
SW
–0.3 V to 45 V
SW, transient < 50 ns
–2.5 V
KFF, with IIN(max) = –5 mA
–0.3 V to 11 V
VOUT
Output voltage range
COMP, RT, SS
–0.3 V to 6 V
IIN
Input current
KFF
IOUT
Output current
RT
TJ
Operating junction temperature range
–55°C to 140°C
Tstg
Storage temperature (2)
–55°C to 150°C
5 mA
200 µA
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
TJC
Thermal resistance junction-to-case
TJA
Thermal resistance junction-to-ambient
TJP
Thermal resistance junction-to-bottom of thermal pad
φJT
(1)
(2)
(3)
(4)
Junction-to-top thermal parameter
260°C
26.6°C/W
(3) (4)
36.5°C/W
(3)
2.1°C/W
(3) (4)
0.848°C/W
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in reduced overall
device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
See technical brief SLMA002 - PowerPAD Thermally Enhanced Package(http://www-s.ti.com/sc/techlit/slma002).
Tested in accordance with the thermal metric definitions of EIA/JESD51-5.
RECOMMENDED OPERATING CONDITIONS
MIN
VI
Input voltage
TA
Operating free-air temperature
NOM
MAX
UNIT
8
40
V
–55
125
°C
ELECTRICAL CHARACTERISTICS
TA = –55°C to 125°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY
VIN
Input voltage range, VIN
8
40
V
1.5
3.3
mA
OPERATING CURRENT
IDD
Output drivers not switching, VFB ≥
0.75 V
Quiescent current
BP5
VBP5
Output voltage
OSCILLATOR/RAMP GENERATOR
IOUT ≤ 1 mA
4.7
5
5.3
V
465
520
585
kHz
(1)
fOSC
Accuracy
8 V ≤ VIN ≤ 40 V
VRAMP
PWM ramp voltage (2)
VPEAK – VVAL
VIH
High-level input voltage, SYNC
VIL
Low-level input voltage, SYNC
ISYNC
Input current, SYNC
2
Pulse width, SYNC
VRT
(1)
(2)
2
V
5
V
5
11
µA
2.5
2.59
50
RT voltage
2.37
V
0.8
ns
V
IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle.
Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 125°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Maximum duty cycle
VFB = 0 V, 500 kHz ≤ fSW ≤ 1 MHz
Feed-forward voltage
IKFF
Feed-forward current operating range (2)
TYP
84%
(2)
MAX UNIT
94%
80%
VFB ≥ 0.75 V
Minimum duty cycle
VKFF
MIN
VFB = 0 V, fSW ≤ 500 kHz
0%
3.35
3.48
20
3.7
V
1200
µA
3.6
µA
SOFT START
ISS
Soft-start source current
VSS
Soft-start clamp voltage
1.2
2.35
tDSCH
Discharge time
CSS = 220 pF
1.4
2.2
3.4
µs
tSS
Soft-start time
CSS = 220 pF, 0 V ≤ VSS ≤ 1.6 V
102
150
230
µs
Output voltage
IOUT ≤ 1 mA
8.9
9.6
10.45
V
8 V ≤ VIN ≤ 40 V, TA = 25°C
0.698
0.7
0.704
8 V ≤ VIN ≤ 40 V, 0°C ≤ TA ≤ 125°C
0.689
0.7
0.717
8 V ≤ VIN ≤ 40 V, –55°C ≤ TA ≤
125°C
0.689
0.7
0.719
2.8
5
MHz
dB
3.7
V
BP10
VBP10
ERROR AMPLIFIER
VFB
Feedback input voltage
V
GBW
Gain bandwidth (3)
AVOL
Open loop gain
40
80
IOH
High-level output source current
1.85
4
IOL
Low-level output source current
1.95
4
VOH
High-level output voltage
ISOURCE = 500 µA
3.1
3.5
VOL
Low-level output voltage
ISINK = 500 µA
0.2
0.37
IBIAS
Input bias current
VFB = 0.7 V
100
220
nA
10
12.2
µA
mA
V
CURRENT LIMIT
ISINK
Current limit sink current
7.5
Propagation delay to output
tON
Switch leading-edge blanking pulse time (3)
tOFF
Off time during a fault
VOS
Offset voltage SW vs ILIM
VILIM = 23.7 V, VSW = (VILIM – 0.5 V)
300
VILIM = 23.7 V, VSW = (VILIM – 2 V)
200
ns
100
ns
7
–70
cycle
s
VILIM = 23.6 V, TA = 25°C
–115
–50
VILIM = 23.6 V, 0°C ≤ TA ≤ 125°C
–155
–38
VILIM = 23.6 V, –55°C ≤ TA ≤ 125°C
–155
–10
VILIM = 11.6 V, TA = 25°C
–118
–43
VILIM = 11.6 V, 0°C ≤ TA ≤ 125°C
–160
–45
VILIM = 11.6 V, TA = –55°C to 125°C
–160
–15
mV
OUTPUT DRIVER
tLRISE
Low-side driver rise time
tLFALL
Low-side driver fall time
tHRISE
High-side driver rise time
tHFALL
High-side driver fall time
VOH
High-level output voltage, HDRV
IHDRV = –0.1 A (HDRV - SW)
VOL
Low-level output voltage, HDRV
IHDRV = 0.1 A (HDRV - SW)
(3)
4
CLOAD = 2200 pF
CLOAD = 2200 pF, (HDRV – SW)
48
110
24
58
48
105
36
82
BOOST BOOST
–1.9
–1
ns
ns
V
0.85
V
Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 125°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage, LDRV
ILDRV = –0.1 A
VOL
Low-level output voltage, LDRV
ILDRV = 0.1 A
MIN
TYP
BP10
–1.8
BP10
–1
Minimum controllable pulse width
MAX UNIT
V
0.6
V
100
160
ns
SS/SD SHUTDOWN
VSD
Shutdown threshold voltage
VEN
Device active threshold voltage
Outputs off
85
125
170
mV
180
210
260
mV
30.8
32.2
33.9
V
35
µA
BOOST REGULATOR
VBOOST
Output voltage
VIN = 24 V
SW NODE
ILEAK
Leakage current (4)
THERMAL SHUTDOWN
Shutdown temperature (4)
TSD
165
Hysteresis (4)
°C
20
UVLO
VUVLO
VDD
(4)
KFF programmable threshold voltage
RKFF = 28.7 kΩ
UVLO, fixed
UVLO, hysteresis
6.85
7.5
7.95
7.05
7.5
7.9
V
0.46
Ensured by design. Not production tested.
TYPICAL CHARACTERISTICS
OFFSET VOLTAGE (VLim vs SW)
TEMPERATURE
Figure 1.
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DEVICE INFORMATION
(1)
For more information on the PWP package, see the Texas Instruments Technical Brief (SLMA002)
(2)
PowerPAD heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
14
O
Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input
voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.
BP5
3
O
5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used
with an external dc load of 1 mA or less.
BP10
11
O
10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1µF ceramic capacitor. This pin may be used with an external dc load of 1 mA or less.
COMP
8
O
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to
the VFB pin to compensate the overall loop. The COMP pin is internally clamped above the peak of the ramp to
improve large signal transient response.
HDRV
13
O
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
ILIM
16
I
Current limit pin used to set the overcurrent threshold. An internal current sink from this pin to ground sets a
voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to
the voltage drop (VIN -SW) across the high side MOSFET during conduction.
KFF
1
I
A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into
this pin is internally divided and used to control the slope of the PWM ramp.
LDRV
10
O
Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
(MOSFET off).
PGND
9
–
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of
the lower MOSFET(s).
RT
2
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
SGND
5
–
Signal ground reference for the device
NAME
NO.
BOOST
SS/SD
6
I
Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used
as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is
approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately
1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive.
The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately
0.85 V, the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains
active.
SW
12
I
This pin is connected to the switched node of the converter and used for overcurrent sensing.
6
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
SYNC
4
I
Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master
frequency. If synchronization is not used, connect this pin to SGND.
VFB
7
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
reference voltage, 0.7 V.
VIN
15
I
Supply voltage for the device
SIMPLIFIED BLOCK DIAGRAM
0.7 VREF
0.85 V
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APPLICATION INFORMATION
The TPS40055 allows the user to optimize the PWM controller to the specific application.
The TPS40055 is the controller of choice for synchronous buck designs, which includes most applications. It has
two quadrant operations and will source or sink output current. This provides the best transient response.
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS40055 has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the
master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a
single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by Equation 1 and the relationship is
charted in Figure 3.
(1)
PROGRAMMING THE RAMP GENERATOR CIRCUIT
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since
the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 2 ).
Figure 2. Voltage Feed-Forward Effect on PWM Duty Cycle
The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT and the
minimum input voltage (VIN(min)) through the following:
(2)
where:
VIN(min) is the ensured minimum start-up voltage. The actual start-up voltage is nominally about 10% lower at
25°C.
8
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RT is the timing resistance in kΩ.
The curve showing the RKFF required for a given switching frequency (fSW) is shown in Figure 4.
For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltage. For more information on large duty cycle operation, see the application note
(SLUA310).
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
Figure 3.
FEED-FORWARD IMPEDANCE
vs
SWITCHING FREQUENCY
Figure 4.
UVLO OPERATION
The TPS40055 uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low
until the input voltage has exceeded the user programmable undervoltage threshold.
The TPS40055 uses the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable
low-line TPS40055 uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start
low until the input voltage has exceeded the user programmable undervoltage threshold. UVLO threshold
compares the PWM ramp duration to the oscillator clock period. An undervoltage condition exists if the
TPS40055 receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a
function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function
of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the
oscillator frequency as described in Equation 3:
(3)
where:
VIN is the desired start-up (UVLO) input voltage
RT is the timing resistance in kΩ
The variable UVLO function uses a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or
fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter than
the clock cycle a power-good signal is asserted and a soft-start initiated and the upper and lower MOSFETS are
turned off.
Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 5 ).
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Figure 5. Undervoltage Lockout Operation
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start up voltage.
The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to
select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 7.
Figure 6. UNDERVOLTAGE LOCKOUT THRESHOLD
vs
HYSTERESIS
Figure 7.
BP5 AND BP10 INTERNAL VOLTAGE REGULATORS
Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in Figure 8
and Figure 9. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10
regulation characteristics is also based on the load presented by switching the external MOSFETs.
10
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INPUT VOLTAGE
vs
BP5 VOLTAGE
INPUT VOLTAGE
vs
BP10 VOLTAGE
Figure 8.
Figure 9.
SELECTING THE INDUCTOR VALUE
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is
physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater
number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter does not enter discontinuous mode until the
load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in
Equation 4.
(4)
where:
VO is the output voltage
ΔI is the peak-to-peak inductor current
CALCULATING THE OUTPUT CAPACITANCE
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.
The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output
ripple is described in Equation 5.
(5)
The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During a
step load, the output capacitance must provide energy to the load (light-to-heavy load step) or absorb excess
inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.
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Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
Equation 6.
(6)
where:
(7)
IOH is the output current under heavy load conditions
IOL is the output current under light load conditions
Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This
applies to applications which have high impedance on the input voltage line or which have excessive ringing on
the VIN line. The input voltage impedance can cause the input voltage to sag enough at start-up to cause a
UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and
cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to
prevent the nuisance UVLO shutdown.
Assuming a hysteresis current of 10% IKFF and the peak detector charges to 8 V and VIN(min) = 10 V, the value of
RA is calculated by Equation 8 using a RKFF = 71.5 kΩ.
(8)
CA is chosen to maintain the peak voltage between switching cycles. To keep the capacitor charge from drooping
0.1 V, or from 8 V to 7.9 V.
(9)
The value of CA may calculate to less than 10 pF, but some standard value up to 47 pF works adequately. The
diode can be a small signal switching diode or Schottky rated for more then 20 V. Figure 10 illustrates a typical
implementation using a small switching diode.
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start up voltage.
12
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+
VIN
−
RA
499 kW
RKFF
71.5 kW
CA
47 pF
1 KFF
ILIM 16
2 RT
VIN 15
3 BP5
BOOST 14
4 SYNC
HDRV 13
5 SGND
SW 12
6 SS
BP10 11
7 VFB
LDRV 10
8 COMP
PGND 9
PWP
DA
1N914, 1N4150
Type Signal Diode
UDG−03034
Figure 10. Hysteresis for Programmable UVLO
Energy in the capacitor is described in Equation 10.
(10)
where:
(11)
where:
Vf is the final peak capacitor voltage
VI is the initial capacitor voltage
Substituting Equation 7 into Equation 6, then substituting Equation 11 into Equation 10, then setting Equation 10
equal to Equation 6, and then solving for CO yields the capacitance described in Equation 12.
(12)
PROGRAMMING SOFT START
TPS40055 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is
programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on
CSS minus 0.85 V is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V
VREF). The loop is closed on the lower of the (CSS – 0.85 V) voltage or the internal reference voltage (0.7-V
VREF). Once the (CSS – 0.85 V) voltage rises above the internal reference voltage, regulation is based on the
internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than
the L-CO time constant as described in Equation 13.
(13)
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There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the
higher the input current required during start-up. This relationship is describe in more detail in the section titled,
Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in Equation 14.
(14)
For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the VIN supply transitions between 6 V and 7 V.
PROGRAMMING CURRENT LIMIT
The TPS40055 uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven, a restart is issued
and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period.
The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is reenabled. If the fault has been removed the output starts up normally. If the output is still present, the counter
counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 11 for typical overcurrent
protection waveforms.
The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at turn-on (IL).
(15)
Figure 11. Typical Current Limit Protection Waveforms
The current limit programming resistor (RILIM) is calculated using Equation 16. Care must be taken in choosing
the values used for VOS and ISINK in the equation. In order to assure the output current at the overcurrent level,
the minimum value of ISINK and the maximum value of VOS must be used.
14
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(16)
where:
ISINK is the current into the ILIM pin and is 7.5 µA, minimum
IOC is the overcurrent setpoint which is the dc output current plus one-half of the peak inductor current
VOS is the overcurrent comparator offset and is –20 mV, maximum
SYNCHRONIZING TO AN EXTERNAL SUPPLY
The TPS40055 can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the
falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS40055 to freely run at the
frequency programmed by RT.
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching
frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a dummy value
for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the
design.
(17)
Use the value of RT(dummy) to calculate the value for RKFF.
(18)
This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency.
RT(dummy) is in kΩ
Loop Compensation
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40055
uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be
included. The modulator gain is described in Figure 11, with VIN being the minimum input voltage required to
cause the ramp excursion to cover the entire switching period as described in Equation 19.
(19)
Duty cycle (D) varies from 0 to 1 as the control voltage (VC) varies from the minimum ramp voltage to the
maximum ramp voltage (VS). Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to
output voltage modulator gain in terms of the input voltage and ramp voltage:
(20)
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Calculate the Poles and Zeros
For a buck converter using voltage mode control, there is a double pole due to the output L-CO. The double pole
is located at the frequency calculated in Equation 21.
(21)
There is also a zero created by the output capacitance (CO) and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 22.
(22)
Calculate the value of RBIAS to set the output voltage (VOUT).
(23)
The maximum crossover frequency (0 dB loop gain) is calculated in Equation 24.
(24)
Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this
frequency, the control to output gain has a -2 slope (–40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 13 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
MODULATOR GAIN
vs
SWITCHING FREQUENCY
Figure 12. PWM Modulator Relationships
Figure 13.
A Type III topology, shown in Figure 14, has 2 zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 15. The two zeros are used to compensate the L-CO
double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide
controlled gain roll-off. In many cases, the second pole can be eliminated and the amplifier's gain roll-off used to
roll-off the overall gain at higher frequencies. Figure 14.
16
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Figure 14. Type III Compensation Configuration
Figure 15. Type III Compensation Gain and Phase
The poles and zeros for a Type III network are described in Equation 25.
(25)
The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩ and
100 kΩ usually yields reasonable values.
The unity gain frequency is described in Equation 26.
(26)
where G is the reciprocal of the modulator gain at fC.
The modulator gain as a function of frequency at fC, is described in Equation 27.
(27)
Minimum Load Resistance
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current, which must be considered when sizing R2.
Too small a value does not allow the output to swing over its full range.
(28)
CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR
The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor
should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate
charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is
described in Equation 29.
(29)
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The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET
via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 30.
(30)
dv/dt INDUCED TURN-ON
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused
by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the
MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source
voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through
currents. Therefore, the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS
capacitance.
HIGH SIDE MOSFET POWER DISSIPATION
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The
high-side MOSFET conduction losses are defined by Equation 31.
(31)
where:
TCR is the temperature coefficient of the MOSFET RDS(on)
The TCR varies depending on MOSFET technology and manufacturer, but typically ranges between
3500 ppm/°C and 10000 ppm/°C.
The IRMS current for the high side MOSFET is described in Equation 32.
(32)
The switching losses for the high-side MOSFET are described in Equation 33.
(33)
where:
IO is the dc-output current
tSW is the switching rise time, typically < 20 ns
fSW is the switching frequency
Typical switching waveforms are shown in Figure 16.
18
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ID2
}
IO
ID1
d
BODY DIODE
CONDUCTION
∆I
1−d
BODY DIODE
CONDUCTION
SW
0
ANTI−CROSS
CONDUCTION
SYNCHRONOUS
RECTIFIER ON
HIGH SIDE ON
UDG−02139
Figure 16. Inductor Current and SW Node Waveforms
The maximum allowable power dissipation in the MOSFET is determined by Equation 34.
(34)
where:
(35)
and θJA is the package thermal impedance.
SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction
losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using
Equation 31 and the RMS current through the synchronous rectifier MOSFET is described in Equation 36.
(36)
The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross
conduction delay time. The body diode conduction losses are described by Equation 37.
(37)
where:
VF is the body diode forward voltage
tDELAY is the delay time just before the SW node rises
The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and
once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery
from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 38.
(38)
where:
QRR is the reverse recovery charge of the body diode.
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The QRR is not always described in a MOSFET's data sheet, but may be obtained from the MOSFET vendor.
The total synchronous rectifier MOSFET power dissipation is described in Equation 39.
(39)
TPS40055 POWER DISSIPATION
The power dissipation in the TPS40055 is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance)[2] can be calculated from Equation 40.
(40)
And the total power dissipation in the TPS40055, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier is described in Equation 41.
(41)
or
(42)
where:
IQ is the quiescent operating current (neglecting drivers)
The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow.
The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air
flow.
(43)
The maximum allowable package power dissipation is related to ambient temperature by Equation 44.
(44)
Substituting Equation 45 into Equation 41 and solving for fSW yields the maximum operating frequency for the
TPS40055. The result is described in Equation 45.
(45)
LAYOUT CONSIDERATIONS
PowerPAD™ PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package, dimensions of the circuit board pad area are 5 mm x 3,4 mm [2]. The dimensions of the package
pad are shown in Figure 17.
20
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Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0,33 mm (13 mils) works well when 1-oz copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter of 0,1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. See the PowerPAD Thermally
Enhanced Package and the mechanical illustration at the end of this document for more information on the
PowerPAD package.
Figure 17. PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In
general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA)
and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on
proper layout and thermal management. The θJA specified in the MOSFET data sheet refers to a given copper
area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce
copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. See
the selected MOSFET's data sheet for more information regarding proper mounting.
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
The TPS40055 provides separate signal ground (SGND) and power ground (PGND) pins. It is important that
circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.
Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to
their respective power and ground pins. Also, sensitive circuits such as FB, RT, and ILIM should not be located
near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
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DESIGN EXAMPLE
•
•
•
•
•
•
•
Input Voltage: 10 Vdc to 24 Vdc
Output voltage: 3.3 V +2% (3.234 ≤ VO ≤ 3.366)
Output current: 8 A (maximum, steady state), 10 A (surge, 10-ms duration, 10% duty cycle maximum)
Output ripple: 33 mVP-P at 8 A
Output load response: 0.3 V => 10% to 90% step load change, from 1 A to 7 A
Operating temperature: -40°C to 85°C
fSW = 300 kHz
1. Calculate maximum and minimum duty cycles
(46)
2. Select switching frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET (tON) must be greater
than 300 ns (see the Electrical Characteristics table). Therefore,
(47)
(48)
Using 400 ns to provide margin,
(49)
Since the oscillator can vary by 10%, decrease fSW by 10%
(50)
and therefore choose a frequency of 300 kHz.
3. Select ΔI
In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load.
(51)
4. Calculate the power losses
Power losses in the high-side MOSFET (Si7860DP) at 24-VIN where switching losses dominate can be calculated
from Equation 52.
(52)
substituting Equation 34 into Equation 33 yields
(53)
22
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and from Equation 33, the switching losses can be determined.
(54)
The MOSFET junction temperature can be found by substituting Equation 35 into Equation 34
(55)
5. Calculate synchronous rectifier losses
The synchronous rectifier MOSFET has two loss components: conduction and diode reverse recovery losses.
The conduction losses are due to IRMS losses, as well as body diode conduction losses during the dead time
associated with the anti-cross conduction delay.
The IRMS current through the synchronous rectifier from Equation 38
(56)
The synchronous MOSFET conduction loss from Equation 33 is:
(57)
The body diode conduction loss from Equation 39 is:
(58)
The body diode reverse recovery loss from Equation 40 is:
(59)
The total power dissipated in the synchronous rectifier MOSFET from Equation 41 is:
(60)
The junction temperature of the synchronous rectifier at 85°C is:
(61)
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.
6. Calculate the inductor value
The inductor value is calculated from Equation 62.
(62)
A 2.9-µH Coev DXM1306-2R9 or 2.6-µH Panasonic ETQ-P6F2R9LFA can be used.
7. Setting the switching frequency
The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from
Equation 63, with fSW in kHz.
(63)
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8. Programming the ramp generator circuit
The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from Equation 64.
W
(64)
9. Calculating the output capacitance (CO)
In this example the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1-A
to 8-A step load. CO can be calculated using Equation 65.
(65)
Using Equation 66, we can calculate the ESR required to meet the output ripple requirements.
97
(66)
(67)
For this design example, two Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.
10. Calculate the soft-start capacitor (CSS)
This design requires a soft-start time (tSTART) of 1 ms. CSS can be calculated on Equation 68
(68)
11. Calculate the current limit resistor (RILIM)
The current limit set point depends on tSTART, VO, CO, and ILOAD at start-up as shown in Equation 69. For this
design,
(69)
For this design, set ILIM for 11 ADC minimum. From Equation 70, with IOC equal to the dc-output surge current
plus one-half the ripple current of 3.2 A and RDS(on) is increased 30% (1.3 × 0.008) to allow for MOSFET heating.
(70)
12. Calculate loop compensation values
Calculate the dc modulator gain (AMOD) from Equation 71
(71)
Calculate the output filter L-CO poles and CO ESR zeros from Equation 72 and Equation 73
(72)
and
24
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(73)
Select the close-loop 0 dB crossover frequency (fC). For this example, fC = 20 kHz.
Select the double zero location for the Type III compensation network at the output filter double pole at 4.93 kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at
73.7 kHz.
The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 74.
(74)
And also from Equation 75.
(75)
Choose R1 = 100 kΩ
The poles and zeros for a type III network are described in Equation 25 and Equation 26.
(76)
(77)
(78)
(79)
(80)
Calculate the value of RBIAS from Equation 81 with R1 = 100 kΩ.
(81)
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5-V droop on
the BOOST pin from Equation 29 is:
(82)
and the BP10V capacitance from Equation 32 is
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(83)
For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1-µF capacitor is used for
the BP10V bypass.
26
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DESIGN EXAMPLE SUMMARY
Figure 18 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the
design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST
to get sufficient gate drive for the upper MOSFET. As seen in Figure 9, the BP10 output is about 6 V with the
input at 8 V, so the upper MOSFET gate drive may be less than 5 V.
A Schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that may
be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V.
+
RKFF
71.5 kW
VIN
330 mF
13 kW
330 mF
TPS40055
1N4150 499 kW
RT
169 kW
1 KFF
ILIM 16
2 RT
VIN 15
100 pF
0.1 mF
47 pF
3 BP5
1.0 mF
BOOST 14
22 mF
50 V
22 mF
50 V
1.0 kW
4 SYNC
1.0 mF
Optional
Hysteresis for
UVLO
CSS
3300 pF
5 SGND
6 SS
C1
330 pF
Si7860
2.9 mH
+
SW 12
R3
6.49 kW
BP10 11
7 VFB
R2
97.6 kW
HDRV 13
Si7860
LDRV 10
1.0 mF
R1
100 kW 180 mF
*optional
VOUT
180 mF
C3
330 pF
-
8 COMP
C2
22 pF
PGND 9
PWP
RBIAS
26.7 kW
Figure 18. 24 V to 3.3 V at 8-A DC-to-DC Converter Design Example
REFERENCES
1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2.
2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief
(SLMA002)
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REVISION HISTORY
Changes from Revision C (February 2012) to Revision D
•
28
Page
Changed ISINK current minimum from 8.5 µA to 7.5 µA for equation 16 ............................................................................. 15
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40055MPWPREP
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
40055M
V62/05617-01XE
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
40055M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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