TPS40100
www.ti.com
SLUS601 – MAY 2005
MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER
WITH ADVANCED SEQUENCING AND OUTPUT MARGINING
FEATURES
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APPLICATIONS
Operation over 4.5 V to 18 V Input Range
Adjustable Frequency (Between 100 kHz and
600 kHz) Current Feedback Control
Output Voltage Range From 0.7 V to 5.5 V
Simultaneous, Ratiometric and Sequential
Startup Sequencing
Adaptive Gate Drive
Remote Sensing (Via Separate GND/PGND)
Internal Gate Drivers for N-channel MOSFETs
Internal 5-V Regulator
24-Pin QFN Package
Thermal Shutdown
Programmable Overcurrent Protection
Power Good Indicator
1%, 690-mV Reference
Output Margining, 3% and 5%
Programmable UVLO (with Programmable
Hysteresis)
Frequency Synchronization
Servers
Networking Equipment
Cable Modems and Routers
XDSL Modems and Routers
Set-Top Boxes
Telecommunications Equipment
Power Supply Modules
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DESCRIPTION
The TPS40100 is a mid voltage, wide-input (between
4.5 V and 18 V), synchronous, step-down controller.
The TPS40100 offers programmable closed loop
soft-start, programmable UVLO (with programmable
hysteresis), programmable inductor sensed current
limit and can be synchronized to other timebases.
The TPS40100 incorporates MOSFET gate drivers
for external N-channel high-side and synchronous
rectifier (SR) MOSFET. Gate drive logic incorporates
adaptive anti-cross conduction circuitry for improved
efficiency, reducing both cross conduction and diode
conduction in the rectifier MOSFET. The externally
programmable current limit provides a hiccup
overcurrent recovery characteristic.
22
21
20
19
MGD
SYNC
PG
VO
ISNS
VIN
1
COMP
2
FB
3
TRKOUT
4
TRKIN
BST 15
5
UVLO
5VBP 14
6
ILIM
VDD 18
SW 17
HDRV 16
GND
SS
GM
PGND
TPS40100
BIAS
VTRKIN
23
RT
VIN
24
MGU
TYPICAL APPLICATION
7
8
9
10
11
12
LDRV 13
UDG−04137
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPS40100
www.ti.com
SLUS601 – MAY 2005
ORDERING INFORMATION
(1)
TA
PACKAGE
-40°C to 85°C
QFN
PART NUMBER (1)
TPS40100RGER
TPS40100RGET
The QFN package (RGE) is available taped and reeled only. Use
large reel device type R (TPS40100RGER) to order quantities of
3,000 per reel. Use small reel device type T (TPS40100RGET) to
order quantities of 250 per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS40100
VIN
Input voltage range
VDD
-0.3 to 20
5VBP, BIAS, FB, ILIM, ISNS, LDRV, MGU, MGD, PG, SS,
SYNC, UVLO, VO
-0.3 to 6
BST to SW, HDRV to SW (2)
-0.3 to 6.0
SW
-1.5 to VVIN
SW (transient) < 100 ns
IIN
Input current range
TRKIN
-0.3 to 20
GND to PGND
-0.3 to 0.3
TRKOUT
-0.3 to 8.0
HDRV, LDRV (RMS)
0.5
HDRV, LDRV (peak)
2.0
FB, COMP, TRKOUT
10 to -10
SS
20 to -20
PG
20
GM
1
RT
10
V5BP
50 (3)
RT source
100
Operating junction temperature range
–40 to 125
Tstg
Storage temperature
–55 to 150
(2)
(3)
2
V
-6 to 30
TJ
(1)
UNIT
A
mA
mA
µA
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
BST to SW and HDRV to SW are relative measurements. BST and HDRV can be this amount of voltage above or below the voltage at
SW.
V5BP current includes gate drive current requirements. Observe maximum TJ rating for the device.
TPS40100
www.ti.com
SLUS601 – MAY 2005
ELECTRICAL CHARACTERISTICS
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
18.0
V
2.5
mA
INPUT VOLTAGE
VVDD
Operating range
4.5
OPERATING CURRENT
IDD
Quiescent current
VFB > 0.8 V, 0% duty cycle
ISD
Shutdown current
VUVLO < 1 V
1.3
1.8
500
µA
5VPB
Internal regulator
7 V ≤ VVDD≤ 18 V, 0 mA ≤ ILOAD≤ 30 mA
4.7
5.0
5.3
4.5 V ≤ VVDD < 7 V, 0 mA ≤ ILOAD≤ 30 mA
4.3
5.0
5.3
V
OSCILLATOR/RAMP GENERATOR
fSW
Programmable oscillator frequency
Oscillator frequency accuracy
100
4.5 V ≤ VVDD < 18 V,
-40°C ≤ TA = TJ≤ 125°C
250
600
275
VRAMP
Ramp amplitude (1)
0.5
tOFF
Fixed off-time
100
DMIN
Minimum duty cycle
tMIN
Minimum controllable pulse width (1)
VVLY
Valley voltage (1)
300
kHz
VP-P
150
ns
0%
CLOAD = 4.7 nF, -40°C ≤ TA = TJ≤ 125°C
1.0
1.6
175
ns
2.0
V
FREQUENCY SYNCHRONIZATION
VIH
High-level input voltage
VIL
Low-level input voltage
ISYNC
Input current, SYNC
tSYNC
Mimimum pulse width, SYNC
tSYNC_SH
Minimum set-up/hold time, SYNC (2)
2
0.8
VSYNC = 2.5 V
4.0
5.5
10.0
50
V
µA
ns
100
SOFT-START AND FAULT IDLE
ISS
Soft-start source (charge) current
13
20
25
ISS_SINK
Soft-start sink (discharge) current
3.4
5.0
6.6
VSSC
Soft-start completed voltage
3.25
3.40
3.75
VSSD
Soft-start discharged voltage
0.15
0.20
0.25
300
500
800
Retry interval time to SS time ratio (1)
VSSOS
µA
V
16
Offset from SS to error amplifier
mV
ERROR AMPLIFIER
GBWP
Gain bandwidth product (1)
3.5
5.0
AVOL
Open loop
60
80
IBIAS
Input bias current, FB
IOH
High-level output current
2
3
IOL
Low-level output current
2
3
50
Slew rate (1)
MHz
dB
200
nA
mA
2.1
V/µs
FEEDBACK REFERENCE
VFB
(1)
(2)
Feedback voltage reference
TA =25°C
686
-40°C < TA = TJ≤ 125°C
683
690
694
697
mV
Ensured by design. Not production tested.
To meet set up time requirements for the synchronization circuit, a negative logic pulse must be greater than 100 ns wide.
3
TPS40100
www.ti.com
SLUS601 – MAY 2005
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE MARGINING
VFBMGU
IMGUP
VFBMGD
Feedback voltage margin 5% up
VMGU ≤ 500 mV
715
725
735
Feedback voltage margin 3% up
2 V ≤ VMGU ≤ 3 V
700
711
720
60
80
100
Feedback voltage margin 5% down
VMGD ≤ 500 mV
645
655
665
Feedback voltage margin 3% down
2 V ≤ VMGD ≤ 3 V
660
669
680
60
80
100
12
30
Margin-up bias current
IMGDN
Margin-down bias current
tMGDLY
Margining delay time (3)
tMGTRAN
Margining transition time
1.5
7.0
mV
µA
mA
µA
ms
CURRENT SENSE AMPLIFIER
gmCSA
Current sense amplifier gain
TCGM
Amplifier gain temperature coefficient
VGMLIN
Gm linear range voltage
TJ =25°C
IISNS
Bias current at ISNS pin
VVO = VISNS = 3.3 V
VGMCM
TJ =25°C
Input voltage common mode
300
333
365
-2000
4.5 V ≤ VIN ≤ 5.5 V
-50
µS
ppm/°C
50
mV
250
nA
0
6
0
3.6
V
CURRENT LIMIT
VILIM
ILIM pin voltage to trip overcurrent
tILIMDLY
Current limit comparator propagation delay
1.48
1.52
V
HDRV transition from on to off
1.44
70
140
ns
DRIVER SPECIFICATIONS
tRHDRV
HIgh-side driver rise time (4)
CLOAD = 4.7 nF
57
tFHDRV
HIgh-side driver fall time (4)
CLOAD = 4.7 nF
47
IHDRVSRPKS
HIgh-side driver peak source current (4)
IHDRVSRMIL
HIgh-side driver source current at 2.5 V (4)
IHSDVSNPK
HIgh-side driver peak sink current (4)
IHDRVSNMIL
High-side driver sink current at 2.5
V (4)
ns
800
VHDRV - VSW = 2.5 V
mA
700
1.3
VHDRV - VSW = 2.5 V
1.2
A
RHDRVUP
HIgh-side driver pullup resistance
IHDRV = 300 mA
2.4
4.0
RHDRVDN
HIgh-side driver pulldown resistance
IHDRV = 300 mA
1.0
1.8
tRLDRV
Low-side driver rise time (4)
CLOAD = 4.7 nF
57
CLOAD = 4.7 nF
47
VLDRV = 2.5 V
700
Low-side driver sink current at 2.5 V (4)
VLDRV = 2.5 V
1.2
RLDRVUP
Low-side driver pullup resistance
ILDRV = 300 mA
2.0
4.0
RLDRVDN
Low-side driver pulldown resistance
ILDRV = 300 mA
0.8
1.5
ISWLEAK
Leakage current from SW pin
time (4)
tFLDRV
Low-side driver fall
ILDRVSRPK
Low-side driver peak source current (4)
ILDRVSNMIL
Low-side driver source current at 2.5 V (4)
ILSDVSNPK
Low-side driver peak sink current (4)
ns
800
mA
1.3
-1
Ω
A
Ω
1
µA
30
100
mV
25
35
µs
1.00
1.25
V
POWERGOOD
VLPGD
Powergood low voltage
tPGD
Powergood delay time
IPGD= 2 mA
15
VVDD = OPEN, 10-kΩ pullup to external
5-V supply
VLPGDNP
Powergood low voltage , no device power
VOV
Power good overvoltage threshold, VFB
765
VUV
Power good undervoltage threshold, VFB
615
(3)
(4)
4
mV
Margining delay time is the time delay from an assertion of a margining command until the output voltage begins to transition to the
margined voltage.
Ensured by design. Not production tested.
TPS40100
www.ti.com
SLUS601 – MAY 2005
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7
25
40
-5
25
40
UNIT
TRACKING AMPLIFIER
VTRKOS
Tracking amplifier input offset voltage
VTRKCM
Input common mode, active range
VTRK
VTRKOS = VTRKIN - VO ; VVO≤ 2 V
VTRKOS = VTRKIN - VO ; 2 V < VVO≤ 6 V
4.5 V ≤ VVDD ≤ 5.5 V
Tracking amplifier voltage range
5 V < VVDD ≤ 18 V (5)
VHTKROUT
High-level output voltage, TRKOUT
VLTKROUT
Low-level output voltage, TRKOUT
ISRCTRKOUT
Source current, TRKOUT
ISNKTRKOUT
Sink current, TRKOUT
VTRKDIF
Differential voltage from TRKIN to VO
0
6
0
3.6
0
6
VVDD = 12 V
5.0
6.5
VVDD = 4.5 V
3.2
3.6
0
8.0
GBWPTRK
Tracking amplifier gain bandwidth
AVOLTRK
Tracking amplifier open loop DC gain (6)
V
0.5
0.65
2.00
1
2
mA
18
product (6)
mV
V
1
MHz
60
dB
PROGRAMMABLE UVLO
VUVLO
Undervoltage lockout threshold
IUVLO
Hysteresis current
1.285
1.332
1.378
V
9.0
10.0
10.8
µA
3.850
4.150
4.425
3.75
4.06
4.35
INTERNALLY FIXED UVLO
VUVLOFON
Fixed UVLO turn-on voltage at VDD pin
VUVLOFOFF
Fixed UVLO turn-off voltage at VDD pin
VUVLOHYST
UVLO hysteresis at VDD pin
-40°C ≤ TA < 125°C
85
V
mV
THERMAL SHUTDOWN
TSD
Thermal shutdown temerature (6)
TSDHYST
Hysteresis (6)
165
25
°C
Amplifier can track to the lesser of 6 V or (VDD × 0.95)
Ensured by design. Not production tested.
DEVICE INFORMATION
UVLO
ILIM
MGD
TRKIN
1
24
TRKOUT
MGU
FB
COMP
RGE PACKAGE
(BOTTOM VIEW)
2
3
4
5
6
7
RT
23
8
BIAS
SYNC
22
9
GND
PG
21
10
SS
VO
20
11
GM
PGND
LDRV
5VBP
BST
HDRV
19
12
18 17 16 15 14 13
SW
ISNS
VDD
(5)
(6)
130
5
TPS40100
www.ti.com
SLUS601 – MAY 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
14
O
Output of an internal 5-V regulator. A 1-µF bypass capacitor should be connected from this
pin to PGND. Power for external circuitry may be drawn from this pin. The total gate drive
current and external current draw should not cause the device to exceed thermal capabilities
BIAS
8
O
The bypassed supply for internal device circuitry. Connect a 0.1-µF or greater ceramic
capacitor from this pin to GND.
BST
15
I
Gate drive voltage for the high-side N-channel MOSFET. An external diode must be
connected from 5VBP (A) to BST(K). A schottky diode is recommended for this purpose. A
capacitor must be connected from this pin to the SW pin.
COMP
1
O
Output of the error amplifier. A feedback network is connected from this pin to the FB pin for
control loop compensation.
FB
2
I
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to
the internal reference voltage (approximately 690 mV).
GM
11
I
Connect a resistor from this pin to GND to set the gain of the current sense amplifier.
GND
9
-
Low power or signal ground for the device. All signal level circuits should be referenced to
this pin unless otherwise noted.
HDRV
16
O
Floating gate drive for the high side N-channel MOSFET.
NAME
NO.
5VBP
ILIM
6
O
Current limit pin used to set the overcurrent threshold and transient ride out time. An internal
current source that is proportional to the inductor current sets a voltage on a resistor
connected from this pin to GND. When this voltage reaches 1.48 V, an overcurrent condition
is declared by the device. Adding a capacitor in parallel with the resistor to GND sets a time
delay that can be used to help avoid nuisance trips.
ISNS
19
I
Input from the inductor DCR sensing network. This input signal is one of the inputs to the
current sense amplifier for current feedback control and overcurrent protection
LDRV
13
O
Gate drive for the N-channel synchronous rectifier.
MGD
23
I
Margin down pin used for load stress test. When this pin is pulled to GND through less than
10 kΩ, the output voltage is decreased by 5%. The 3% margin down at the output voltage is
accommodated when this pin is connected to GND through a 30-kΩ resistor.
MGU
24
I
Margin up pin used for load stress test. When this pin is pulled to GND through less than 10
kΩ, the output voltage is increased by 5%. The 3% margin up at the output voltage is
accommodated when this pin is connected to GND through a 30-kΩ resistor.
PG
21
O
Open drain power good output for the device. This pin is pulled low when the voltage at the
FB pin is more than 10% higher or lower than 690 mV, a UVLO condition exists, soft-start is
active, tracking is active, an overcurrent condition exists or the die is over temperature.
PGND
12
-
Power ground for internal drivers
RT
7
I
A resistor connected from this pin to GND sets operating frequency.
SS
10
I
Soft-start programming pin. A capacitor connected from this pin to ground programs the
soft-start time. This pin is also used as a time out function during an overcurrent event.
SW
17
I
Connected to the switched node of the converter. This pin is the return line for the flying high
side driver.
SYNC
22
I
Rising edge triggered synchronization input for the device. This pin can be used to
synchronize the oscillator frequency to an external master clock. This pin may be left floating
or grounded if the function is not used.
TRKIN
4
I
Control input allowing simultaneous startup of multiple controllers. The converter output
tracks TRKIN voltage with a small controlled offset (typically 25 mV) when the tracking
amplifier is used. See application secttion for more information.
TRKOUT
3
O
Output of the tracking amplifier. If the tracking feature is used, this pin should be connected
to FB pin through a resistor in series with a diode. The resistor value can be calculated from
the equivalent impedance at the FB node. The diode should be a low leakage type to
minimize errors due to diode reverse current. For further information on compensation of the
tracking amplifier refer to the application information
UVLO
5
I
Provides for programming the undervoltage lockout level and serves as a shutdown input for
the device.
VDD
18
I
Supply voltage for the device.
VO
20
I
Output voltage. This is the reference input to the current sense amplifier for current mode
control and overcurrent protection.
6
TPS40100
www.ti.com
SLUS601 – MAY 2005
FUNCTIONAL BLOCK DIAGRAM
RT
SYNC
UVLO
7
22
5
TPS40100
Oscillator
COMP
1
FB
2
1.33 V
CLK
MGD 23
16 HDRV
10 µA
PWM
20 kΩ
SS
+
+
OC
0.725 V
MGU 24
15 BST
UVLO
+
Reference
Select
FAULT
0.711 V
0.690 V
Adaptive
Gate
Drive
and
Prebias
Control
17 SW
14 5VBP
CLK
13 LDRV
0.669 V
0.655 V
12 PGND
+
+
ISNS 19
OC
1.48 V
+
VO 20
Current
Mirror
21 PG
THERMSD
+
1.5 V
CLK
OC
GM 11
TRKOUT
3
OC/SS
Controller
FAULT
Reference
Voltages
Housekeeping
+
18 VDD
TRKIN 4
6
10
ILIM
SS
9
8
GND
BIAS
UDG−04142
7
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION
Introduction
The TPS40100 is a synchronous buck controller targeted at applications that require sequencing and output
voltage margining features. This controller uses a current feedback mechanism to make loop compensation
easier for loads that can have wide capacitance variations. Current sensing (for both current feedback and
overcurrent) is true differential and can be done using the inductor DC resistance (with a R-C filter) or with a
separate sense resistor in series with the inductor. The overcurrent level is programmable independently from
the amount of current feedback providing greater application flexibility. Likewise, the overcurrent function has
user programmable integration to eliminate nuisance tripping and allow the user to tailor the response to
application requirements. The controller provides an integrated method to margin the output voltage to ± 3% and
± 5% of its nominal value by simply grounding one of two pins directly or through a resistance. Powergood and
clock synchronization functions are provided on dedicated pins. Users can program operating frequency and the
closed loop soft-start time by means of a resistor and capacitor to ground respectively. Output sequencing/tracking can be accomplished in one of three ways: sequential (one output comes up, then a second
comes up), ratiometric (one or more outputs reach regulation at the same time – the voltages all follow a
constant ration while starting) and simultaneous (one or more outputs track together on startup and reach
regulation in order from lowest to highest).
Programming Operating Frequency
Operating frequency is set by connecting a resistor to GND from the RT pin. The relationship is:
ȡ
ȧ
Ȣ
ȣ
ȧ
Ȥ
ǒ
Ǔ
4
4
R T + * 3.98 2 10 ) 5.14 10 * 8.6 (kW)
f
SW
f SW
(1)
where
•
•
fSW is the switching frequency in kHz
RT is in kΩ
Figure 1 and Figure 2 show the relationship between the switching frequency and the RT resistor as described in
Equation 1. The scaling is different between them to allow the user a more accurate views at both high and low
frequency.
8
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
TIMING RESISTOR
vs
SWITCHING FREQUENCY
(250 kHz to 600 kHz)
TIMING RESISTOR
vs
SWITCHING FREQUENCY
(100 kHz to 350 kHz)
225
550
500
200
RT − Timing Resistance − kΩ
RT − Timing Resistance − kΩ
450
175
150
125
100
75
400
350
300
250
200
150
50
250
300
350
400
450
500
550
600
100
100
fSW − Switching Frequency − kHz
Figure 1.
150
200
250
300
350
f − Switching Frequency − kHz
Figure 2.
Selecting an Inductor Value
The inductor value determines the ripple current in the output capacitors and has an effect on the achievable
transient response. A large inductance decreases ripple current and output voltage ripple, but is physically larger
than a smaller inductance at the same current rating and limits output current slew rate more that a smaller
inductance would. A lower inductance increases ripple current and output voltage ripple, but is physically smaller
than a larger inductance at the same current rating. For most applications, a good compromise is selecting an
inductance value that gives a ripple current between 20% and 30% of the full load current of the converter. The
required inductance for a given ripple current can be found from:
L+
ǒV IN * V OUTǓ
VIN
f SW
V OUT
DI
(H)
(2)
where
•
•
•
•
•
L is the inductance value (H)
VIN is the input voltage to the converter (V)
VOUT is the output voltage of the converter (V)
fSW is the switching frequency chosen for the converter (Hz)
∆I is the peak-to-peak ripple current in the inductor (A)
Selecting the Output Capacitance
The required value for the output capacitance depends on the output ripple voltage requirements and the ripple
current in the inductor, as well as any load transient specifications that may exist.
The output voltage ripple depends directly on the ripple current and is affected by two parameters from the
output capacitor: total capacitance and the capacitors equivalent series resistance (ESR). The output ripple
voltage (worst case) can be found from:
9
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
ƪ
DV + DI
ESR )
ǒ
Ǔƫ
1
C OUT
8
f SW
(V)
(3)
where
•
•
•
•
•
∆V is the peak to peak output ripple voltage (V)
∆I is the peak-to-peak ripple current in the inductor (A)
fSW is the switching frequency chosen for the converter (Hz)
COUT is the capacitance value of the output capacitor (F)
ESR is the equivalent series resistance of the capacitor, COUT (Ω)
For electrolytic capacitors, the output ripple voltage is almost entirely (90% or more) due to the ESR of the
capacitor. When using ceramic output capacitors, the output ripple contribution from ESR is much smaller and
the capacitance value itself becomes more significant. Paralleling output capacitors to achieve a desired output
capacitance generally lowers the effective ESR more effectively than using a single larger capacitor. This
increases performance at the expense of board area.
If there are load transient requirements that must be met, the overshoot and undershoot of the output voltage
must be considered. If the load suddenly increases, the output voltage momentarily dips until the current in the
inductor can ramp up to match the new load requirement. If the feedback loop is designed aggressively, this
undershoot can be minimized. For a given undershoot specification, the required output capacitance can be
found by:
C O(under) +
L
2
V UNDER
I STEP
2
D MAX
ǒV IN * V OUTǓ
(F)
(4)
where
•
•
•
•
•
•
•
CO(under) is the output capacitance required to meet the undershoot specification (F)
L is the inductor value (H)
ISTEP is the change in load current (A)
VUNDER is the maximum allowable output voltage undershoot
DMAX is the maximum duty cycle for the converter
VIN is the input voltage
VOUT is the output voltage
Similarly, if the load current suddenly goes from a high value to a low value, the output voltage overshoots. The
ouput voltage rises until the current in the inductor drops to the new load current. The required capacitance for a
given amount of overshoot can be found by:
2
C O(over) +
2
L I STEP
V OVER V OUT
(F)
(5)
where
•
•
•
•
•
CO(over) is the output capacitance required to meet the undershoot specification (F)
L in the inductor value (H)
ISTEP is the change in load current (A)
VOVER is the maximum allowable output voltage overshoot
VOUT is the output voltage
The required value of output capacitance is the maximum of CO(under) and CO(over).
Knowing the inductor ripple current, the switching frequency, the required load step and the allowable output
voltage excursion allows calculation of the required output capacitance from a transient response perspective.
The actual value and type of output capacitance is the one that satisfies both the ripple and transient
specifications.
10
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
Calculating the Current Sense Filter Network
The TPS 40100 gets current feedback information by sensing the voltage across the inductor resistance, RLDC. In
order to do this, a filter must be constructed that allows the sensed voltage to be representative of the actual
current in the inductor. This filter is a series R-C network connected across the inductor as shown in Figure 3.
To ISNS pin
VIN
RFLT
L
To VO pin
CFLT
RLDC
100 Ω
VO
CO
UDG−04150
Figure 3. Current Sensing Filter Circuit
If the RFLT-CFLT time constant is matched to the L/RLDC time constant, the voltage across CFLT is equal to the
voltage across RLDC. It is recommended to keep RFLT 10 kΩ or less. CFLT can be arbitrarily chosen to meet this
condition (100 nF is suggested). RFLT can then be calculated.
L
R FLT +
* 100 (W)
RLDC CFLT
(6)
where
•
•
•
•
RFLT is the current sense filter resistance (Ω)
CFLT is the current sense filter capacitance (F)
L is the output inductance (H)
RLDC is the DC resistance of the output inductor (Ω)
When laying out the board, better performance can be accomplished by locating CFLT as close as possible to the
VO and ISNS pins. The closer the two resistors can be brought to the device the better as this reduces the
length of high impedance runs that are susceptible to noise pickup. The 100-Ω resistor from VOUT to the VO pin
of the device is to limit current in the event that the output voltage dips below ground when a short is applied to
the output of the converter.
Compensation for Inductor Resistance Change Over Temperature
The resistance in the inductor that is sensed is the resistance of the copper winding. This value changes over
temperature and has approximately a 4000 ppm/°C temperature coefficient. The gain of current sense amplifier
in the TPS40100 has a built in temperature coefficient of approximately -2000 ppm/°C. If the circuit is physically
arranged so that there is good thermal coupling between the inductor and the device, the thermal shifts tend to
offset. If the thermal coupling is perfect, the net temperature coefficient is 2000 ppm/°C. If the coupling is not
perfect, the net temperature coefficient lies between 2000 ppm/°C and 4000 ppm/°C. For most applications this is
sufficient. If desired, the temperature drifts can be compensated for. The following compensation scheme
assumes that the temperature rise at the device is directly proportional to the temperature rise at the inductor. If
this is not the case, compensation accuracy suffers. Also, there is generally a time lag in the temperature rise at
the device vs. at the inductor that could introduce transient errors beyond those predicted by the compensation.
Also, the 100-Ω resistor in Figure 3 is not shown. However, it is required if the output voltage can dip below
ground during fault conditions. The calculations are not afffected, other than increasing the effective value of RF1
by 100-Ω.
11
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
The relative resistance change in the inductor is given by:
R REL(L) + 1 ) TC L ǒT L * T BASEǓ (dimensionless)
(7)
where
•
•
•
•
RREL(L) is the relative resistance of the inductor at TL compared to the resistance at TBASE
TCL is the temperature coefficient of copper, 4000 ppm/°C or 0.004
TL is the inductor copper temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
The relative gain of the current sense amplifier is given by a similar equation:
gm (REL) + 1 ) TC GM ǒT IC * T BASEǓ (dimensionless)
(8)
where
•
•
•
•
gmREL is the relative gain of the amplifier at TIC compared to the gain at TBASE
TCGM is the temperature coefficient of the amplifier gain, -2000 ppm/°C or -0.002
TIC is the device junction temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
The temperature rise of the device can usually be related to the temperature rise of the inductor. The relationship
between the two temperature rises can be approximated as a linear relationship in most cases:
T IC * T BASE + ǒT L * T BASEǓ k THM
(9)
where
•
•
•
•
TIC is the device junction temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
TL is the inductor copper temperature (°C)
kTHM is the constant that relates device temperature rise to the inductor temperature rise and must be
determined experimentally for any given design
With these assumptions, the effective inductor resistance over temperature is:
R REL(eff) + RREL(L)
gm REL + ƪ1 ) TC LǒT L * T BASEǓƫ
ƪ1 ) k THM
TC GM
ǒT L * TBASEǓƫ
(dimensionless)
(10)
RREL(eff) is the relative effective resistance that must be compensated for when doing the compensation. The
circuit of Figure 4 shows a method of compensating for thermal shifts in current limit. The NTC thermistor (RNTC)
must be well coupled to the inductor. CFLT should be located as close to the device as possible.
12
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
VO
20
ILIM
6
RILIM
ISNS
+
−2000 ppm/°C
19
RTHE
RF3
RF2
RNTC
VIN
CFLT
RF1
L
RLDG
VOUT
COUT
UDG−04148
Figure 4. Compensation for Temperature Coefficient of the Inductor Resistance
The first step is to determine an attenuation ratio α. This ratio should be near to 1 but not too close. If it is too
close to 1, the circuit requires large impedances and thermistor values too high. If α is too low, the current signal
is attenuated unnecessarily. A suggested value is 0.8.
R THE
a ^ 0.8
(dimensionless)
R THE ) R F1
(11)
RTHE is the equivalent resistance of the RF2-RF3-RNTC network:
R
RNTC
R THE + RF2 ) F3
(W)
RF3 ) RNTC
(12)
The base temperature (TBASE) should be selected to be the lowest temperature of interest for the thermal
matching – the lowest ambient expected. The resistance of the inductor at this base temperature should be used
to calculate effective resistance. The expected current sense amplifier gain at TBASE should be used for
calculating over current components (RILIM).
The next step is to decide at what two temperatures the compensation is matched to the response of the
deviceand inductor copper, T1 and T2. Once these are chosen, an NTC thermistor can be chosen and its value
found from its data sheet at these two temperatures: RNTC(T1) and RNTC(T2). The component values in the network
can be calculated using the following equations:
13
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
R F1 +
L
RLDC(Tbase)
C FLT a
(W)
(13)
R LDC(T1) + RLDC(Tbase)
RREL(effT1) (W)
(14)
R LDC(T2) + RLDC(Tbase)
RREL(effT2) (W)
(15)
R THE(T1) +
R THE(T2) +
a +1*
a
R LDC(Tbase)
RLDC(T1) * a
a
R LDC(Tbase)
R LDC(Tbase)
RLDC(T2) * a
R F1
R F1
R LDC(Tbase)
RNTC(T1) * RNTC(T2)
RTHE(T1) * RTHE(T2)
(W)
(16)
(W)
(17)
(dimensionless)
(18)
b + R NTC(T1) ) R NTC(T2) (W)
R NTC(T2)
(W2)
* b " Ǹb 2 * 4ac
2a
(W)
c + R NTC(T1)
R F3 +
R F2 +
RTHE(T1)
ǒRF3 ) RNTC(T1)Ǔ * RF3
RF3 ) R NTC(T1)
(19)
(20)
(21)
R NTC(T1)
(W)
(22)
where
•
•
•
•
•
•
•
•
L is the value of the output inductance (H)
CFLT is the value of the current sense filter capacitor (F)
α is the attenuation ratio chosen from Equation 11
RTHE(T1), RTHE(T2) are the equivalent resistances of the RTHE network at temperatures T1 and T2
RLDC(Tbase) is the DC resistance of the inductor at temperature TBASE in Ω
RLDC(T1), RLDC(T2) are the inductor resistances at temperatures T1 and T2
RREL(effT1), RREL(effT2), are the relative resistances of the inductor at T1 and T2 vs. Tbase
RNCT(T1), RNTC(T2) are the effective resistance of the NTC thermistor at temperatures T1 and T2
Establishing Current Feedback
The amount of current feedback in a given application is programmable by the user. The amount of current
feedback used is intended to be just enough to reduce the Q of the output filter double pole. This allows design
of a converter control loop that is stable for a very wide range of output capacitance. Setting the current feedback
higher offers little real benefit and can actually degrade load transient response, as well as introduce pulse
skipping in the converter. The current feedback is adjusted by setting the gain of the current sense amplifier. The
amplifier is a transconductance type and its gain is a set by connecting a resistor from the GM pin to GND:
3
R GM +
(W)
2
43.443 gm CSA ) 0.01543 gm CSA ) 3.225 10 *6
(23)
where
•
•
RGM is the resistor that sets the gain of the amplifier (Ω)
gmCSA is the gain of the current sense amplifier (S)
The value of the sense amplifier gain should be less than 1000 µS, and more than 250 µS, with the resulting
gain setting resistor greater than 50 kΩ. As a suggested starting point, set the gain of the current sense amplifier
to a nominal 280 µS with RGM of 279 kΩ. This value should accommodate most applications adequately.
Figure 5 shows the current sense amplifier gain setting resistance vs. the sense amplifier gain.
14
TPS40100
www.ti.com
SLUS601 – MAY 2005
APPLICATION INFORMATION (continued)
RGM − Gain Setting Resistance − kΩ
CURRENT SENSE AMPLIFIER GAIN SETTING RESISTANCE
vs
CURRENT SENSE AMPLIFIER GAIN
325
275
225
175
125
75
25
250
400
550
700
850
1000
gm − Sense Amplifier Transconductance − µS
Figure 5.
Control to Output Gain of the Converter
A model that gives a good first order approximation to the control to output gain of a converter based on the
TPS40100 controller is shown in Figure 6. This model can be used in conjunction with a simulator to generate ac
and transient response plots. The block labeled “X2” is a simple gain of 2. The amplifier gm can be a simple
voltage controlled current source with a gain equal to the selected gm for the current sense amplifier (CSA).
Analytically, the control to output gain of this model ( Figure 6) can be expressed as follows:
V IN K PWM K FILT(s)
K CO(s) +
(dimensionless)
1 ) Y(s) KCS KPWM VIN
(24)
KFILT(s) is the output filter transfer function:
KFILT(s) =
R LOAD
R LDC ) R LOAD
R ESR
L
C OUT)RLOAD
RLDC)R LOAD
s2 )
COUT
L)C OUT ǒRLOAD
s)1
R ESR)R LDC
R LOAD
RLOAD)R LDC
RESRǓ
s)1
(25)
(dimensionless)
Usually, RLDC 0.7 V)
• VFB < 0.61 V
• VFB > 0.77 V
• VUVLO < 1.33 V
• Overcurrent condition exists
• Die temperature is greater than 165°C
A short filter (20 µs) must be overcome before PGD pulls to GND from a high state to allow for short transient
conditions and noise and not indicate a power NOT good condition.
The PGD pin attempts to pull low in the absence of input power. If the VDD pin is open circuited, the voltage on
PGD typically behaves as shown in Figure 17.
26
TPS40100
www.ti.com
SLUS601 – MAY 2005
POWERGOOD VOLTAGE
vs
POWERGOOD CURRENT
2.5
VVDD = 0 V
VPGD − Powergood Voltage − V
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
IPGD − Powergood Current − mA
Figure 17.
Pre-Bias Operation
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the
output. Since synchronous buck converters inherently sink current some method of overcoming this characteristic
must be employed. Applications that require this operation are typically power rails for a multiple supply
processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn on until
there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage. This is
detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller
uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage is
commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current
only during the startup sequence. If the pre-existing voltage is higher that the intended regulation point for the
output of the converter, the converter starts and sinks current when the soft-start time has completed.
Remote Sense
The TPS 40100 is capable of remotely sensing the load voltage to improve load regulation. This is accomplished
by connecting the GND pin of the device and the feedback voltage divider as near to the load as possible.
CAUTION:
Long distance runs for the GND pin will cause erratic controller behavior.
This begins to appear as increased pulse width jitter. As a starting point, the GND pin connection should be no
further than six inches from the PGND connection. The actual distance that starts causing erratic behavior is
application and layout dependent and must be evaluated on an individual basis. If the controller exhibits output
pulse jitter in excess of 25 ns and the GND pin is tied to the load ground, connecting the GND pin closer to the
PGND pin (and thereby sacrificing some load regulation) may improve performance. In either case, connecting
the feedback voltage divider at the point of load should not cause any problems. For layout, the voltage divider
components should be close to the device and a trace can be run from there to the load point.
27
TPS40100
www.ti.com
SLUS601 – MAY 2005
Application Schematics
Margin down 3%
Power Good Indication
3.3 V to 5 V logic supply or 5VBP pin
27 kΩ
Margin up 3%
2N7002
27 kΩ
2N7002
12 V
10 kΩ
1
COMP
2
FB
12 V
ISNS
PG
19
VDD 18
Si73444DP
SW 17
TRKOUT
MMBD1501A
200 kΩ
20
HDRV 16
TPS40100
47 nF
4
100 nF
BST 15
TRKIN
4.99 kΩ
BAT54
5
UVLO
5VBP 14
6
ILIM
LDRV 13
VOUT
470 µF
1.2 V
Panasonic
15 A
EEF−SEOD471R
100 pF
GND
SS
GM
PGND
13.7 kΩ
BIAS
1 µF
40.2 kΩ
RT
Si7868DP
2
7
8
9
10
11
12
158 kΩ
1 µF
270 kΩ
162 kΩ
1 µF
5.9 kΩ 100 nF
1.0 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
30 kΩ
3
100 kΩ
21
VO
14.3 kΩ
22
SYNC
MGU
VOUT
Connect at load 300 pF
23
MGD
24
47 pF
1
1
150 nF
10 nF
(if required)
1
22 µF TDK C4532X7R1C226M
2
Open switch after input power is stable and SS capacitor had finished charging.
10 Ω
BAT54S
(if required)
Remote
GND Sense
Connect at
Load
UDG−04140
Figure 18. 300-kHz, 12-V to 1.2-V Converter With Tracking Startup Capability and Remote Sensing
28
TPS40100
www.ti.com
SLUS601 – MAY 2005
Margin down 5%
Power Good Indication
3.3 V to 5 V logic supply or 5VBP pin
Margin up 5%
2N7002
3.32 kΩ
12 V 330 pF
10 kΩ
1
COMP
2
FB
21
20
VO
22
19
12 V
ISNS
6.2 kΩ
23
PG
MGU
3.9 nF
24
SYNC
47 pF
VOUT
Connect at load
MGD
2N7002
VDD 18
Si7344DP
5.9 kΩ 100 nF
SW 17
1.0 µH
COEV
15 kΩ
3
MMBD1501A
100 kΩ 200 kΩ
TRKOUT
TPS40100
47 nF
VOUT
3.3 V
15 A
DXM1306−1R0
HDRV 16
1.7 mΩ (typ)
100 nF
4
TRKIN
BST 15
5
UVLO
5VBP 14
6
ILIM
LDRV 13
4.99 kΩ
100 pF
GND
SS
GM
PGND
40.2 kΩ 2.67 kΩ
BIAS
1 µF
RT
3
7
8
9
10
11
12
BAT54
2
Si7868DP
120 kΩ 1 µF
1
150 nF 270 kΩ
1
22 µF TDK C4532X7R1C226M
2
100 µF TDK C3225X5ROJ107M
3
Open switch after input power is stable and SS capacitor had finished charging.
2
1 µF
1
158 kΩ
2
UDG−04141
Figure 19. 400-kHz, 12-V to 3.3-V Converter With Tracking Capability and 5% Margining
29
TPS40100
www.ti.com
SLUS601 – MAY 2005
12 V
22
21
14.3 kΩ
1
COMP
2
FB
20
19
12 V
ISNS
23
VO
24
PG
NC
SYNC
NC
MGU
300 pF
NC
MGD
47 pF
10 kΩ
NC
VDD 18
5.9 kΩ
Si73444DP
SW 17
200 kΩ
NC
3
TRKOUT
NC
4
TRKIN
BST 15
5
UVLO
5VBP 14
1 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
HDRV 16
TPS40100
100 nF
100 nF
BAT54
470 µF
Panasonic
EEF−SEOD471R
Si7868DP
100 pF
GND
SS
GM
PGND
13.7 kΩ
BIAS
40.2 kΩ
LDRV 13
ILIM
RT
6
7
8
9
10
11
12
158 kΩ
1
1 µF
VOUT
1.2 V
15 A
1
270 kΩ
187 kΩ
1 µF
150 nF
1
22 µF TDK C4532X7R1C226M
UDG−05063
Figure 20. Minimal Application for 12-V to 1-V Converter
30
TPS40100
www.ti.com
SLUS601 – MAY 2005
NC
22
21
1
COMP
2
FB
3
TRKOUT
20
19
VO
PG
23
12 V
ISNS
14.3 kΩ
12 V
NC
24
SYNC
300 pF
NC
MGD
47 pF
MGU
10 kΩ
VDD 18
SW 17
1 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
HDRV 16
TPS40100
NC
5.9 kΩ 100 nF
Si73444DP
100 nF
4
TRKIN
BST 15
5
UVLO
5VBP 14
6
ILIM
LDRV 13
200 kΩ
BAT54
470 µF
Panasonic
EEF−SEOD471R
SS
GM
PGND
7
8
9
10
11
12
158 kΩ
187 kΩ 1 µF
23
1
COMP
2
FB
3
TRKOUT
22
21
PG
24
Power
Good
20
19
VDD 18
12 V
Si7344DP
SW 17
12 V
NC
HDRV 16
100 pF
5VBP 14
6
ILIM
LDRV 13
PGND
UVLO
GM
5
SS
BST 15
GND
2.67 kΩ
TRKIN
BIAS
40.2 kΩ
100 nF
4
RT
NC
7
8
9
10
11
12
BAT54
Si7868DP
2
1 µF
158 kΩ
120 kΩ
1 µF
5.9 kΩ 100 nF
1 µH
COEV
DZM1306−1R
3 mΩ (typ)
TPS40100
200 kΩ
1
ISNS
6.2 kΩ
330 pF
NC
VO
3.9 nF
1
10 kΩ
SYNC
470 pF
NC
MGU
3.32 kΩ
External 5 V
150 nF
External
Clock
50%
Duty
10 kΩ
VOUT
1.2 V
15 A
1 µF
270 kΩ
MGD
100 pF
GND
13.7 kΩ
BIAS
40.2 kΩ
RT
Si7868DP
150 nF 270 kΩ
1
2
2
VOUT
3.3 V
15 A
1
1
22 µF TDK C4532X7R1C226M
2
100 µF TDK C3225X5ROJ107M
UDG−05064
Figure 21. Sequenced Supplies, With Oscillators 180 Degrees Out of Phase
31
TPS40100
www.ti.com
SLUS601 – MAY 2005
200 kΩ
22
21
20
1
COMP
2
FB
3
TRKOUT
19
External
5V
12 V
ISNS
14.3 kΩ
23
PG
300 pF
NC
24
VO
12 V
NC
SYNC
47 pF
MGD
10 kΩ
MGU
10 kΩ
VDD 18
5.9 kΩ
Si73444DP
100 nF
SW 17
30 kΩ
MMBD1501A
4.99 kΩ
HDRV 16
TPS40100
47 nF
100 nF
4
TRKIN
BST 15
5
UVLO
5VBP 14
BAT54
VOUT
1.2 V
15 A
Si7868DP
ILIM
BIAS
GND
SS
GM
PGND
7
8
9
10
11
12
40.2 kΩ
13.7 kΩ
LDRV 13
RT
6
158 kΩ
470 µF
Panasonic
EEF−SEOD471R
1 µF
270 kΩ
100 pF
1
470 µF
Panasonic
EEF−SEOD471R
1
150 nF
187 kΩ 1 µF
External Clock,
50% duty
Power
Good
NC
24
23
12 V
12 V
1
COMP
2
FB
20
3
2.67 kΩ
BST 15
5
UVLO
5VBP 14
6
ILIM
LDRV 13
100 pF
PGND
40.2 kΩ
TRKIN
GM
2.2 µF
7
8
9
10
11
12
22 µF TDK C4532X7R1C226M
2
100 µF TDK C3225X5ROJ107M
120 kΩ 1 µF
Si7868DP
2
1 µF
150 nF
3 Open switch after input power is stable and SS capacitor has finished charging.
Figure 22. Tracking Supplies
32
BAT54
1
2
VOUT
3.3 V
15
A
2
1
270 kΩ
158 kΩ
1
100 nF
4
SS
3
5.9 kΩ 100 nF
1 µH
COEV
DZM1306−1R
3 mΩ (typ)
HDRV 16
TPS40100
47 nF
GND
4.99 kΩ
TRKOUT
BIAS
MMBD1501A
Si7344DP
SW 17
RT
200 kΩ
12 V
VDD 18
15 kΩ
47 kΩ
19
ISNS
PG
21
VO
6.2 kΩ
22
SYNC
3.9 nF
MGU
470 pF
330 pF
NC
10 kΩ
MGD
3.32 kΩ
UDG−05066
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS40100RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
40100
Samples
TPS40100RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
40100
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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