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TPS51116
SLUS609J – MAY 2004 – REVISED JANUARY 2018
TPS51116 Complete DDR, DDR2, DDR3, DDR3L, LPDDR3 and DDR4 Power Solution
Synchronous Buck Controller, 3-A LDO, Buffered Reference
1 Features
2 Applications
•
•
1
•
Synchronous Buck Controller (VDDQ)
– Wide-Input Voltage Range: 3.0-V to 28-V
– D−CAP™ Mode with 100-ns Load Step
Response
– Current Mode Option Supports Ceramic
Output Capacitors
– Supports Soft-Off in S4/S5 States
– Current Sensing from RDS(on) or Resistor
– 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V
(LPDDR3 and DDR4) or
Output Range 0.75-V to 3.0-V
– Equipped with Powergood, Overvoltage
Protection and Undervoltage Protection
3-A LDO (VTT), Buffered Reference (VREF)
– Capable to Sink and Source 3 A
– LDO Input Available to Optimize Power Losses
– Requires only 20-μF Ceramic Output Capacitor
– Buffered Low Noise 10-mA VREF Output
– Accuracy ±20 mV for both VREF and VTT
– Supports High-Z in S3 and Soft-Off in S4/S5
– Thermal Shutdown
•
DDR/DDR2/DDR3/DDR3L/LPDDR3/DDR4
Memory Power Supplies
SSTL-2, SSTL-18, SSTL-15 and HSTL
Termination
3 Description
The TPS51116 provides a complete power supply for
DDR/SSTL-2,
DDR2/SSTL-18,
DDR3/SSTL-15,
DDR3L, LPDDR3 and DDR4 memory systems. It
integrates a synchronous buck controller with a 3-A
sink/source tracking linear regulator and buffered low
noise reference. The device offers the lowest total
solution cost in systems where space is at a
premium. The synchronous controller runs fixed 400kHz, pseudo-constant frequency PWM with an
adaptive on-time control that can be configured in DCAP™ Mode for ease of use and fastest transient
response or in current mode to support ceramic
output capacitors. The 3-A sink/source LDO
maintains fast transient response only requiring 20-μF
(2 × 10 μF) of ceramic output capacitance. In
addition, the LDO supply input is available externally
to significantly reduce the total power losses. The
device supports all of the sleep state controls placing
VTT at high-Z in S3 (suspend to RAM) and
discharging VDDQ, VTT and VTTREF (soft-off) in
S4/S5 (suspend to disk). The device has all of the
protection features including thermal shutdown and is
offered in both a 20-pin HTSSOP PowerPAD™
package and 24-pin 4 × 4 QFN.
4 Typical Application
VIN
M1
IRF7821
C1
Ceramic
0.1 µF
VTT
0.9 V
2A
24
23
22
21
VTT VLDOIN VBST
VREF
0.9 V 10 mA
20
C5
2 × 10 µF
VDDQ
1.8 V
10 A
19
LL DRVL
1
VTTGND
CS_GND 17
2
VTTSNS
PGND 18
3
GND
CS 16
M2
IRF7832
C6
SP-CAP
2 × 150 µF
R1 5.1 Ÿ
TPS51116
4
C3
Ceramic
2 × 10 µF
DRVH
L1 1 µH
MODE
V5IN 15
5V_IN
R3 5.1 Ÿ
C4
Ceramic
0.033 µF
5
VTTREF
6
COMP
V5FILT 14
PGOOD 13
NC VDDQSNS
7
8
VDDQSET
S3
S5
NC
9
10
11
12
S3
S5
R2
100 NŸ
C7
Ceramic
1 µF
C2
Ceramic
1 µF
PGOOD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51116
SLUS609J – MAY 2004 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Dissipation Ratings ..................................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 DDR3 Application With Current Mode ................... 28
9.3 DDR3 Application With D−CAP™ Mode ................ 32
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (March 2012) to Revision J
Page
•
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added descriptions and specification for DDR4 operating mode thoughout the data sheet.................................................. 1
•
Clarified graphs in Typical Characteristics section................................................................................................................. 9
Changes from Revision H (July 2009) to Revision I
Page
•
Added clarity to Features section ........................................................................................................................................... 1
•
Added reference to "SSTL-15" in Applications section ......................................................................................................... 1
•
Added references to "LPDDR3 " to the Title and Description sections .................................................................................. 1
•
Added references to "LPDDR3 " to the Detailed Description section .................................................................................. 19
•
Added clarity to Figure 34..................................................................................................................................................... 21
2
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SLUS609J – MAY 2004 – REVISED JANUARY 2018
6 Pin Configuration and Functions
MODE
VTTREF
COMP
1
24
GND
VTT
2
3
4
5
6
7
NC
VDDQSNS
VBST
22
9
VDDQSET
DRVH
21
10
S3
LL
20
11
S5
12
19
18 17 16 15 14 13
NC
PGND
DRVL
PGOOD
8
V5FILT
23
V5IN
VLDOIN
CS
VBST
DRVH
LL
DRVL
PGND
CS
V5IN
PGOOD
S5
S3
CS_GND
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VLDOIN
VTT
VTTGND
VTTSNS
GND
MODE
VTTREF
COMP
VDDQSNS
VDDQSET
VTTGND
PWP Package
20-Pin HTSSOP
Top View
VTTSNS
RGE Package
24-Pin QFN
Top View
Pin Functions
NAME
NO.
I/O
DESCRIPTION
PWP
RGE
COMP
8
6
I/O
Output of the transconductance amplifier for phase compensation. Connect to V5IN pin to
disable gM amplifier and use D-CAP mode.
CS
15
16
I/O
Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip
voltage setting input for RDS(on) current sense scheme if connected to V5IN (PWP), V5FILT
(RGE) through the voltage setting resistor.
DRVH
19
21
O
Switching (high-side) MOSFET gate-drive output.
DRVL
17
19
O
Rectifying (low-side) MOSFET gate-drive output.
GND
5
3
-
Signal ground. Connect to negative terminal of the VTT LDO output capacitor.
CS_GND
-
17
–
Current sense comparator input (+) and ground for powergood circuit.
LL
18
20
I/O
MODE
6
4
I
–
7
–
–
12
–
PGND
16
18
–
Ground for rectifying (low-side) MOSFET gate driver (PWP, RGE). Also current sense
comparator input(+) and ground for powergood circuit (PWP).
PGOOD
13
13
O
Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the
target range.
S3
11
10
I
S3 signal input.
S5
12
11
I
S5 signal input.
V5IN
14
15
I
5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).
V5FILT
–
14
I
Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN to
V5FILT.
VBST
20
22
I/O
VDDQSET
10
9
I
VDDQSNS
9
8
I/O
VLDOIN
1
23
I
NC
Switching (high-side) MOSFET gate driver return. Current sense comparator input (-) for
RDS(on) current sense.
Discharge mode setting pin. See VDDQ and VTT Discharge Control section.
No connect.
Switching (high-side) MOSFET driver bootstrap voltage input.
VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge
current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for
VDDQ output if VDDQSET pin is connected to V5IN or GND.
Power supply for the VTT LDO.
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SLUS609J – MAY 2004 – REVISED JANUARY 2018
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Pin Functions (continued)
NO.
NAME
I/O
DESCRIPTION
PWP
RGE
VTT
2
24
O
Power output for the VTT LDO.
VTTGND
3
1
-
Power ground output for the VTT LDO.
VTTREF
7
5
O
VTTREF buffered reference output.
VTTSNS
4
2
I
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output
capacitor.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VIN
Input voltage range
VOUT
Output voltage range
MIN
MAX
VBST
–0.3
36
VBST wrt LL
–0.3
6
CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN,
VLDOIN, VDDQSET, V5FILT
–0.3
6
PGND, VTTGND, CS_GND
–0.3
0.3
DRVH
–1.0
36
LL
–1.0
30
COMP, DRVL, PGOOD, VTT, VTTREF
–0.3
6
TA
Operating ambient temperature range
–40
85
Tstg
Storage temperature
–55
150
(1)
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
4.75
5.25
V
VBST, DRVH
–0.1
34
LL
–0.6
28
VLDOIN, VTT, VTTSNS, VDDQSNS
–0.1
3.6
VTTREF
–0.1
1.8
PGND, VTTGND, CS_GND
–0.1
0.1
S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,
DRVL
–0.1
5.25
–40
85
Supply voltage, V5IN, V5FILT
Voltage range
Operating free-air temperature, TA
4
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V
°C
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7.4
SLUS609J – MAY 2004 – REVISED JANUARY 2018
Dissipation Ratings
PACKAGE
TA < 25°C POWER RATING
(W)
DERATING FACTOR ABOVE
TA = 25°C
(mW/°C)
TA = 85°C POWER RATING
(W)
20-pin PWP
2.53
25.3
1.01
24-pin RGE
2.20
22.0
0.88
7.5 Thermal Information
TPS51116
THERMAL METRIC
(1)
PWP
HTSSOP
RGE
QFN
20
24
UNIT
RθJA
Junction-to-ambient thermal resistance
41.2
35.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.4
41.1
°C/W
RθJB
Junction-to-board thermal resistance
23.9
12.9
°C/W
ψJT
Junction-to-top characterization parameter
1.1
07
°C/W
ψJB
Junction-to-board characterization parameter
23.7
12.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
3.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Electrical Characteristics
over operating free-air temperature range VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IV5IN1
Supply current 1, V5IN (1)
TA = 25°C, No load, VS3 = VS5 = 5 V,
COMP connected to capacitor
0.8
2
IV5IN2
Supply current 2, V5IN (1)
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
COMP connected to capacitor
300
600
IV5IN3
Supply current 3, V5IN (1)
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
VCOMP = 5 V
240
500
IV5INSDN
Shutdown current, V5IN (1)
TA = 25°C, No load, VS3 = VS5 = 0 V
0.1
1.0
IVLDOIN1
Supply current 1, VLDOIN
TA = 25°C, No load, VS3 = VS5 = 5 V
1
10
IVLDOIN2
Supply current 2, VLDOIN
TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V,
0.1
10
IVLDOINSDN
Standby current, VLDOIN
TA = 25°C, No load, VS3 = VS5 = 0 V
0.1
1.0
mA
μA
VTTREF OUTPUT
VVTTREF
VVTTREFTOL
Output voltage, VTTREF
Output voltage tolerance
VVDDQSNS/2
–20
20
–10 mA < IVTTREF < 10 mA,
VVDDQSNS = 1.8 V, Tolerance to VVDDQSNS/2
–18
18
–10 mA < IVTTREF < 10 mA,
VVDDQSNS = 1.5 V, Tolerance to VVDDQSNS/2
–15
15
–10 mA < IVTTREF < 10 mA,
VVDDQSNS = 1.2 V, Tolerance to VVDDQSNS/2
–12
12
–20
–40
–80
20
40
80
VVTTREFSRC
Source current
VVDDQSNS = 2.5 V, VVTTREF = 0 V
VVTTREFSNK
Sink current
VVDDQSNS = 2.5 V, VVTTREF = 2.5 V
(1)
V
–10 mA < IVTTREF < 10 mA,
VVDDQSNS = 2.5 V, Tolerance to VVDDQSNS/2
mV
mA
V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.
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TPS51116
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Electrical Characteristics (continued)
over operating free-air temperature range VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C, VVDDQSET = 0 V, No load
2.465
2.500
2.535
0°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load (2)
2.457
2.500
2.543
–40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No
load (2)
2.440
2.500
2.550
UNIT
VDDQ OUTPUT
VVDDQ
Output voltage, VDDQ
TA = 25°C, VVDDQSET = 5 V, No load
(2)
1.776
1.800
1.824
0°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load (2)
1.769
1.800
1.831
–40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No
load (2)
1.764
1.800
1.836
–40°C ≤ TA ≤ 85°C, Adjustable mode, No
load (2)
VVDDQSET
RVDDQSNS
VDDQSET regulation
voltage
Input impedance,
VDDQSNS
0.75
3.0
TA = 25°C, Adjustable mode
742.5
750.0
757.5
0°C ≤ TA ≤ 85°C, Adjustable mode
740.2
750.0
759.8
–40°C ≤ TA ≤ 85°C, Adjustable mode
738.0
750.0
762.0
VVDDQSET = 0 V
215
VVDDQSET = 5 V
180
Adjustable mode
460
VVDDQSET = 0.78 V, COMP = Open
–0.04
VVDDQSET = 0.78 V, COMP = 5 V
–0.06
IVDDQSET
Input current, VDDQSET
IVDDQDisch
Discharge current, VDDQ
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0 V
IVLDOINDisch
Discharge current, VLDOIN
10
V
mV
kΩ
μA
40
mA
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0.5 V
700
mA
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5
V
1.25
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8
V
0.9
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5
V
0.75
VTT OUTPUT
VVTTSNS
VVTTTOL25
VVTTTOL18
VVTTTOL15
(2)
6
Output voltage, VTT
VTT output voltage
tolerance to VTTREF
VTT output voltage
tolerance to VTTREF
VTT output voltage
tolerance to VTTREF
V
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5
V, IVTT = 0 A
–20
20
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5
V, |IVTT| < 1.5 A
–30
30
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5
V, |IVTT| < 3 A
–40
40
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5
V, IVTT = 0 A
–20
20
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5
V, |IVTT| < 1 A
–30
30
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5
V, |IVTT| < 2 A
–40
40
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5
V, IVTT = 0 A
–20
20
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5
V, |IVTT| < 1 A
–30
30
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5
V, |IVTT| < 2 A
–40
40
mV
mV
mV
Specified by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
VVTTTOL12
IVTTOCLSRC
VTT output voltage
tolerance to VTTREF
Source current limit, VTT
TEST CONDITIONS
MIN
TYP
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5
V, IVTT = 0 A
–20
20
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5
V, |IVTT| < 1 A
–30
30
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5
V, |IVTT| < 1.5 A
–40
40
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS
= 1.19 V, PGOOD = HI
3.0
3.8
6.0
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V
1.5
2.2
3.0
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS
= 1.31 V, PGOOD = HI
3.0
3.6
6.0
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ
1.5
2.2
3.0
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
–10
IVTTOCLSNK
Sink current limit, VTT
IVTTLK
Leakage current, VTT
IVTTBIAS
Input bias current, VTTSNS VS3 = 5 V, VVTTSNS = VVDDQSNS /2
–1
IVTTSNSLK
Leakage current, VTTSNS
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
–1
Discharge current, VTT
TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
VVTT = 0.5 V
10
17
240
300
IVTTDisch
MAX
UNIT
mV
A
10
–0.1
1
μA
1
mA
TRANSCONDUCTANCE AMPLIFIER
gm
Gain
TA = 25°C
ICOMPSNK
COMP maximum sink
current
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.7 V, VCOMP = 1.28 V
360
13
ICOMPSRC
COMP maximum source
current
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.3 V, VCOMP = 1.28 V
–13
VCOMPHI
COMP high clamp voltage
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.3 V, VCS = 0 V
1.31
1.34
1.37
VCOMPLO
COMP low clamp voltage
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.7 V, VCS = 0 V
1.18
1.21
1.24
tON
Operating on-time
VIN = 12 V, VVDDQSET = 0 V
520
tON0
Startup on-time
VIN = 12 V, VVDDQSNS = 0 V
125
tON(min)
Minimum on-time
TA = 25°C (2)
100
tOFF(min)
Minimum off-time
TA = 25°C (2)
350
μS
μA
V
DUTY CONTROL
ns
ZERO CURRENT COMPARATOR
VZC
Zero current comparator
offset
–6
0
6
mV
OUTPUT DRIVERS
RDRVH
RDRVL
tD
DRVH resistance
DRVL resistance
Dead time
Source, IDRVH = –100 mA
3
6
0.9
3
3
6
Sink, IDRVL = 100 mA
0.9
3
LL-low to DRVL-on (2)
10
DRVL-off to DRVH-on (2)
20
Sink, IDRVH = 100 mA
Source, IDRVL = –100 mA
Ω
ns
INTERNAL BST DIODE
VFBST
IVBSTLK
Forward voltage
VV5IN-VBST , IF = 10 mA, TA = 25°C
VBST leakage current
VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,
TA = 25°C
0.7
0.8
0.9
V
0.1
1.0
μA
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Electrical Characteristics (continued)
over operating free-air temperature range VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VPGND-CS , PGOOD = HI, VCS < 0.5 V
50
60
70
VPGND-CS , PGOOD = LO, VCS < 0.5 V
20
30
40
TA = 25°C, VCS > 4.5 V, PGOOD = HI
9
10
11
TA = 25°C, VCS > 4.5 V, PGOOD = LO
4
5
6
UNIT
PROTECTIONS
VOCL
Current limit threshold
ITRIP
Current sense sink current
TCITRIP
TRIP current temperature
coefficient
RDS(on) sense scheme, On the basis
of TA = 25°C (2)
VOCL(off)
Overcurrent protection
COMP offset
(VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,
VCS > 4.5 V (2)
VR(trip)
Current limit threshold
setting range
VV5IN-CS
(2) (1)
4500
–5
0
mV
μA
ppm/°C
5
mV
30
150
POWERGOOD COMPARATOR
PG in from lower
92.5%
95.0%
97.5%
PG in from higher
102.5%
105.0%
107.5%
VTVDDQPG
VDDQ powergood
threshold
IPG(max)
PGOOD sink current
VVTT = 0 V, VPGOOD = 0.5 V
2.5
7.5
tPG(del)
PGOOD delay time
Delay for PG in
80
130
200
Wake up
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
No discharge
4.7
PG hysteresis
5%
mA
μs
UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD
V5IN UVLO threshold
voltage
VUVV5IN
VTHMODE
MODE threshold
Non-tracking discharge
0.1
VTHVDDQSET
VDDQSET threshold
voltage
2.5 V output
0.08
0.15
0.25
1.8 V output
3.5
4.0
4.5
VIH
High-level input voltage
S3, S5
2.2
VIL
Low-level input voltage
S3, S5
VIHYST
Hysteresis voltage
S3, S5
VINLEAK
Logic input leakage current
S3, S5, MODE
–1
1
VINVDDQSET
Input leakage/ bias current
VDDQSET
–1
1
V
0.3
0.2
μA
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
VDDQ OVP trip threshold
voltage
tOVPDEL
VDDQ OVP propagation
delay (2)
VUVP
Output UVP trip threshold
tUVPDEL
Output UVP propagation
delay (2)
tUVPEN
Output UVP enable delay (2)
OVP detect
Hysteresis
110%
115%
120%
5%
1.5
UVP detect
70%
Hysteresis
10%
32
μs
cycle
1007
THERMAL SHUTDOWN
TSDN
8
Thermal SDN threshold
(2)
Shutdown temperature
Hysteresis
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160
10
°C
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7.7 Typical Characteristics
2
1
1.8
0.9
1.6
0.8
V5IN Shutdown Current (µA)
V5IN Supply Current (mA)
All data in the following graphs are measured from the PWP packaged device.
1.4
1.2
1
0.8
0.6
0.7
0.6
0.5
0.4
0.3
0.4
0.2
0.2
0.1
0
-40
-25
-10
5
20 35 50 65 80
Junction Temperature (°C)
95
0
-40
110 125
Figure 1. V5IN Supply Current vs Junction Temperature
0.9
8
0.8
DDR2
VLDOIN Supply Current (µA)
9
V5IN Supply Current (mA)
1
7
6
5
4
3
1.5
2
110 125
D001
0.4
0.3
0.1
1
95
0.5
1
-0.5
0
0.5
VTT Current (A)
20 35 50 65 80
Junction Temperature (°C)
0.6
0.2
-1
5
0.7
2
-1.5
-10
Figure 2. V5IN Shutdown Current vs Junction Temperature
10
0
-2
-25
D001
0
-40
-25
D001
-10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
D001
VVTT = 0.3 V
Figure 3. V5IN Supply Current vs VTT Current
Figure 4. VLDOIN Supply Current vs Junction Temperature
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Typical Characteristics (continued)
All data in the following graphs are measured from the PWP packaged device.
16
14
PGOOD = HI
ITRIP − CS Current − µA
12
10
8
6
PGOOD = LO
4
IDISCH − VDDQ Discharge Current − mA
80
2
0
−50
0
50
100
70
60
50
40
30
20
10
−50
150
TJ − Junction Temperature − °C
0
50
100
TJ − Junction Temperature − °C
150
Figure 6. VDDQ Discharge Current vs Junction Temperature
Figure 5. CS Current vs Junction Temperature
140
30
VOVP
Voltage Protection Trip Thresholds (V)
IDISCH − VTT Discharge Current − mA
VUVP
25
20
15
10
−50
0
50
100
TJ − Junction Temperature − °C
150
Figure 7. VTT Discharge Current vs Junction Temperature
10
120
100
80
60
±50
0
50
100
Junction Temperature (°C)
150
Figure 8. Overvoltage and Undervoltage Threshold vs
Junction Temperature
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Typical Characteristics (continued)
All data in the following graphs are measured from the PWP packaged device.
450
430
DDR2
DDR
420
400
Switching Frequency (kHz)
Switching Frequency (kHz)
350
410
400
390
300
250
200
150
100
380
50
0
370
4
8
12
16
20
24
0
28
Input Voltage (V)
IVDDQ = 7 A
DCAP Mode
1.815
1.815
1.810
1.810
VDDQ Output Voltage (V)
1.820
1.805
1.800
1.795
1.795
1.785
1.785
DDR
DCAP Mode
4
6
8
VDDQ Output Current (A)
VIN = 12 V
10
1.800
1.790
2
8
1.805
1.790
0
4
6
VDDQ Output Current (A)
VIN =12 V
Figure 10. Switching Frequency vs IVDDQ Output Current
1.820
1.780
2
DCAP Mode
Figure 9. Switching Frequency vs Input Voltage
VDDQ Output Voltage (V)
DDR2
DDR
10
1.780
4
DDR2
Figure 11. VDDQ Load Regulation
IVDDQ = 0 A
IVDDQ = 10 A
8
12
16
20
24
Input Voltage (V)
DCAP Mode
Figure 12. VDDQ Line Regulation
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Typical Characteristics (continued)
All data in the following graphs are measured from the PWP packaged device.
1.30
0.94
1.29
0.93
1.28
0.92
VTT Output Voltage (V)
VTT Output Voltage (V)
1.27
1.26
1.25
1.24
1.23
0.91
0.90
0.89
0.88
1.22
VVLDOIN = 1.8 V
1.21
VVLDOIN = 1.8 V
VVLDOIN = 1.5 V
VVLDOIN = 1.2 V
0.87
VVLDOIN = 2.5 V
1.20
±5
±4
±3
±2
±1
0
1
2
3
4
0.86
±3
5
±2
±1
0
1
2
3
VTT Output Current (A)
VTT Output Current (A)
DDR
DDR2
Figure 13. VTT Load Regulation
Figure 14. VTT Load Regulation
0.79
0.65
0.64
0.78
0.63
VTT Output Voltage (V)
VTT Output Voltage (V)
0.77
0.76
0.75
0.74
0.62
0.61
0.6
0.59
0.58
0.73
0.57
0.72
0.71
-3
DDR3
0.56
-2
-1
0
1
VTT Output Current (A)
2
0.55
-3
D001
VVLDOIN = 1. 5 V
-2
-1
0
1
VTT Output Current (A)
2
3
D001
DDR4
Figure 15. VTT Load Regulation
12
3
Figure 16. VTTREF Output Voltage vs Output Current
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Typical Characteristics (continued)
1.252
0.904
1.251
0.903
1.25
0.902
VTTREF Voltage (V)
VTTREF Voltage (V)
All data in the following graphs are measured from the PWP packaged device.
1.249
1.248
1.247
0.901
0.9
0.899
1.246
0.898
1.245
0.897
1.244
-10
-8
-6
DDR
-4
-2
0
2
4
VTTREF Current (mA)
6
8
0.896
-10
10
D021
-4
-2
0
2
4
VTTREF Current (mA)
6
8
10
D001
Figure 18. VTTREF Load Regulation
0.754
0.604
0.753
0.603
0.752
0.602
VTTREF Output Voltage (V)
VTTREF Output Voltage (V)
-6
DDR2
Figure 17. VTTREF Load Regulation
0.751
0.75
0.749
0.748
0.601
0.6
0.599
0.598
0.747
0.597
0.746
0.745
-12 -10
-8
D001
-8
-6 -4 -2
0
2
4
6
VTTREF Output Current (mA)
8
10
12
0.596
-12
D001
DDR3
-9
-6
-3
0
3
6
VTTREF Output Current (mA)
9
12
D001
DDR4
Figure 19. VTTREF Load Regulation
Figure 20. VTTREF Load Regulation
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Typical Characteristics (continued)
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
All data in the following graphs are measured from the PWP packaged device.
70
60
70
60
Input Voltage
20 V
12 V
8V
50
Input Voltage
20 V
12 V
8V
50
0
1
2
3
DDR
fSW = 400 kHz
4
5
6
7
VDDQ Current (A)
8
9
10
0
1
D001
VVDDQ = 2.5 V
DDR2
fSW = 400 kHz
Figure 21. VDDQ Efficiency vs VDDQ Current
2
3
4
5
6
7
VDDQ Current (A)
8
9
10
D001
VVDDQ = 1.8 V
Figure 22. VDDQ Efficiency vs VDDQ Current
VVDDQ (50 mV/div)
VVDDQ (50 mV/div)
IVDDQ (2 A/div)
IIND (5 A/div)
VVTTREF (10 mV/div)
VVTT (10 mV/div)
IVDDQ (5 A/div)
t − Time − 2 µs/div
t − Time − 20 µs/div
Heavy Load
Figure 23. Ripple Waveforms
14
Figure 24. VDDQ Load Transient Response
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Typical Characteristics (continued)
All data in the following graphs are measured from the PWP packaged device.
VVDDQ (50 mV/div)
VVTT (20 mV/div)
S5
VDDQ
VVTTREF
(20 mV/div)
VTTREF
IVTT
(2 A/div)
PGOOD
IVDDQ = IVTTREF = 0 A
t − Time − 100 µs/div
t − Time − 20 µs/div
Figure 25. VTT Load Transient Response
Figure 26. VDDQ, VTT, and VTTREF Start-Up Waveforms
VDDQ
VDDQ
VTTREF
VTTREF
VTT
VTT
S5
S5
IVDDQ = IVTT = IVTTREF = 0 A
IVDDQ = IVTT = IVTTREF = 0 A
t − Time − 200 µs/div
t − Time − 1 ms/div
Figure 27. Soft-Start Waveforms Tracking Discharge
Figure 28. Soft-Stop Waveforms Non-Tracking Discharge
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Typical Characteristics (continued)
All data in the following graphs are measured from the PWP packaged device.
180
80
135
60
40
90
40
90
20
45
20
45
0
0
0
0
80
60
180
Phase
135
−45
−20
Gain
−40
−90
−60
−135
IVDDQ = 7 A
1k
10 k
100 k
Gain
−20
−40
−90
−60
−135
−80
10 k
IVTT = −1 A
1M
100 k
Phase − 5
−180
10 M
1M
f − Frequency − Hz
f − Frequency − Hz
DDR2
Current mode
Source
Figure 30. VTT Bode Plot
Figure 29. VDDQ Bode Plot
80
180
60
135
40
Phase
20
Gain − dB
−45
90
45
0
Gain
0
−20
−45
−40
−90
Phase − °
−80
100
−180
Phase − 5
Gain − dB
Gain − dB
Phase
−135
−60
IVTT = 1 A
−80
10 k
100 k
1M
−180
10 M
f − Frequency − Hz
DDR2
Sink
Figure 31. VTT Bode Plot
16
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8 Detailed Description
8.1 Overview
8.2 Functional Block Diagram
Figure 32. PWP Package
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Functional Block Diagram (continued)
Figure 33. RGE Package
18
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8.3 Feature Description
The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a
10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin
HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that
required with DDR/DDR2/DDR3/DDR3L/LPDDR3/DDR4 memory systems. The switch mode power supply
(SMPS)
portion
employs
external
N-channel
MOSFETs
to
support
high
current
for
DDR/DDR2/DDR3/LPDDR3/DDR4 memory VDD/VDDQ. The preset output voltage is selectable from 2.5 V or
1.8 V. User-defined output voltage is also possible and can be adjustable from 0.75 V to 3 V. Input voltage range
of the SMPS is 3 V to 28 V. The SMPS runs an adaptive on-time PWM operation at high-load condition and
automatically reduces frequency to keep excellent efficiency down to several mA. Current sensing scheme uses
either RDS(on) of the external rectifying MOSFET for a low-cost, loss-less solution, or an optional sense resistor
placed in series to the rectifying MOSFET for more accurate current limit. The output of the switcher is sensed by
VDDQSNS pin to generate one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT active
termination supply. The VTT LDO can source and sink up to 3-A peak current with only 20-μF (two 10-μF in
parallel) ceramic output capacitors. VTTREF tracks VDDQ/2 within ±1% of VDDQ. VTT output tracks VTTREF
within ±20 mV at no load condition while ±40 mV at full load. The LDO input can be separated from VDDQ and
optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing
phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2).
The device offers two output discharge function alternatives when both VTT and VDDQ are disabled. The
tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT
output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using
internal discharge MOSFETs which are connected to VDDQSNS and VTT. The current capability of these
discharge FETs are limited and discharge occurs more slowly than the tracking discharge. These discharge
functions can be disabled by selecting non-discharge mode.
8.3.1 VDDQ SMPS, Light Load Condition
TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This
reduction of frequency is achieved smoothly and without increase of VOUTripple or load regulation. Detail
operation is described as follows. As the output current decreases from heavy load condition, the inductor current
is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary
between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when
this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous
conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next
ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current
increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor
current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the
threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1:
(V IN * V OUT) V OUT
1
I OUT(LL) +
2 L f
V IN
where
•
f is the PWM switching frequency (400 kHz)
(1)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at
IOUT(LL)/10 and 4 kHz at IOUT(LL)/100.
8.3.2 Low-Side Driver
The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is
represented by the internal resistance, which is 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A deadtime to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well
as the high-side gate drive current times 5 V makes the driving power which needs to be dissipated from the
device package.
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Feature Description (continued)
8.3.3 High-Side Driver
The high-side driver is designed to drive high-current, low on-resistance, N-channel MOSFET(s). When
configured as a floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also
calculated by the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied
by the flying capacitor between VBST and LL pins. The drive capability is represented by the internal resistance,
which is 3 Ω for VBST to DRVH and 0.9 Ω for DRVH to LL.
8.3.4 Current Sensing Scheme
In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor
sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor
should be connected between the source terminal of the low-side MOSFET and PGND. CS pin is connected to
the MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS
pin. For RDS(on) sensing scheme, CS pin should be connected to V5IN (PWP), or V5FILT (RGE) through the trip
voltage setting resistor, RTRIP. In this scheme, CS terminal sinks 10-μA ITRIP current and the trip level is set to the
voltage across the RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that
LL pin should be connected to the drain terminal of the low-side MOSFET. ITRIP has 4500ppm/°C temperature
slope to compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive
current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense
resistor or the source terminal of the low-side MOSFET.
8.3.5 PWM Frequency and Adaptive On-Time Control
TPS51116 includes an adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output
voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and
proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time.
Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during
the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In
order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output
becomes 750 mV or larger.
8.3.6 VDDQ Output Voltage Selection
TPS51116 can be used for both of DDR (VVDDQ = 2.5 V) and DDR2 (VVDDQ = 1.8 V) power supply and adjustable
output voltage (0.75 V < VVDDQ < 3 V) by connecting VDDQSET pin as shown in Table 1. Use the adjustable
output voltage scheme for a DDR3 (VVDDQ= 1.5 V) or LPDDR3/DDR4 (VVDDQ= 1.2 V) application.
Table 1. VDDQSET and Output Voltages
(1)
(2)
VDDQSET
VDDQ (V)
VTTREF and VTT
GND
2.5
VVDDQSNS/2
NOTE
DDR
V5IN
1.8
VVDDQSNS/2
DDR2
FB Resistors
Adjustable
VVDDQSNS/2
0.75 V < VVDDQ < 3 V (1) (2)
VVDDQ ≥ 1.2 V when used as VLDOIN
Including DDR3, LPDDR3 and DDR4
8.3.7 VTT Linear Regulator and VTTREF
The TPS51116 device integrates high performance low-dropout linear regulator that is capable of sourcing and
sinking current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small
ceramic capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load
transient. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal,
VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin.
For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. It is
recommended to attach two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR
20
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of the output capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to
achieve loop stability. The RC filter time constant should be almost the same or slightly lower than the time
constant made by the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and
buffer. This regulator also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-μF
ceramic capacitor for stable operation.
When VTT is not required in the design, following treatment is strongly recommended.
• Connect VLDOIN to VDDQSNS.
• Tie VTTSNS to VTT, and remove capacitors from VTT to float.
• Connect VTTGND and MODE to GND (Non-tracking discharge mode as shown in Table 3)
• Maintain a 0.033-µF capacitor connected at VTTREF.
• Pull down S3 to GND with 1 kΩ of resistance.
A typical circuit for this application is shown in Figure 34
VIN
TPS51116 PWP
1
VLDOIN
VBST 20
2
VTT
DRVH 19
3
VTTGND
LL 18
4
VTTSNS
DRVL 17
5
GND
PGND 16
6
MODE
7
VTTREF
8
COMP
9
VDDQSNS
VDDQ
0.033 ?F
CS 15
V5IN 14
5VIN
PGOOD 13
S5 12
1 kW
10 VDDQSET
S3 11
PGOOD
S5
UDG-12044
Figure 34. Application Circuit When VTT Is Not Required
8.3.8 Controling Outputs Using the S3 and S5 Pins
In the DDR, DDR2, DDR3, LPDDR3 or DDR4 memory applications, it is important to maintain the VDDQ voltage
level higher than VTT (or VTTREF) voltage including both start-up and shutdown. The TPS51116 device
provides this management by simply connecting both the S3 and S5 pins to the sleep-mode signals such as
SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ, VTTREF and VTT are turned on at S0 state (S3
= S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and VTTREF voltages are kept on while VTT is turned off
and left at high impedance (high-Z) state. The VTT output is floated and does not sink or source current in this
state. In S4/S5 states (S3 = S5 = low), all of the three outputs are disabled. Outputs are discharged to ground
according to the discharge mode selected by MODE pin (see VDDQ and VTT Discharge Control section). Each
state code represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 =
soft OFF. (See Table 2)
Table 2. Sleep Mode Control Using the S3 and S5 Pins
STATE
S3
S5
VDDQ
VTTREF
VTT
S0
HI
HI
ON
ON
ON
S3
LO
HI
ON
ON
OFF (High-Z)
S4/S5
LO
LO
OFF (Discharge)
Off (Discharge)
OFF (Discharge)
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8.3.9 Soft-Start Function and Powergood Status
The soft-start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At
the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold
is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,
the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 μs. The
overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another
45 μs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the
target voltage), then turns off powergood open-drain MOSFET.
The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed
in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood
threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low
and constant current that gives linear ramp up of the output. When the output comes up to the good state, the
overcurrent limit level is released to normal value (3.8 A). The device has an independent counter for each
output, but the PGOOD signal indicates the status of VDDQ only and does not indicate VTT powergood status
externally. See Figure 35.
100%
87%
80%
VVDDQ
VOCL
VPGOOD
VS5
85 µs
45 µs
UDG−04066
Figure 35. VDDQ Soft-Start and Powergood Timing
Soft-start duration, tVDDQSS, tVTTSS are functions of output capacitances.
2 ´ CVDDQ ´ VVDDQ ´ 0.8
+ 85 ms
t VDDQSS =
IVDDQOCP
where
•
IVDDQOCP is the current limit value for VDDQ switcher calculated by Equation 5
(2)
C
´ VVTT
t VTTSS = VTT
IVTTOCL
where
•
IVTTOCL = 2.2 A (typ)
(3)
In both Equation 2 and Equation 3 , no load current during start-up are assumed. Note that both switchers and
the LDO do not start up with full load condition.
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8.3.10 VDDQ and VTT Discharge Control
The TPS51116 device discharges VDDQ, VTTREF and VTT outputs when S3 and S5 are both low. There are
two different discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.
Table 3. Discharge Selection
MODE
DISCHARGE MODE
V5IN
No discharge
VDDQ
Tracking discharge
GND
Non-tracking discharge
When in tracking-discharge mode, the device discharges outputs through the internal VTT regulator transistors
and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via
VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can
handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off
and the operation mode is changed to the non-tracking-discharge mode.
When in non-tracking-discharge mode, teh device discharges outputs using internal MOSFETs which are
connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.
Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In no discharge mode, the
device does not discharge any output charge.
8.3.11 Current Protection for VDDQ
The SMPS has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. The
trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme
section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV.
For RDS(on) sensing scheme, CS terminal sinks 10 μA and the trip level is set to the voltage across this RTRIP
resistor.
V TRIP (mV) + RTRIP (kW) 10 (mA)
(4)
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load
current at overcurrent threshold, IOCP, can be calculated as shown in Equation 5.
I OCP +
V TRIP
I
V
) RIPPLE + TRIP )
2
RDS(on)
R DS(on) 2
1
L
ǒV IN * V OUTǓ
f
V OUT
V IN
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes less than Powergood level, the VTRIP is cut into half and
the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and
shutdown.
8.3.12 Current Protection for VTT
The LDO has an internally fixed constant overcurrent limiting of 3.8 A while operating at normal condition. This
trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of
±10% of the target voltage.
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8.3.13 Overvoltage and Undervoltage Protection for VDDQ
TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is
connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If
an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.
When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes
high and the circuit latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
The device monitors the VDDQSNS pin voltage directly and if it becomes greater than 4 V, it turns off the highside MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP
comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116
latches OFF both top and low-side MOSFETs. This function is enabled after 1007 cycles of SMPS operation to
ensure startup.
8.3.14 Undervoltage Lockout (UVLO) Protection, V5IN (PWP), V5FILT (RGE)
The device has 5-V supply undervoltage lockout protection (UVLO). When the V5IN (PWP) voltage or V5FILT
(RGE) voltage is lower than UVLO threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a nonlatch protection.
8.3.15
Input Capacitor, V5IN (PWP), V5FILT (RGE)
Add a ceramic capacitor with a value between 1.0 μF and 4.7 μF placed close to the V5IN (PWP) pin or V5FILT
(RGE) pin to stabilize 5 V from any parasitic impedance from the supply.
8.3.16 Thermal Shutdown
TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160°C (typ),
SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the
device is cooled down by about 10°C.
8.4 Device Functional Modes
8.4.1 VDDQ SMPS, Dual PWM Operation Modes
The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.
It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode
uses internal compensation circuit and is suitable for low external component count configuration with an
appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external
compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as
ceramic or specialty polymer capacitors.
These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,
TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is
monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the
output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to
VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This
MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined
by VIN and VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time
control (see PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when
feedback information indicates insufficient output voltage and inductor current information indicates below the
overcurrent limit. Repeating operation in this manner, the controller regulates the output voltage. The
synchronous low-side or the rectifying MOSFET is turned on each OFF state to keep the conduction loss
minimum. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables
seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over
broad range of load current.
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Device Functional Modes (continued)
In the current mode control scheme, the transconductance amplifier generates a target current level
corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During
the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and
when the inductor current signal comes lower than the target current level, the comparator provides SET signal
to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support
various types of output MOSFETs and capacitors. In D-CAP mode, the transconductance amplifier is disabled
and the PWM comparator compares the feedback point voltage and the internal 750-mV reference during the
OFF state. When the feedback point comes lower than the reference voltage, the comparator provides SET
signal to initiate the next ON state.
8.4.2 Current Mode Operation
A buck converter using current mode operation can be partitioned into three portions, a voltage divider, an error
amplifier and a switching modulator. By linearizing the switching modulator, we can derive the transfer function of
the whole system. Because current mode scheme directly controls the inductor current, the modulator can be
linearized as shown in Figure 36.
Figure 36. Linearizing the Modulator
In this example, the inductor is located inside the local feedback loop and its inductance does not appear in the
small signal model. As a result, a modulated current source including the power inductor can be modeled as a
current source with its transconductance of 1/RS and the output capacitor represent the modulator portion. This
simplified model is applicable in the frequency space up to approximately a half of the switching frequency. One
note is, although the inductance has no influence to small signal model, it has influence to the large signal model
as it limits slew rate of the current source. This means the buck converter’s load transient response, one of the
large signal behaviors, can be improved by using smaller inductance without affecting the loop stability.
Equation 6 describes the total open loop transfer function of the entire system.
H(s) + H 1(s) H 2(s) H 3(s)
(6)
Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of the three blocks is shown starting with
Equation 7.
R2
H 1(s) +
(R2 ) R1)
(7)
H 2(s) + * gm
R O ǒ1 ) s
ǒ1 ) s
CC
CC
R OǓ ǒ1 ) s
RCǓ
C C2
R CǓ
(8)
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Device Functional Modes (continued)
H 3(s) +
(1 ) s
CO
ǒ1 ) s
CO
ESR)
RLǓ
RL
RS
(9)
There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.
1
w P1 +
ǒCC ROǓ
w P2 +
w P3 +
w Z1 +
w Z2 +
(10)
1
ǒCO
RLǓ
(11)
1
ǒCC2
RCǓ
(12)
1
ǒCC
RCǓ
(13)
ESRǓ
(14)
1
ǒCO
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be
kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. Equation 15calculates the 0
dB frequency, f0.
gm RC
gm R C
0.75
R1
f0 + 1
+ 1
2p R1 ) R2 C O RS
2p VOUT C O R S
(15)
8.4.3 D-CAP™ Mode Operation
Figure 37 shows a simplified schematic of a buck converter application operating in D-CAP™ mode.
Figure 37. Linearizing the Modulator
The PWM comparator compares the VDDQSNS voltage divided by R1 and R2 with internal reference voltage,
and determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is high
enough to maintain the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant.
The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input
voltage increase.
f0, must be lower than 1/3 of the switching frequency.Equation 16 defines the 0-dB frequency calculation.
f
1
f0 +
v SW
3
2p ESR CO
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Device Functional Modes (continued)
Because the 0-dB frequency, f0 is determined solely by the output capacitor characteristics, loop stability of DCAP™ mode is determined by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP)
have CO in the order of several 100 μF and ESR in range of 10 mΩ. These makes f0 on the order of 100 kHz or
less and the loop is then stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable
for this operational mode.
Although D-CAP™ mode design provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient
amount of feedback signal needs to be provided by external circuit to reduce jitter level.
The required signal level is approximately 15 mV at comparing point. This gives VRIPPLE = (VOUT/0.75) x 15 (mV)
at the output node. The output capacitor’s ESR should meet this requirement.
The external components selection is simple for applications that operate in D-CAP™ mode.
1. Choose inductor. Inductor selection for DCAP mode operation is the same as for current mode operation.
Please refer to the instructions in the Current Mode Operation section.
2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are
recommended. Determine ESR to meet required ripple voltage above. Equation 17 shows an approximation
calculation.
V
0.015
ESR + OUT
[ VOUT
60 [mW]
I RIPPLE 0.75
I OUT(max)
(17)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 DDR3 Application With Current Mode
Figure 38. DDR3 Current Mode Application Schematic
9.2.1 Design Requirements
Table 4. Design Requirements
PARAMETER
VIN
Input voltage
VV5IN
V5IN voltage
VVDDQ
VDDQ output voltage
IVDDQ
VDDQ output current
VVTT
VTT output voltage
IVTT
VTT output current
28
TEST CONDITIONS
MIN
TYP
MAX
4.5
12
28
5
DDR3
V
10
0.75
DDR3, VVTT = 0.75 V
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V
V
1.5
0
UNIT
A
V
3
A
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9.2.2 Detailed Design Procedure
9.2.2.1 Pin Connections
In current mode configuration, the COMP pin is connect to ground via compensation network. The VDDQSET pin
is connect to a resistor divider to set VDDQ voltage at 1.5 V. In this design, the RDS(on) of low side switch is used
for current sense, therefore the CS pin connected to V5IN via a resistor. The MODE pin is connected to VDDQ to
select tracking discharge mode.
9.2.2.2 Choose the inductor
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current.
L+
ǒVIN(max) * VOUTǓ
1
I IND(ripple)
f
VOUT
VIN(max)
+
ǒV IN(max) * V OUTǓ
2
I OUT(max)
f
V OUT
V IN(max)
(18)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as shown in Equation 19.
I IND(peak) +
V TRIP
) 1
RDS(on) L f
ǒVIN(max) * VOUTǓ
V OUT
VIN(max)
(19)
9.2.2.3 Choose rectifying (low-side) MOSFET
When RDS(on) sensing scheme is selected, the rectifying MOSFET’s on-resistance is used as this RS so that
lower RDS(on) does not always promise better performance. In order to clearly detect inductor current, minimum
RS recommended is to give 15 mV or larger ripple voltage with the inductor ripple current. This promises smooth
transition from CCM to DCM or vice versa. Upper side of the RDS(on) is of course restricted by the efficiency
requirement, and usually this resistance affects efficiency more at high-load conditions. When using external
resistor current sensing, there is no restriction for low RDS(on). However, the current sensing resistance RS itself
affects the efficiency
9.2.2.4 Choose output capacitance
When organic semiconductor capacitors (OS-CON) or specialty polymer capacitors (SP-CAP) are used, ESR to
achieve required ripple value at stable state or transient load conditions determines the amount of capacitor(s)
need, and capacitance is then enough to satisfy stable operation. The peak-to-peak ripple value can be
estimated by ESR times the inductor ripple current for stable state, or ESR times the load current step for a fast
transient load response. When ceramic capacitor(s) are used, the ESR is usually small enough to meet ripple
requirement. In contrast, transient undershoot and overshoot driven by output capacitance becomes the key
factor in determining the capacitor(s) required.
9.2.2.5 Determine f0 and calculate RC
Use Equation 20 to and calculate RC. A higher RC value shows faster transient response in cost of unstableness.
If the transient response is not enough even with high RC value, try increasing the out put capacitance. The
recommended f0 value is fOSC/4.
V OUT CO
R C v 2p f 0
gm RS
0.75
(20)
R C + 2.8
V OUT
C O [mF]
R S [mW]
(21)
9.2.2.6 Calculate CC2
This capacitance acts to cancel zero caused by ESR of the output capacitor. When ceramic capacitors are used,
there is no need for capacitor CC2.
1
1
w z2 +
+ wp3 +
ǒCO ESRǓ
ǒC C2 RCǓ
(22)
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CC2 =
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CO ´ ESR
RC
(23)
9.2.2.7 Calculate CC.
The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it causes phase delay,
another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined by CC and RC.
Recommended ωz1 is 10 times lower to the f0 frequency.
f
1
f z1 +
+ 0
10
2p C C R C
(24)
9.2.2.8 Determine the value of R1 and R2.
These two resistor values are required when using adjustable mode,
V
* 0.75
R1 + OUT
R2
0.75
(25)
9.2.3 Application Curves
DDR3
VIN = 12 V
Current Mode
IOUT = 10 A
DDR3
VIN = 12 V
Figure 39. Statup Waveforms
30
Current Mode
IOUT = 1 A
Figure 40. Shutdown Waveforms
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94
Efficiency (%)
92
90
88
86
84
82
0
DDR3
VIN = 12 V
Current Mode
IOUT = 1 A
1
2
DDR3
fSWN = 400 kHz
Figure 41. Output Ripple
3
4
5
6
Ouptut Current (A)
7
8
9
10
D001
Current Mode
Figure 42. Efficiency vs Output Current
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9.3 DDR3 Application With D−CAP™ Mode
Figure 43. DDR3 DCAP Mode Application Schematic
9.3.1 Design Requirements
Table 5. Design Requirements
PARAMETER
VIN
Input voltage
VV5IN
V5IN voltage
VVDDQ
VDDQ output voltage
IVDDQ
VDDQ output current
VVTT
VTT output voltage
IVTT
VTT output current
TEST CONDITIONS
MIN
TYP
MAX
4.5
12
28
5
DDR3
V
10
0.75
DDR3, VVTT = 0.75 V
–3
V
V
1.5
0
UNIT
A
V
3
A
9.3.2 Detailed Design Procedure
The general design procedure is the same as that for the current mode design example described in Detailed
Design Procedure.
9.3.2.1 Pin Connections
In D−CAP™ mode configuration, the COMP pin is connect to V5IN. The VDDQSET pin is connect to a resistor
divider to set VDDQ voltage at 1.5 V. In this design, the RDS(on) of low side switch is used for current sense,
therefore the CS pin connected to V5IN via a resistor. The MODE pin is connected to VDDQ to select tracking
discharge mode.
9.3.2.2 Choose the Components
Refer to the instructions in the current mode design example to choose inductor, MOSFETs. Organic
semiconductor capacitor or polymer capacitor are recommended for D−CAP™ mode design. The output ripple
should be larger than (VOUT/0.75) x 15 (mV). In this design, two pieces of 150 μF PSCAP capacitors with 45 mΩ
ESR are selected.
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9.3.3 Application Curves
DDR3
VIN = 12 V
DCAP Mode
IOUT = 10 A
DDR3
VIN = 12 V
Figure 44. Startup Waveforms
DCAP Mode
IOUT = 1 A
Figure 45. Shutdown Waveforms
DDR3
VIN = 12 V
DCAP Mode
IOUT = 10 A
Figure 46. VDDQ Output Ripple
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply between 3 V and 28 V. There are input voltage
and switch node voltage limitations from the MOSFET. A separate 5-V power supply is required for the internal
circuits and MOSFET gate drivers of the device.
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11 Layout
11.1 Layout Guidelines
Consider these guidelines before designing a layout using the TPS51116 device.
• PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET
and high-voltage side of the inductor, should be as short and wide as possible.
• Consider adding a small snubber circuit, consisting of a 3-Ω resitor and a 1-nF capacitor, between LL and
PGND in case a high-frequency surge is observed on the LL voltage waveform.
• All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage
switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.
• VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for
VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide
connection.
• The output capacitor for VTT should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to
sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitor(s).
• Consider adding LPF at VTTSNS when the ESR of the VTT output capacitor(s) is larger than 2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of VTTREF. Avoid any noise generative lines.
• Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding
common impedance to the high current path of the VTT source/sink current.
• GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND
to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid
additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.
• Connect CS_GND (RGE) to source of rectifying MOSFET using Kevin connection. Avoid common trace for
high-current paths such as the MOSFET to the output capacitors or the PGND to the MOSFET trace. When
using an external current sense resistor, apply the same care and connect it to the positive side (ground side)
of the resistor.
• PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25 mil) or wider trace. Connect to
source of rectifying MOSFET with shortest possible path.
• Place a V5FILT filter capacitor (RGE) close to the device, within 12 mm (0.5 inches) if possible.
• The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH,
DRVL or PGOOD.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.
Include numerous vias with a 0.33-mm diameter connected from the thermal land to the internal and solderside ground plane(s) to enhance heat dissipation.
34
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TPS51116
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11.2 Layout Example
Figure 47. Layout
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Product Folder Links: TPS51116
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TPS51116
SLUS609J – MAY 2004 – REVISED JANUARY 2018
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
D-CAP, PowerPAD, E2E are trademarks of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
36
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TPS51116
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SLUS609J – MAY 2004 – REVISED JANUARY 2018
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS51116
37
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51116PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS51116
TPS51116PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS51116
TPS51116PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS51116
TPS51116PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS51116
TPS51116RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51116
TPS51116RGERG4
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51116
TPS51116RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51116
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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