TPS54519
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SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
2.95 V to 6 V Input, 5-A Synchronous Step Down SWIFT™ Converter
FEATURES
DESCRIPTION
•
The TPS54519 device is a full featured 6 V, 5 A,
synchronous step down current mode converter with
two integrated MOSFETs.
1
2
•
•
•
•
•
•
•
Two 30 mΩ (typical) MOSFETs for high
efficiency at 5-A loads
200kHz to 2MHz Switching Frequency
0.6 V Voltage Reference With ± 1% Initial
Accuracy
Adjustable Slow Start / Sequencing
UV and OV Power Good Output
Low Operating and Shutdown Quiescent
Current
Safe Start-up into Pre-Biased Output
Cycle by Cycle Current Limit, Thermal and
Frequency Fold Back Protection
–40°C to 140°C Operating Junction
Temperature Range
Thermally Enhanced 3mm × 3mm 16-pin QFN
The TPS54519 enables small designs by integrating
the MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2 MHz switching frequency,
and minimizing the IC footprint with a small 3mm x
3mm thermally enhanced QFN package.
Efficiency is maximized through the integrated 30mΩ
MOSFETs and 350μA typical supply current. Using
the enable pin, shutdown supply current is reduced to
2 μA by entering a shutdown mode.
APPLICATIONS
Under voltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the slow start
pin. An open drain power good signal indicates the
output is within 93% to 107% of its nominal voltage.
•
•
Frequency fold back and thermal shutdown protects
the device during an overcurrent condition.
•
•
•
Low-Voltage, High-Density Power Systems
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
The TPS54519 is supported in the SwitcherPro™
Software Tool at www.ti.com/switcherpro.
For more SWIFT™ documentation, see the TI
website at www.ti.com/swift.
100
VIN
CBOOT
VIN
VIN = 5 V
BOOT
90
R4
TPS54519
EN
LO
VOUT
PH
CO
R5
R1
PWRGD
VSENSE
SS/TR
RT
COMP
GND
AGND
POWERPAD
C ss
Efficiency - %
CI
80
VIN = 3 V
70
60
VOUT = 1.2 V
FSW = 1MHz
R2
50
0
RT
R3
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IL - Load Current - A
C1
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, SwitcherPro are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TPS54519
SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TJ
PACKAGE
PART NUMBER
–40°C to 140°C
3 × 3 mm QFN
TPS54519RTE
ABSOLUTE MAXIMUM RATINGS
VALUE
Input voltage
MAX
VIN
–0.3
7
EN
–0.3
7
BOOT
Output voltage
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
7
SS/TR
–0.3
3
RT
–0.3
6
BOOT-PH
8
–0.6
PH 10 ns Transient
Sink current
V
PH + 8
PH
Source current
UNIT
MIN
V
7
–2
7
μA
EN
100
RT
100
COMP
100
μA
PWRGD
10
mA
SS/TR
100
μA
2
kV
Electrostatic discharge (HBM)
Electrostatic discharge (CDM)
500
V
Operating Junction temperature, Tj
–40
140
°C
Storage temperature, Tstg
–65
150
°C
THERMAL INFORMATION
THERMAL METRIC (1) (2)
TPS54519
RTE (16 PINS)
θJA
Junction-to-ambient thermal resistance (standard board)
49.1
θJA
Junction-to-ambient thermal resistance (custom board) (3)
37.0
ψJT
Junction-to-top characterization parameter
0.7
ψJB
Junction-to-board characterization parameter
21.8
θJC(top)
Junction-to-case(top) thermal resistance
50.7
θJC(bot)
Junction-to-case(bottom) thermal resistance
7.5
θJB
Junction-to-board thermal resistance
21.8
(1)
(2)
(3)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 140°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in the application section of this data sheet for more
information.
Test boards conditions:
(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
2.4
2.8
V
1
5
μA
455
500
μA
1.25
1.37
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
2.95
Internal under voltage lockout threshold
No voltage hysteresis, rising and falling
Shutdown supply current
EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V
Quiescent Current - Iq
VSENSE = 0.9 V, 25°C, RT = 400 kΩ
6
V
ENABLE AND UVLO (EN PIN)
Enable threshold
Input current
Rising
1.16
Falling
1.18
Enable threshold + 50 mV
-3.6
Enable threshold – 50 mV
-0.7
μA
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference
0 A ≤ IOUT ≤ 5 A, 25°C
0.594
0.600
0.606
BOOT-PH= 5 V
30
60
BOOT-PH= 2.95 V
35
70
VIN= 5 V
30
60
VIN= 2.95 V
35
70
V
MOSFET
High side switch resistance
Low side switch resistance
mΩ
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
250
μmhos
Error amplifier transconductance (gm) during
slow start
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
Vsense = 0.4 V
85
μmhos
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to Iswitch gm
±20
μA
19.0
A/V
CURRENT LIMIT
Current limit threshold
6.0
Low-side reverse current limit
7.0
8.0
A
–2.7
A
155
°C
7.5
°C
THERMAL SHUTDOWN
Thermal Shutdown
150
Hysteresis
TIMING RESISTOR (RT PIN)
Switching frequency range using RT mode
Switching frequency
200
Rt = 84 kΩ
400
490
2000
kHz
600
kHz
PH (PH PIN)
Minimum On time
Measured at 50% points on PH, VIN = 5 V, IOUT =
500 mA
100
ns
Minimum Off time
Prior to skipping off pulses, BOOT-PH = 2.95 V,
IOUT = 4 A
60
ns
Rise/Fall Time
VIN = 5 V
1.5
V/ns
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
BOOT (BOOT PIN)
Ω
BOOT Charge Resistance
VIN = 5 V
15
BOOT-PH UVLO
VIN = 2.95 V
2.1
Charge Current
V(SS) = 0.3 V
2.4
SS/TR to VSENSE matching
VSSTR = 0.3 V
73
SS to reference crossover
98% nominal
SS discharge voltage (overload)
VSENSE = 0 V
80
μA
SS discharge current (UVLO, EN, Thermal
Fault)
VIN = 5 V, V(SS) = 0.5 V
1.2
mA
VSENSE rising (Good)
93
% Vref
VSENSE rising (Fault)
110
% Vref
2
% Vref
2.75
V
115
mV
SLOW START / TRACKING (SS/TR PIN)
μA
0.87
V
POWER GOOD (PWRGD PIN)
VSENSE threshold
Hysteresis
VSENSE falling
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V
On resistance
100
nA
Ω
78
Output low
I(PWRGD) = 3.5 mA
0.5
V
Minimum VIN for valid output
V(PWRGD) < 0.5 V at 100 μA
0.8
V
4
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DEVICE INFORMATION
PIN CONFIGURATION
VIN
1
VIN
2
VIN
EN
PWRGD
BOOT
QFN16
RTE Package
(Top View)
16
15
14
13
12
PH
11
PH
PowerPAD
(17)
PH
GND
4
9
SS/TR
6
7
8
RT
5
COMP
10
VSENSE
3
AGND
GND
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
AGND
5
Analog Ground should be electrically connected to GND close to the device.
13
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum
required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
7
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
15
Enable pin, internal pull-up current source. Pull below 1.18 V to disable. Float to enable. Can be used to set the
on/off threshold (adjust UVLO) with two additional resistors.
3, 4
Power Ground. This pin should be electrically connected directly to the power pad under the IC.
BOOT
COMP
EN
GND
PH
Thermal
Pad
PWRGD
RT
SS/TR
VIN
VSENSE
10, 11, 12
The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier
MOSFET.
17
GND pin should be connected to the exposed power pad for proper operation. This thermal pad should be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
14
An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent, over/undervoltage or EN shut down.
8
Resistor Timing.
9
Slow-start. An external capacitor connected to this pin sets the output voltage rise time. This pin can also be
used for tracking.
1, 2, 16
6
Input supply voltage, 2.95 V to 6 V.
Inverting node of the transconductance (gm) error amplifier.
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FUNCTIONAL BLOCK DIAGRAM
PWRGD
EN
VIN
i1
Shutdown
93%
ihys
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
107%
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
COMP Clamp
ERROR
AMPLIFIER
PWM
Comparator
VSENSE
SS/TR
Current
Sense
BOOT
Logic and PWM
Latch
Shutdown
Logic
S
COMP
Slope
Compensation
PH
Frequency
Shift
Overload
Recovery
Maximum
Clamp
AGND
6
Oscillator
THERMALPAD
GND
RT
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SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS CURVES
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
VIN SUPPLY CURRENT vs TEMPERATURE
3
490
VI = 5 V
470
ICC - Supply Current - mA
Iq - Shutdown Supply Current - mA
480
2.5
2
VI = 3.3 V
1.5
VI = 5 V
1
460
450
440
VI = 3.3 V
430
420
0.5
410
0
-40
-10
20
50
80
110
400
-40
140
-10
20
50
80
110
140
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 1.
Figure 2.
EN PIN VOLTAGE vs TEMPERATURE
EN PIN CURRENT vs TEMPERATURE
0
1.28
1.27
-0.5
1.26
-1
EN - Pin Current - mA
EN - Threshold - V
1.25
1.24
EN Rising, VI = 3.3 V
EN Rising, VI = 5 V
EN Falling, VI = 3.3 V
EN Falling, VI = 5 V
1.23
1.22
1.21
1.20
-1.5
EN Pin Current @ VI = 3.3 V, VEN = Threshold + 50 mV
EN Pin Current @ VI = 5 V, VEN = Threshold + 50 mV
EN Pin Current @ VI = 3.3 V, VEN = Threshold - 50 mV
EN Pin Current @ VI = 5 V, VEN = Threshold - 50 mV
-2
-2.5
-3
1.19
1.18
-3.5
1.17
1.16
-40
-10
20
50
80
110
-4
-40
140
-10
Figure 4.
0.603
0.602
0.601
0.600
0.599
VI = 3.3 V, CMP = 1 V
VI = 5 V, CMP = 1 V
VI = 3.3 V, CMP = 0.7 V
VI = 5 V, CMP = 0.7 V
VI = 3.3 V, CMP = 1.3 V
VI = 5 V, CMP = 1.3 V
0.597
0.596
0.595
20
50
80
110
140
RDSON - Static Drain-Source On-State Resistance - W
0.604
0.598
110
140
Rdson vs TEMPERATURE
0.605
Vref - Voltage Reference - V
80
Figure 3.
VOLTAGE REFERENCE vs TEMPERATURE
-10
50
TJ - Junction Temperature - °C
0.606
0.594
-40
20
TJ - Junction Temperature - °C
50
45
40
35
30
25
High Side Rdson @ VI = 3.3 V
High Side Rdson @ VI = 5 V
20
Low Side Rdson @ VI = 3.3 V
Low Side Rdson @ VI = 5 V
15
-40
TJ - Junction Temperature - °C
-10
20
50
80
110
140
TJ - Junction Temperature - °C
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS CURVES (continued)
SWITCHING FREQUENCY vs TEMPERATURE
SWITCHING FREQUENCY vs RT RESISTANCE
500
2000
RT = 84 kW,
VI = 5 V
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
1700
495
490
485
480
1400
1100
800
500
475
-40
200
-10
20
50
80
110
140
0
50
100
TJ - Junction Temperature - °C
Figure 7.
200
250
Figure 8.
SWITCHING FREQUENCY vs VSENSE
SS CHARGE CURRENT vs TEMPERATURE
-2
100
-2.1
VSENSE FALLING
75
ISS - SS Charge Current - mA
Normal Switching Frequency - %
150
RT- Resistance - kW
VSENSE RISING
50
25
-2.2
VI = 5 V; VSS = 0.3 V
-2.3
-2.4
VI = 3.3 V; VSS = 0.3 V
-2.5
-2.6
-2.7
0
0
0.1
0.2
0.3
0.4
0.5
-2.8
-40
0.6
20
50
80
110
TJ - Junction Temperature - °C
Figure 9.
Figure 10.
TRANSCONDUCTANCE vs TEMPERATURE
TRANSCONDUCTANCE (SLOW START) vs
TEMPERATURE
310
140
105
100
VI = 3.3 V
290
VI = 3.3 V
VI = 5 V
VI = 5 V
95
EA - Transconductance - mA/V
EA - Transconductance - mA/V
-10
VSENSE - V
270
250
230
210
90
85
80
75
70
65
190
60
170
-40
8
-10
20
50
80
110
140
55
-40
-10
20
50
80
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 11.
Figure 12.
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110
140
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TYPICAL CHARACTERISTICS CURVES (continued)
HIGH-SIDE FET CURRENT LIMIT vs
TEMPERATURE
PWRGD Rdson vs TEMPERATURE
130
120
110
7.5
Rdson - Power Good - W
HSFET lim - High Side Fet Current Limit Current - A
8
VI = 5 V
7
VI = 3.3 V
6.5
100
VI = 5 V
90
80
70
60
50
40
30
6
-40
-10
20
50
80
110
20
-40
140
-10
20
50
80
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 13.
Figure 14.
110
140
PWRGD THRESHOLD vs TEMPERATURE
112
110
PWRGD Threshold - % Vref
108
106
Vsense (Good) Falling
Vsense (Fault) Rising
104
102
100
98
Vsense (Good) Falling
96
Vsense (Fault) Rising
94
92
90
88
-40
-10
20
50
80
110
140
TJ - Junction Temperature - °C
Figure 15.
OVERVIEW
The TPS54519 is a 6-V, 5-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs.
To improve performance during line and load transients the device implements a constant frequency, peak
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT pin.
The TPS54519 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source
that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition,
the pull up current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS54519 is 455 μA when not switching and under no load. When the device is
disabled, the supply current is less than 5 μA.
The integrated 30 mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents
up to 5 amperes.
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The TPS54519 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor
voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a
preset threshold. This BOOT circuit allows the TPS54519 to operate approaching 100%. The output voltage can
be stepped down to as low as the 0.6 V reference.
The TPS54519 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54519 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power
good comparator. When the regulated output voltage is greater than 107% of the nominal voltage, the
overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until
the output voltage is lower than 105%.
The SS/TR pin is used to minimize inrush currents or provide power supply sequencing during power up. A small
value capacitor should be coupled to the pin for slow start. The SS/TR pin is discharged before the output power
up to ensure a repeatable restart after an over-temperature fault, UVLO fault or disabled condition.
The use of a frequency foldback circuit reduces the switching frequency during startup and over current fault
conditions to help limit the inductor current.
10
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DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54519 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved
transient response performance.
SLOPE COMPENSATION AND OUTPUT CURRENT
The TPS54519 adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full
duty cycle range.
BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION
The TPS54519 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
To improve drop out, the TPS54519 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.1 V, typically. The high side MOSFET is turned off using an UVLO circuit, allowing for
the low side MOSFET to conduct when the voltage from BOOT to PH drops below 2.1 V. Since the supply
current sourced from the BOOT pin is very low, the high side MOSFET can remain on for more switching cycles
than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.
ERROR AMPLIFIER
The TPS54519 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower
of the SS/TR pin voltage or the internal 0.6 V voltage reference. The transconductance of the error amplifier is
250 μA/V during normal operation. When the voltage of VSENSE pin is below 0.6 V and the device is regulating
using the SS/TR voltage, the gm is 85 μA/V. The frequency compensation components are placed between the
COMP pin and ground.
VOLTAGE REFERENCE
The voltage reference system produces 0.6 V Voltage Reference at the non-inverting input of the error amplifier.
ADJUSTING THE OUTPUT VOLTAGE
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a 100 kΩ for the R1 resistor and use the Equation 1
to calculate R2. To improve efficiency at very light loads consider using larger value resistors. If the values are
too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are
noticeable.
æ
ö
0.6 V
R2 = R1 ´ ç
÷
è VO - 0.6 V ø
(1)
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TPS54519
VO
R1
VSENSE
R2
0.6 V
+
Figure 16. Voltage Divider Circuit
ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT
The TPS54519 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 17 to adjust the input voltage UVLO by using two
external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (VSTOP) above
2.7 V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply
variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54519
operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis is
added. When the EN pin is pulled below 1.18 V, the 2.9 μA is removed. This additional current facilitates input
voltage hysteresis.
TPS54519
i hys
VIN
2.9 mA
i1
R1
0.7 mA
R2
EN
+
-
Figure 17. Adjustable Under Voltage Lock Out
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
V
è ENRISING ø
R1 =
æ
ö
V
IP ç 1 - ENFALLING ÷ + Ih
VENRISING ø
è
R2 =
VSTOP
(2)
R1´ VENFALLING
- VENFALLING + R1(IP + Ih )
(3)
spacer
where:
Ih = 2.9 µA
IP = 0.7 µA
VENRISING = 1.25 V
VENFALLING = 1.18 V
12
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SLOW START / TRACKING PIN
The TPS54519 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the
SS/TR pin to ground implements a slow start time. The TPS54519 has an internal pull-up current source of
2.4μA which charges the external slow start capacitor. Equation 4 calculates the required slow start capacitor
value where Tss is the desired slow start time in ms, Iss is the internal slow start charging current of 2.4 μA, and
Vref is the internal voltage reference of 0.6 V.
Tss(mS) ´ Iss(mA)
Css(nF) =
Vref(V)
(4)
If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.18 V, or a thermal shutdown
event occurs, the TPS54519 stops switching and the SS/TR is discharged to 0 volts before reinitiating a
powering up sequence.
SEQUENCING
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin
of another device. Figure 18 shows the sequential method. The power good is coupled to the EN pin on the
TPS54519 which enables the second power supply once the primary supply reaches regulation.
Ratio-metric start up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp
up and reach regulation at the same time. When calculating the slow start time the pull up current source must
be doubled in Equation 4. The ratio metric method is illustrated in Figure 20.
TPS54519
TPS54519
PWRGD1
EN1
EN2
EN1
SS/TR1
SS/TR2
PWRGD1
EN2
PWRGD2
Vo u t 1
Vo u t 2
Figure 18. Sequential Start-Up Sequence
Figure 19. Sequential Startup using EN and
PWRGD
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TPS54519
EN1
EN1/2
SS/TR1
PWRGD1
SS1
Vo u t 1
Vo u t 2
TPS54519
EN2
SS/TR2
PWRGD2
Figure 20. Schematic for Ratio-metric Startup
Sequence
Figure 21. Ratio-metric Startup with Vout1 Leading
Vout2
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 22 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and
Vout2. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR
to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start
up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a
negative number in Equation 5 through Equation 7 for ΔV. Equation 7 will result in a positive number for
applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Since the SS/TR pin
must be pulled below 40mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the
tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from
Equation 5 is greater than the value calculated in Equation 8 to ensure the device can recover from a fault. As
the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as
the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage needs to be greater than 0.87 V for a complete handoff to the internal voltage reference as shown in
Figure 21.
vertical spacer
R1 =
Vout2 + D V
Vssoffset
´
Vref
Iss
(5)
Vref ´ R1
Vout2 + DV - Vref
(6)
spacer
R2 =
spacer
DV = Vout1 - Vout2
(7)
spacer
R1 > 2930 ´ Vout1- 145 ´ DV
(8)
spacer
14
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TPS54519
EN1
VOUT1
EN1
SS/TR1
PWRGD1
SS2
Vout1
TPS54519
EN2
Vout2
VOUT 2
R1
SS/TR2
R2
PWRGD2
Figure 22. Schematic for Ratio-metric Start-Up
Sequence
Figure 23. Ratio-metric Start-Up using Coupled
SS/TR Pins
CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT Pin)
The switching frequency of the TPS54519 is adjustable over a wide range from 200 kHz to 2000 kHz by placing
a maximum of 218 kΩ and minimum of 16.9 kΩ, respectively, on the RT pin. An internal amplifier holds this pin
at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT is typically
0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 8 and
Figure 9, or Equation 9.
spacer
RT (kW) = 84145 ´ FSW (kHz)-1.121
(9)
spacer
Fsw(kHz) = 24517 ´ RT(kW)-0.89
(10)
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 60 ns at full current load and 100 ns at no load, and limits the
maximum operating input voltage or output voltage.
OVERCURRENT PROTECTION
The TPS54519 implements a cycle by cycle current limit. During each switching cycle the high side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
FREQUENCY SHIFT
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54519
implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low
side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current
runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%,
then 50%, then 25% as the voltage decreases from 0.6 to 0 volts on VSENSE pin to allow the low side MOSFET
to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases
as the voltage on VSENSE increases from 0 to 0.6 volts. See Figure 7 for details.
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REVERSE OVERCURRENT PROTECTION
The TPS54519 implements low side current protection by detecting the voltage across the low side MOSFET.
When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if
the reverse current is more than 2.7 A. By implementing this additional protection scheme, the converter is able
to protect itself from excessive current during power cycling and start-up into pre-biased outputs.
POWER GOOD (PWRGD PIN)
The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is
recommended to use a pull-up resistor between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or
less. The PWRGD is in a valid state once the VIN input voltage is greater than 0.8 V, typically.
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54519 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109%
of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next
clock cycle.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 155°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 155°C, the device reinitiates the power up sequence
by discharging the SS/TR pin to 0 volts. The thermal shutdown hysteresis is 7.5°C.
SMALL SIGNAL MODEL FOR LOOP RESPONSE
Figure 24 shows an equivalent model for the TPS54519 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gm of 250 μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The
1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency
response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting
a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis.
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PH
VO
Power Stage
19 A/V
a
b
R1
c
R3
C2
RESR
RL
COMP
0.6 V
CO RO
VSENSE
gm
250 µA/V
C1
COUT
R2
Figure 24. Small Signal Model for Loop Response
SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 24 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54519 power stage can be approximated to a voltage controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 11 and consists of a dc gain, one dominant pole and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 24) is the power stage
transconductance. The gm for the TPS54519 is 19 A/V. The low frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 12. As the load
current increases and decreases, the low frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 13].
The combined effect is highlighted by the dashed line in the right half of Figure 25. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for the varying load conditions which makes it easier to design the frequency compensation.
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 25. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
ç 1+
vo
è 2p
= Adc ´
vc
æ
ç 1+
è 2p
ö
s
÷
× ¦z ø
ö
s
÷
× ¦p ø
(11)
Adc = gmps ´ RL
(12)
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¦p =
¦z =
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1
C OUT ´ R L ´ 2 p
COUT
(13)
1
´ RESR ´ 2p
(14)
SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION
The TPS54519 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 26. The Type 2
circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high frequency pole is added to attenuate high frequency noise.
VO
R1
VSENSE
COMP
gmea
R2
Vref
RO
CO
5pF
Type 2A
R3
C2
Type 2B
R3
C1
C1
Figure 26. Types of Frequency Compensation
The design guidelines for TPS54519 loop compensation are as follows:
1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 15 and Equation 16.
Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 17
and Equation 18 to estimate a starting point for the crossover frequency, fc. Equation 17 is the geometric
mean of the modulator pole and the esr zero and Equation 18 is the mean of modulator pole and the
switching frequency. Use the lower value of Equation 17 or Equation 18 as the maximum crossover
frequency.
Iout m ax
2 p ´ Vout ´ Cout
(15)
1
¦ z m od =
2 p ´ Resr ´ Cout
(16)
¦C =
¦p mod ´ ¦ z mod
(17)
¦C =
¦p mod ´
¦ p m od =
¦ sw
2
(18)
2. R3 can be determined by
2p × ¦ c ´ Vo ´ COUT
R3 =
gmea ´ Vref ´ gmps
(19)
Where is the gmea amplifier gain (250 μA/V), gmps is the power stage gain (19 A/V).
¦p =
1
C OUT ´ R L ´ 2 p . C1 can be determined by
3. Place a compensation zero at the dominant pole
R ´ COUT
C1 = L
R3
4. C2 is optional. It can be used to cancel the zero from Co’s ESR.
Resr ´ COUT
C2 =
R3
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APPLICATION INFORMATION
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
This design is available as the PWR037-002 evaluation module (EVM). A few parameters must be known in
order to start the design process. These parameters are typically determined on the system level. For this
example, we start with the following known parameters:
Output Voltage
1.8 V
Transient Response 1.25 to 3.75 A load step
ΔVout = 4%
Maximum Output Current
5A
Input Voltage
3V-6V
Output Voltage Ripple
< 30 mV p-p
Start Input Voltage (rising VIN)
2.9 V
Stop Input Voltage (falling VIN)
2.66 V
Switching Frequency (Fsw)
1000 kHz
SELECTING THE SWITCHING FREQUENCY
The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest
switching frequency possible since this produces the smallest solution size. The high switching frequency allows
for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter’s
performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an
ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a
high efficiency operation. Using Equation 9, R4 is calculated to be 35.4 kΩ. A standard 1% 35.7 kΩ value was
chosen in the design.
L1
1.2 uH
U1
TPS54519
VIN= 3-6V
16 VIN
1 VIN
VIN
C1
C2
R1
10uF
0.1uF
14.3k
2 VIN
15 EN
6 VSNS
VSNS
C3
R2
220pF
11.5k
C4
1
PH
11
PH
12
BOOT
13
GND
1
3
VOUT= 1.8V, 5A
2
VOUT
C7
R5
R4
35.7k
C6
C9
47uF
47uF
R6
C10
20k
220pF
VIN
VSNS
100k
R7
10.0k
PWRPD
C5
C8
0.1uF
GND 4
AGND 5
9 SS/TR
23.7k
1000pF
10
PWRGD 14
7 COMP
8 RT/CLK
R3
PH
17
1 Optional
0.01uF
Figure 27. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO
OUTPUT INDUCTOR SELECTION
The inductor selected works for the entire TPS54519 input voltage range. To calculate the value of the output
inductor, use Equation 22. KIND is a coefficient that represents the amount of inductor ripple current relative to the
maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a
ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 0.84 μH. For this
design, a larger standard value was chosen: 1.2 μH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 24 and Equation 25.
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For this design, the RMS inductor current is 5.009 A and the peak inductor current is 5.525 A. The chosen
inductor is a Coilcraft XAL5030-122ME. It has a saturation current rating of 11.8 A (20% inductance loss) and an
RMS current rating of 8.7 A ( 20 ºC temperature rise). The series resistance is 6,78 mΩ typical.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Vout
´
L1 =
Io ´ Kind
Vinmax ´ ¦ sw
(22)
Iripple =
ILrms =
Vinmax - Vout
Vout
´
L1
Vinmax ´ ¦ sw
Io 2 +
æ Vo ´ (Vinmax - Vo) ö
1
´ ç
÷
12
è Vinmax ´ L1 ´ ¦ sw ø
(23)
2
(24)
Iripple
ILpeak = Iout +
2
(25)
OUTPUT CAPACITOR
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing
a tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessary
to accomplish this.
For this example, the transient load response is specified as a 4% change in Vout for a load step from 1.25 A
(25% load) to 3.75 A (75%). For this example, ΔIout = 3.75 - 1.25 = 2.5 A and ΔVout= 0.04 × 1.8 = 0.072 V.
Using these numbers gives a minimum capacitance of 69.4 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
Equation 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement,
Equation 27 yields 4.38uF.
2 ´ DIout
Co >
¦ sw ´ DVout
(26)
Co >
1
´
8 ´ ¦ sw
1
Voripple
Iripple
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage.
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Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 28 indicates the ESR should be less than 28.6 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 28.6 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 47 μF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 29 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 29 yields
303 mA.
Voripple
Resr <
Iripple
(28)
Icorm s =
Vout ´ (Vinm ax - Vout)
12 ´ Vinm ax ´ L1 ´ ¦ sw
(29)
INPUT CAPACITOR
The TPS54519 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54519.
The input ripple current can be calculated using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 31. Using the design example values, Ioutmax=4 A, Cin=10 μF, Fsw=1
MHz, yields an input voltage ripple of 124 mV and a rms input ripple current of 2.45 A.
Icirms = Iout ´
Vout
´
Vinmin
(Vinmin
- Vout )
Vinmin
(30)
Ioutmax ´ 0.25
DVin =
Cin ´ ¦ sw
(31)
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54519 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start capacitor value can be calculated using Equation 4. For the example circuit, the slow start time is
not too critical since the output capacitor value is 2 x 47μF which does not require much current to charge to 1.8
V. The example circuit has the slow start time set to an arbitrary value of 2.5 ms which requires a 10 nF
capacitor. In TPS54519, Iss is 2.4 μA and Vref is 0.6 V.
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BOOTSTRAP CAPACITOR SELECTION
A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
UNDER VOLTAGE LOCK OUT SET POINT
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54519. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 2.794 V (VSTART). After the regulator starts switching, it should
continue to do so until the input voltage falls below 2.595 V (VSTOP).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 and Equation 3 can be used to calculate the resistance values necessary. From Equation 2 and
Equation 3, a 14.3 kΩ between Vin and EN and a 11.5 kΩ between EN and ground are required to produce the
2.794 and 2.595 volt start and stop voltages.
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 100 kΩ was selected for R6. Using Equation 32, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.5 kΩ.
Vref
R7 =
R6
Vo - Vref
(32)
Due to the internal design of the TPS54519, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 33
(
(
(
)))- (Ioutmin ´ (RL + RDS ))
Voutmin = Ontimemin ´ Fsmax ´ Vinmax - Ioutmin ´ (2 ´ RDS )
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum contollable on-time (60 ns typical. 110 nsec no load)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS = minimum high side MOSFET on resistance (30 - 44 mΩ)
RL = series resistance of output inductor
(33)
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 34
22
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)(
(
))
(
Voutmax = 1 - (Offtimemax ´ Fsmax ) ´ Vinmin - Ioutmax ´ (2 ´ RDS ) - Ioutmax ´ (RL + RDS )
Where:
Voutmax = maximum achievable output voltage
Offtimeman = maximum off time (60 nsec typical)
Fsmax = maximum switching frequency including tolerance
Vinmin = minimum input voltage
Ioutmax = maximum load current
RDS = maximum high side MOSFET on resistance (60 - 70 mΩ)
RL = series resistance of output inductor
(34)
COMPENSATION
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 35
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(35)
For the TPS54519 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a
reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model of (insert link here). Apply the values calculated previously to the output filter components of L1, C8
and C9. Set Rload to the appropriate value. For this design, L1 = 1.2 µH. C8 and C9 use the derated
capacitance value of 43 µF, and the ESR is set to 3 mohm. The Rload resistor is 1.8 / 5 = 21.6 mΩ. Now the
power stage characteristic can be plotted as shown in Figure 28
G 60
a
i
n
180d P
h
a
s
e
120d
40
20
60d
-9.79 db @ 70 kHz
0
0d
-20
-60d
-40
-120d
Gain - dB
Phase - Degrees
-60
100Hz
1.0KHz
10KHz
Frequency
100KHz
-180d
1.0MHz
Figure 28. Power Stage Gain and Phase Characteristics
For this design, the intended crossover frequency is 70 kHz. From the power stage gain and phase plots, the
gain at 70 kHz is -9.79 dB and the phase is -131.87 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 36.
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R3 =
10
-GPWRSTG
20
gmEA
×
Vout
VREF
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(36)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 70 kHz.
The required value for C5 is given by Equation 37.
1
C5 =
F
2 × p × R3 × CO
10
(37)
To maximize phase gain the high frequency pole is not implemented and C4 is not populated. The pole can be
useful to offset the ESR of aluminum electrolytic output capacitors. If desired the value for C4 can be calculated
from Equation 38.
1
C4 =
2 × p × R3 × FP
(38)
For maximum phase boost, the pole frequency FP will typically be one decade above the intended crossover
frequency FCO.
The feed forward capacitor C10, is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair located at Equation 39 and
Equation 40.
1
FZ =
2 × p × C10 × R6
(39)
1
FP =
2 × p × C10 × R6 P R7
(40)
This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well. For
optimum performance, the zero and pole should be located symmetrically about the intended crossover
frequency. The required value for C10 can calculated from Equation 41.
1
C10 =
VREF
2 × p × R6 × FCO ×
VOUT
(41)
For this design the calculated values for the compensation components are R3 = 23.8 kΩ ,C5 = 959 pF and C10
= 197 pF. Using standard values, the compensation components are R3 = 23.7 kΩ ,C5 = 1000 pF and C10 =
220 pF.
APPLICATION CURVES
24
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EFFICIENCY
vs
LOAD CURRENT
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
EFFICIENCY
vs
LOAD CURRENT
60
50
40
30
50
40
30
20
20
VIN = 3.3 V
VIN = 5 V
10
0
60
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
4
4.5
5
0
0.001
G001
Figure 29.
0.01
0.1
Output Current (A)
1
G002
Figure 30.
TRANSIENT RESPONSE, 2 A STEP
VOUT = 50 mV/div (ac coupled)
VIN = 3.3 V
VIN = 5 V
10
POWER UP VOUT, VIN
VIN = 5 V/div
EN = 2 V/div
IOUT = 2 A/div
PWRGD = 5 V/div
Slew rate = 0.5 A/µs
VOUT = 1 V/div
Time = 2 ms/div
Time = 200 µs/div
Figure 31.
Figure 32.
POWER DOWN VOUT, VIN
VIN = 5 V/div
POWER UP VOUT, EN
VIN = 5 V/div
EN = 2 V/div
EN = 2 V/div
PWRGD = 5 V/div
PWRGD = 5 V/div
VOUT = 1 V/div
VOUT = 1 V/div
Time = 2 ms/div
Time = 2 ms/div
Figure 33.
Figure 34.
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POWER DOWN VOUT, EN
OUTPUT RIPPLE, 5 A
VOUT = 20 mV/div (ac coupled)
VIN = 5 V/div
EN = 2 V/div
PH = 2 V/div
PWRGD = 5 V/div
VOUT = 1 V/div
Time = 100 µs/div
Time = 500 ns/div
Figure 35.
Figure 36.
INPUT RIPPLE, 5 A
CLOSED LOOP RESPONSE, VIN (3.3 V), 4 A
PH = 2 V/div
180
150
120
90
60
30
0
−30
−60
−90
−120
−150
−180
1000000
Gain
Phase
1000
10000
Frequency (Hz)
100000
Phase (°)
Gain (dB)
VIN = 100 mV/div (ac coupled)
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
100
G005
Time = 500 ns/div
Figure 37.
Figure 38.
LOAD REGULATION
vs
LOAD CURRENT
REGULATION
vs
INPUT VOLTAGE
1
0.4
Output Voltage Deviation (%)
Output Voltage Deviation (%)
VIN = 3.3 V
VIN = 5 V
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
0.3
0.2
0.1
0
−0.1
−0.2
−0.8
−0.3
−1
−0.4
IOUT = 2.5 A
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
4
4.5
5
3
G003
Figure 39.
26
3.5
4
4.5
5
Input Voltage (V)
5.5
6
G004
Figure 40.
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Maximum Temperature = 58 °C
48 °C
23 °C
IOUT = 5 A
Figure 41. Thermal Image
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).
Pcon = Io2 × Rdson_temp
Pd = ƒsw × Iout × 0.7 × 40 × 10-9
Psw = 0.5 × Vin × Io × ƒsw × 7 × 10-9
Pgd = 2 × Vin × 6 × 10-9 × ƒsw
Pq = 455 × 10-6 × Vin
Where:
IOUT is the output current (A).
Rdson is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
ƒsw is the switching frequency (Hz).
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJMAX = 140°C
TAmax = TJ max – Rth × Ptot
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
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LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 42 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the
top side ground area to the internal planes near the input and output capacitors. For operation at full rated load,
the top side ground area along with any additional internal ground planes must provide adequate heat dissipating
area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located very close to the
PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected
to a separate analog ground trace as shown. The RT pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
28
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VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
PH
GND
VOUT
OUTPUT
FILTER
CAPACITOR
PH
SLOW START
CAPACITOR
RT
COMP
VSENSE
AGND
SS/TR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 42. PCB Layout Example
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REVISION HISTORY
NOTE: Page numbers of current revision may differ from previous versions.
Changes from Original (September 2011) to Revision A
•
30
Page
Added Voltage Reference spec for Condition "0 A ≤ IOUT ≤ 5 A, 25°C " .............................................................................. 3
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PACKAGE OPTION ADDENDUM
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11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS54519RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
54519
Samples
TPS54519RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
54519
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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