TPS55340MRTETEP

TPS55340-EP SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 TPS55340-EP Integrated 5-A, 40-V Wide Input Range Boost/SEPIC/Flyback DC-DC Regulator 1 Features 3 Description • • • • • • • • • • • The TPS55340-EP is a monolithic, non-synchronous switching regulator with integrated 5-A, 40-V power switch. It can be configured in several standard switching-regulator topologies, including boost, SEPIC and isolated flyback. The device has a wide input voltage range to support applications with input voltage from multi-cell batteries or regulated 3.3-, 5-, 12-, and 24-V power rails. 2 Applications • • • • • The TPS55340-EP regulates the output voltage with current mode pulse width modulation (PWM) control, and has an internal oscillator. The switching frequency of PWM is set by either an external resistor or by synchronizing to an external clock signal. The user can program the switching frequency from 100 kHz to 1.2 MHz. The device features a programmable soft-start function to limit inrush current during start-up and has other built-in protection features including cycleby-cycle over current limit and thermal shutdown. Device Information ORDER NUMBER TPS55340MRTETEP 3.3-V, 5-V, 12-V, 24-V power conversion Boost, SEPIC, and flyback topologies Thunderbolt port, power docking for tablets and portable PCs Industrial power systems ADSL modems L VIN D (1) PACKAGE(1) WQFN (16) BODY SIZE (NOM) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. 100 VOUT 95 CI TPS55340 VIN SW EN SW RSH FREQ SS SW FB COMP PGND SYNC PGND AGND PGND CSS RFREQ RC CC Typical Application (Boost) 90 CO Efficiency (%) • Internal 5-A, 40-V low-side MOSFET switch 2.9-V to 32-V input voltage range ±0.7% reference voltage 0.5-mA operating quiescent current 2.7-µA shutdown supply current Fixed frequency current mode PWM vontrol Frequency adjustable from 100 kHz to 1.2 MHz Synchronization capability to external clock Adjustable soft-start time Pulse-skipping for higher efficiency at light loads Cycle-by-cycle current limit, thermal shutdown, and UVLO protection Supports defense, aerospace, and medical applications – Controlled baseline – One assembly and test site – One fabrication site – Available in military (–55°C to 125°C) temperature range – Extended product life cycle – Extended product-change notification – Product traceability 85 VOUT = 24 V fSW = 600 kHz 80 75 70 65 RSL VIN = 15 V VIN = 12 V VIN = 5 V 60 55 50 0 0.4 0.8 1.2 1.6 Output Current (A) 2 2.4 G031 Efficiency vs Output Current An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................3 7 Specifications.................................................................. 4 7.1 Absolute Maximum Ratings........................................ 4 7.2 Handling Ratings.........................................................4 7.3 Recommended Operating Conditions.........................4 7.4 Thermal Information....................................................4 7.5 Electrical Characteristics.............................................5 7.6 Typical Characteristics................................................ 6 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................12 9 Application and Implementation.................................. 13 9.1 Application Information............................................. 13 9.2 Typical Applications.................................................. 13 10 Power Supply Recommendations..............................27 11 Layout........................................................................... 28 11.1 Layout Guidelines................................................... 28 11.2 Layout Examples.....................................................28 12 Device and Documentation Support..........................30 12.1 Device Support....................................................... 30 12.2 Receiving Notification of Documentation Updates..30 12.3 Support Resources................................................. 30 12.4 Trademarks............................................................. 30 12.5 Electrostatic Discharge Caution..............................30 12.6 Glossary..................................................................30 13 Mechanical, Packaging, and Orderable Information.................................................................... 30 4 Revision History Changes from Revision * (July 2014) to Revision A (September 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document. ................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 5 Description (continued) The 5-A, 40-V TPS55340-EP boost converter is pin-to-pin compatible with the 3-A, 40-V TPS61175, and it extends the maximum input voltage from 18 to 32 V. SW 1 VIN 2 SW SW NC PGND 6 Pin Configuration and Functions 16 15 14 13 12 PGND 11 PGND NC PowerPAD SS 4 9 6 7 FREQ 8 FB 5 COMP 10 AGND 3 SYNC EN Figure 6-1. 16-Pin WQFN RTE Package (Top View) Table 6-1. Pin Functions PIN NAME DESCRIPTION NO. AGND 6 Signal ground of the IC COMP 7 Output of the transconductance error amplifier. An external RC network connected to this pin compensates the regulator feedback loop. EN 3 Enable pin. When the voltage of this pin falls below the enable threshold for more than 1 ms, the IC turns off. FB 8 Error amplifier input and feedback pin for positive voltage regulation. Connect to the center tap of a resistor divider to program the output voltage. FREQ 9 Switching frequency program pin. An external resistor connected between the FREQ pin and AGND sets the switching frequency. NC 10 14 Reserved pin that must be connected to ground 11 PGND 12 Power ground of the IC. It is connected to the source of the internal power MOSFET switch. 13 PowerPAD 17 The PowerPAD™ should be soldered to the AGND. If possible, use thermal vias to connect to internal ground plane for improved power dissipation. SS 4 Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start timing. 1 SW 15 SW is the drain of the internal power MOSFET. Connect SW to the switched side of the boost or SEPIC inductor or the flyback transformer. 16 SYNC 5 Switching frequency synchronization pin. An external clock signal can be used to set the switching frequency between 200 kHz and 1 MHz. If not used, this pin should be tied to AGND. VIN 2 The input supply pin to the IC. Connect VIN to a supply voltage between 2.9 and 32 V. It is acceptable for the voltage on the pin to be different from the boost power stage input. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP 3 TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating temperature (unless otherwise noted)(1) Supply voltages on pin VIN(2) Voltage on pin EN(2) Voltage on pins FB, FREQ, and COMP(2) Voltage on pin SS(2) Voltage on pin SYNC(2) Voltage on pin SW(2) Operating junction temperature (1) (2) MIN MAX –0.3 34 UNIT V –0.3 34 V –0.3 3 V –0.3 5 V –0.3 7 V –0.3 40 V –55 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin 7.2 Handling Ratings Tstg Storage temperature range pins(1) Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) V(ESD) (1) (2) MIN MAX UNIT –65 150 °C –2000 2000 –500 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN NOM MAX UNIT VIN Input voltage 2.9 32 V VOUT Output voltage VIN 38 V VEN EN voltage 0 32 V VSYN External switching frequency logic input 0 5 V TA Operating free-air temperature –55 125 °C TJ Operating junction temperature –55 150 °C 7.4 Thermal Information THERMAL METRIC(1) WQFN (16 PINS) Rθ JA Junction-to-ambient thermal resistance 43.3 Rθ JC(top) Junction-to-case (top) thermal resistance 38.7 Rθ JB Junction-to-board thermal resistance 14.5 ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 14.5 Rθ JC(bot) Junction-to-case (bottom) thermal resistance 3.5 (1) 4 TPS55340-EP UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 7.5 Electrical Characteristics Vin = 5 V, TJ = –55°C to 150°C, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage 2.9 32 IQ Operating quiescent current into Vin Device nonswitching, VFB = 2 V 0.5 ISD Shutdown current EN = GND 2.7 VUVLO Undervoltage lockout threshold VIN falling Vhys Undervoltage lockout hysteresis V mA 10 µA 2.5 2.7 V 120 140 160 mV 0.9 1.08 1.30 V ENABLE AND REFERENCE CONTROL VEN EN threshold voltage EN rising input VENh EN threshold hysteresis 0.1 0.16 0.22 V REN EN pulldown resistor 400 950 1600 kΩ Toff Shutdown delay, SS discharge VSYNh SYN logic high voltage VSYNl SYN logic low voltage EN high to low 1.0 ms 1.2 0.4 V 1.229 1.254 V 1.6 30 VOLTAGE AND CURRENT CONTROL VREF Voltage feedback regulation voltage 1.204 IFB Voltage feedback input bias current Isink Comp pin sink current VFB = VREF + 200 mV, VCOMP = 1 V Isource Comp pin source current VFB = VREF – 200 mV, VCOMP = 1 V VCCLP Comp pin clamp voltage High Clamp, VFB = 1 V Low Clamp, VFB = 1.5 V VCTH Comp pin threshold Duty cycle = 0% 1.04 V Gea Error amplifier transconductance Rea Error amplifier output resistance ƒea Error amplifier crossover frequency 240 nA 42 µA 42 µA 3.1 0.75 V 360 440 µmho 10 MΩ 500 kHz FREQUENCY ƒSW Frequency Dmax Maximum duty cycle VFREQ FREQ pin voltage Tmin_on Minimum on pulse width RFREQ = 480 kΩ 75 94 130 RFREQ = 80 kΩ 460 577 740 920 1140 1480 89% 96% RFREQ = 40 kΩ VFB = 1 V, RFREQ = 80 kΩ kHz 1.25 V RFREQ = 80 kΩ 77 ns 60 70 POWER SWITCH RDS(ON) N-channel MOSFET on-resistance VIN = 5 V VIN = 3 V ILN_NFET N-channel leakage current VDS = 25 V 110 120 mΩ 2.1 µA OCP and SS ILIM N-channel MOSFET current limit D = Dmax ISS Soft-start bias current Vss = 0 V 5.25 6.6 8.25 A 6 µA 165 °C 15 °C THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold Thysteresis Thermal shutdown threshold hysteresis Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP 5 TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 7.6 Typical Characteristics Vin = 5 V, TJ = 25°C (unless otherwise noted) 8 Current Limit Threshold (A) Transconductance (µA/V) 400 380 360 340 320 300 ±50 ±25 0 25 50 75 100 125 4 3 2 ±75 ±50 0 ±25 25 50 75 100 125 150 Temperature (ƒC) C001 Figure 7-1. Error Amplifier Transconductance vs Temperature C002 Figure 7-2. Switch Current Limit vs Temperature 1.230 120 100 1.228 Resistance (mŸ) Voltagle Reference (V) 5 150 Temperature (ƒC) 1.226 1.224 VIN = 3 V 80 60 VIN = 5 V 40 VIN = 12 V 1.222 20 0 1.220 ±75 ±50 ±25 0 25 50 75 100 125 150 Temperature (ƒC) ±75 0 ±25 25 50 75 1400 1200 Frequency (kHz) 1200 1000 800 600 400 500 C004 800 600 1 Rmessage FREQ = 40 kŸ 2 Rmessage FREQ = 80 kŸ Rmessage kŸ FREQ = 480 3 400 0 ±75 ±50 G005 Figure 7-5. Frequency vs FREQ Resistance 150 1000 200 200 100 Resistance (kΩ) 125 Figure 7-4. RDS(ON) vs Temperature 1400 30 100 Temperature (ƒC) 1600 0 ±50 C003 Figure 7-3. Feedback Voltage Reference vs Temperature Frequency (kHz) 6 1 ±75 6 7 ±25 0 25 50 75 100 125 Temperature (ƒC) 150 C005 Figure 7-6. Frequency vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP TPS55340-EP SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 700 3.5 600 3.0 500 COMP Voltage (V) Frequency (kHz) www.ti.com 400 Non-Foldback Foldback 300 200 COMP Pin Clamp High 2.0 COMP Pin Clamp Low 1.5 1.0 100 0 −50 2.5 −25 0 25 50 75 Temperature (°C) 100 125 0.5 150 ±75 ±50 ±25 G007 RFREQ = 80 kΩ Figure 7-7. Non-Foldback Frequency vs Foldback Frequency 0 25 50 75 EN Voltage Rising EN Voltage Falling 1.200 Enable Voltage (V) Input Voltage (V) 2.600 UVLO Stop 2.550 150 C008 1.300 UVLO Start 125 Figure 7-8. COMP Clamp Voltage vs Temperature 2.700 2.650 100 Temperature (ƒC) 1.100 1.000 0.900 0.800 2.500 0.700 ±75 ±50 ±25 0 25 50 75 100 125 Temperature (ƒC) 150 Figure 7-9. Input Voltage UVLO vs Temperature ±50 ±25 100 99 95 97 96 25 50 75 100 125 150 C010 Figure 7-10. Enable Voltage vs Temperature 100 98 0 Temperature (ƒC) Minimum On Time (ns) Maximum Duty Cycle (%) ±75 C009 90 85 80 75 95 70 94 ±75 ±50 ±25 0 25 50 75 Temperature (ƒC) 100 125 150 ±75 ±50 ±25 RFREQ = 80 kΩ 0 25 50 75 Temperature (ƒC) C011 100 125 150 C012 RFREQ = 80 kΩ Figure 7-11. Maximum Duty Cycle vs Temperature Figure 7-12. Minimum On Time vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP 7 TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 8 2.100 1.900 Supply Current (mA) Shutdown Current (µns) 7 6 5 4 3 1.500 Switching 1.300 Non-Switching 1.100 0.900 0.700 2 0.500 0.300 1 ±75 ±50 ±25 0 25 50 75 Temperature (ƒC) 100 125 150 ±75 ±50 ±25 0 25 50 75 Temperature (ƒC) C013 Figure 7-13. Shutdown Current vs Temperature 8 1.700 100 125 150 C014 Figure 7-14. Supply Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 8 Detailed Description 8.1 Overview The TPS55340-EP integrates a 5-A, 40-V low-side N-channel MOSFET for boost converter output up to 38 V. The TPS55340-EP regulates the output with current mode PWM control. The PWM control circuitry turns on the switch at the beginning of each oscillator clock cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up. During this portion of the switching cycle, the output capacitor provides the load current. When the inductor current reaches a threshold level set by the error amplifier output, the power switch turns off and the external Schottky diode is forward biased to allow the inductor current to flow to the output. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats every switching cycle. The duty cycle of the converter is determined by the PWM control comparator which compares the error amplifier output and the current signal. The oscillator frequency is programmed by the external resistor or synchronized to an external clock signal. A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope compensation is necessary to avoid subharmonic oscillation that is intrinsic to peak current mode control at duty cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate to maintain stability. The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The output of the error amplifier is connected to the COMP pin. An external RC compensation network connected to the COMP pin is chosen for feedback loop stability and optimum transient response. 8.2 Functional Block Diagram VIN SW FB Error Amp EN 1.229V Reference COMP PWM Control Ramp Generator Gate Driver Lossless Current Sense S Oscillator SS FREQ SYNC AGND PGND Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP 9 TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 8.3 Feature Description 8.3.1 Switching Frequency The switching frequency is set by a resistor (RFREQ) connected to the FREQ pin of the TPS55340-EP. The relationship between the timing resistance RFREQ and frequency is shown in Figure 7-5. Do not leave this pin open. A resistor must always be connected from the FREQ pin to ground for proper operation. Calculate the resistor value required for a desired frequency using Equation 1. RFREQ(kΩ) = 57500 × ƒsw(kHz)–1.03 (1) For the given resistor value, calculate the corresponding frequency with Equation 2. ƒsw(kHz) = 41600 × RFREQ(kΩ)–0.97 (2) The TPS55340-EP switching frequency can be synchronized to an external clock signal that is applied to the SYNC pin. The required logic levels of the external clock are shown in the specification table. The recommended duty cycle of the clock is in the range of 10% to 90%. A resistor must be connected from the FREQ pin to ground when the converter is synchronized to the external clock and the external clock frequency must be within ±20% of the corresponding frequency set by the resistor. For example, if the frequency programmed by the FREQ pin resistor is 600 kHz, the external clock signal should be in the range of 480 to 720 kHz. 8.3.2 Voltage Reference and Setting Output Voltage An internal voltage reference provides a precise 1.229-V voltage reference at the error amplifier non-inverting input. To set the output voltage, select the FB pin resistor RSH and RSL according to Equation 3. æR ö VOUT = 1.229 V ´ ç SH + 1÷ è R SL ø (3) 8.3.3 Soft Start The TPS55340-EP has a built-in soft-start circuit which significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current source (6 µA typical) charges a capacitor (CSS) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the peak current and duty cycle of PWM controller. Limiting the peak switch current during start-up with a slow ramp on the SS pin reduces in-rush current and output voltage overshoot. After the capacitor reaches 1.8 V, the soft-start cycle is completed and the soft-start voltage no longer clamps the error amplifier output. When the EN is pulled low for at least 1 ms, the IC enters the shutdown mode and the SS capacitor is discharged through a 5-kΩ resistor to prepare for the next soft-start sequence. 8.3.4 Slope Compensation The TPS55340-EP has internal slope compensation to prevent subharmonic oscillations. The sensed current slope of boost converter can be expressed as Equation 4. V Sn = IN ´ RSENSE L (4) Calculate the slope compensation dv/dt using Equation 5. Se = 0.32 V RFREQ 0.5 mA + 16 ´ (1 - D) ´ 6 pF 6 pF (5) In a converter with current mode control, in addition to the output voltage feedback loop, take into account the inner current loop including the inductor current sampling effect and slope compensation on the small signal response, which can be modeled as seen in Equation 6. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-EP TPS55340-EP www.ti.com SLVSCG7A – JULY 2014 – REVISED SEPTEMBER 2021 1 He(s) = 1+ éæ S s ´ êç 1 + e Sn êëçè ù ö ÷ ´ (1 - D) - 0.5 ú ÷ úû ø + fsw s2 (p ´ fsw ) 2 (6) where • • • RSENSE (15 mΩ) is the equivalent current sense resistor RFREQ is timing resistor used to set frequency D is the duty cycle Note that if Sn