TPS57114MRTETEP

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS57114-EP SLVSCG0 – JULY 2014 TPS57114-EP 2.95-V to 6-V Input, 3.5-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Converter 1 Features 3 Description • The TPS57114-EP device is a full-featured 6-V, 3.5-A, synchronous step-down current-mode converter with two integrated MOSFETs. 1 • • • • • • • Two 12-mΩ (Typical) MOSFETs for High Efficiency at 3.5-A Loads 200-kHz to 2-MHz Switching Frequency 0.8-V ±1% Voltage Reference Over Temperature (–55°C to 125°C) Synchronizes to External Clock Adjustable Slow Start and Sequencing UV and OV Power-Good Output Thermally Enhanced 3-mm × 3-mm 16-Pin WQFN Supports Defense, Aerospace, and Medical Applications – Controlled Baseline – One Assembly and Test Site – One Fabrication Site – Available in Military (–55°C to 125°C) Temperature Range – Extended Product Life Cycle – Extended Product-Change Notification – Product Traceability 2 Applications • • • Low-Voltage, High-Density Power Systems Point-of-Load Regulation for High-Performance DSPs, FPGAs, ASICs, and Microprocessors Broadband, Networking, and Optical Communications Infrastructure The TPS57114-EP enables small designs by integrating the MOSFETs, implementing currentmode control to reduce external component count, reducing inductor size by enabling up to 2-MHz switching frequency, and minimizing the IC footprint with a small 3-mm × 3-mm thermally-enhanced WQFN package. The TPS57114-EP provides accurate regulation for a variety of loads with an accurate ±1% voltage reference (VREF) over temperature. The integrated 12-mΩ MOSFETs and 515-µA typical supply current maximize efficiency. Entering shutdown mode by using the enable pin reduces the shutdown supply current to 5.5 µA. The internal undervoltage lockout (UVLO) setting is 2.45 V, but programming the threshold with a resistor network on the enable pin can increase it. The slowstart pin controls the output-voltage start-up ramp. An open-drain power-good signal indicates the output is within 93% to 107% of its nominal voltage. Device Information(1) ORDER NUMBER PACKAGE TPS57114MRTETEP WQFN (16) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic TPS57114-EP VIN VIN CBOOT Efficiency vs Output Current BOOT 100 R4 3 Vin LO EN 95 PH R5 VOUT VSENSE SS/TR RT/CLK COMP C ss RT R3 C1 85 R1 PWRGD GND AGND POWERPAD 5 Vin 90 CO R2 Efficiency - % CI 80 75 70 65 60 fs = 500kHz 55 50 Vout = 1.8V 0 1 2 IO - Output Current - A 3 4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 5 8.1 8.2 8.3 8.4 8.5 8.6 5 5 5 6 6 9 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 9.2 Functional Block Diagram ....................................... 14 9.3 Feature Description................................................. 14 9.4 Device Functional Modes ....................................... 21 10 Application and Implementation........................ 23 10.1 Application Information.......................................... 23 10.2 Typical Application ................................................ 25 11 Power Supply Recommendations ..................... 33 12 Layout................................................................... 33 12.1 Layout Guidelines ................................................. 33 12.2 Layout Example .................................................... 34 13 Device and Documentation Support ................. 35 13.1 Trademarks ........................................................... 35 13.2 Electrostatic Discharge Caution ............................ 35 13.3 Glossary ................................................................ 35 14 Mechanical, Packaging, and Orderable Information ........................................................... 35 Detailed Description ............................................ 13 9.1 Overview ................................................................. 13 5 Revision History 2 Date Revision Notes July 2014 * Initial release. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 6 Description (continued) Frequency foldback and thermal shutdown protect the device during an overcurrent condition. The SwitcherPro™ software tool, available at www.ti.com/switcherpro, supports the TPS57114-EP. For more SWIFT™ documentation, see the TI website at www.ti.com/swift. TPS57114-EP is a current mode controller used to support various topologies such as buck converter configuration. Current mode control is a two-loop system. The switching power supply inductor is hidden within the inner current control loop. This simplifies the design of the outer voltage control loop and improves power supply performance in many ways, including better dynamics. The objective of this inner loop is to control the statespace averaged inductor current, but in practice, the instantaneous peak inductor current is the basis for control (switch current—equal to inductor current during the on time—is often sensed). If the inductor ripple current is small, peak inductor current control is nearly equivalent to average inductor current control. The peak method of inductor current control functions by comparing the upslope of inductor current (or switch current) to a current program level set by the outer loop. The comparator turns the power switch off when the instantaneous current reaches the desired level. The current ramp is usually quite small compared to the programming level, especially when VIN is low. As a result, this method is extremely susceptible to noise. A noise spike is generated each time the switch turns on. A fraction of a volt coupled into the control circuit can cause it to turn off immediately, resulting in a subharmonic operating mode with much greater ripple. Circuit layout and bypassing are critically important to successful operation. The peak current mode control method is inherently unstable at duty ratios exceeding 0.5, resulting in subharmonic oscillation. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. Slope compensation must be added to the sensed current waveform or subtracted from the control voltage to ensure stability above a 50% duty cycle. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. Current limit control design has numerous advantages: • Current mode control provided peak switch current limiting – pulse-by-pulse current limit. • The control loop is simplified as one pole because the output inductor is pushed to higher frequency, thus a two-pole system turns into two real poles. Thus, the system reduces to a first-order system and simplifies the control. • Multiple converters can be paralleled and allow equal current sharing amount the various converters. • Inherently provides for input voltage feed-forward because any perturbation in the input voltage is reflected in the switch or inductor current. Because switch or inductor current is a direct-control input, this perturbation is rapidly corrected. • The error amplifier output (outer control loop) defines the level at which the primary current (inner loop) regulates the pulse duration and output voltage. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com PH 12 PH 11 BOOT PWRGD EN VIN 7 Pin Configuration and Functions 13 14 15 16 1 VIN 2 VIN Exposed Thermal Pad 3 GND SS/TR 9 4 GND 7 6 5 AGND RT/CLK 8 VSENSE 10 COMP PH Pin Functions PIN NAME DESCRIPTION NO. AGND 5 Connect analog ground electrically to GND close to the device. BOOT 13 The device requires a bootstrap capacitor between BOOT and PH. Having the voltage on this capacitor below the minimum required by the BOOT UVLO forces the output to switch off until the capacitor recharges. COMP 7 Error amplifier output, and input to the output-switch current comparator. Connect frequency-compensation components to this pin. EN 15 Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. An alternative use of this pin can be to set the on-off threshold (adjust UVLO) with two additional resistors. 3 GND 4 Power ground. Electrically connect this pin directly to the thermal pad under the IC. 10 PH 11 The source of the internal high-side power MOSFET and the drain of the internal low-side (synchronous) rectifier MOSFET 12 PWRGD 14 An open-drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent, overvoltage, undervoltage, or EN shutdown. RT/CLK 8 Resistor-timing or external-clock input pin. SS/TR 9 Slow start and tracking. An external capacitor connected to this pin sets the output-voltage rise time. Another use of this pin is for tracking. 1 VIN 2 Input supply voltage, 2.95 to 6 V 16 VSENSE 6 Inverting node of the transconductance (gm) error amplifier Thermal pad — Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any internal PCB ground plane using multiple vias for good thermal performance. 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 8 Specifications 8.1 Absolute Maximum Ratings (1) MIN MAX VIN –0.3 7 EN –0.3 7 BOOT Input voltage PH + 7 VSENSE –0.3 3 COMP –0.3 3 PWRGD –0.3 7 SS/TR –0.3 3 RT/CLK –0.3 7 BOOT-PH Output voltage Sink current PH –0.6 7 –2 10 (1) V EN 100 µA RT/CLK 100 µA COMP 100 µA 10 mA 100 µA 150 °C PWRGD SS/TR Temperature V 7 PH 10-ns transient Source current UNIT TJ –55 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 8.2 Handling Ratings MIN Tstg Storage temperature range Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) V(ESD) Electrostatic discharge Machine model (MM) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (1) (2) (2) MAX UNIT °C –65 150 –4000 4000 –200 200 –1500 1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(VIN) Input voltage 2.95 6 V TA Operating ambient temperature –55 125 °C TJ Operating junction temperature –55 150 °C Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com 8.4 Thermal Information TPS57114-EP THERMAL METRIC (1) RTE UNIT 16 PINS Junction-to-ambient thermal resistance (2) RθJA 44.4 (3) RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance (4) 16 ψJT Junction-to-top characterization parameter (5) 0.7 ψJB Junction-to-board characterization parameter (6) 16.9 RθJC(bot) Junction-to-case (bottom) thermal resistance (7) 4.6 (1) (2) (3) (4) (5) (6) (7) 46.1 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 8.5 Electrical Characteristics TJ = –55°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN UVLO START 2.28 2.5 VIN UVLO STOP 2.45 2.6 V SUPPLY VOLTAGE (VIN PIN) Internal undervoltage-lockout threshold V Shutdown supply current V(EN) = 0 V, 2.95 V ≤ V(VIN) ≤ 6 V 5.5 15 µA Quiescent current – Iq V(VSENSE) = 0.9 V, V(VIN) = 5 V, RT = 400 kΩ 515 750 µA Rising 1.25 Falling 1.18 ENABLE AND UVLO (EN PIN) Enable threshold Input current Enable threshold + 50 mV –3.2 Enable threshold – 50 mV –1.65 V µA VOLTAGE REFERENCE (VSENSE PIN) Voltage reference 2.95 V ≤ V(VIN) ≤ 6 V, –55°C < TJ < 150°C 0.79 0.8 0.81 BOOT-PH = 5 V 12 30 BOOT-PH = 2.95 V 16 30 V(VIN) = 5 V 13 30 V(VIN) = 2.95 V 17 30 V MOSFET High-side switch resistance Low-side switch resistance mΩ mΩ ERROR AMPLIFIER Input current 2 nA Error-amplifier transconductance (gm) –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V 245 µS Error-amplifier transconductance (gm) during slow start –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, V(VSENSE) = 0.4 V 79 µS Error-amplifier source and sink V(COMP) = 1 V, 100-mV overdrive ±20 µA 25 S COMP to Iswitch gm 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 Electrical Characteristics (continued) TJ = –55°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP V(VIN) = 2.95 V, 25°C < TJ < 150°C 5 6.4 TJ = –55°C 4 MAX UNIT CURRENT LIMIT Current-limit threshold V(VIN) = 6 V, 25°C < TJ < 150°C 4.4 TJ = –55°C A 5.56 4 THERMAL SHUTDOWN Thermal shutdown Hysteresis 168 °C 20 °C TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching frequency range using RT mode Switching frequency 200 R(RT/CLK) = 400 kΩ 400 Switching frequency range using CLK mode Minimum CLK pulse duration RT/CLK voltage 500 300 2000 kHz 600 kHz 2000 kHz 80 R(RT/CLK) = 400 kΩ ns 0.5 RT/CLK high threshold 1.6 RT/CLK low threshold 0.4 V 2.5 V 0.6 V RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns PLL lock in time Measure at 500 kHz 42 µs Measured at 50% points on PH, IOUT = 3.5 A 75 Measured at 50% points on PH, V(VIN) = 6 V, IOUT = 0 A 120 PH (PH PIN) Minimum on-time Minimum off-time Rise time Fall time Prior to skipping off pulses, BOOT-PH = 2.95 V, IOUT = 3.5 A V(VIN) = 6 V, 3.5 A ns 60 ns 2.25 V/ns 2 BOOT (BOOT PIN) BOOT charge resistance V(VIN) = 5 V 16 Ω BOOT-PH UVLO V(VIN) = 2.95 V 2.1 V SLOW START AND TRACKING (SS/TR PIN) Charge current V(SS/TR) = 0.4 V 2 µA SS/TR to VSENSE matching V(SS/TR) = 0.4 V 54 mV SS/TR to reference crossover 98% normal 1.1 V SS/TR discharge voltage (overload) V(VSENSE) = 0 V 60 mV SS/TR discharge current (overload) V(VSENSE) = 0 V, V(SS/TR) = 0.4 V 350 µA SS discharge current (UVLO, EN, thermal fault) V(VIN) = 5 V, V(SS) = 0.5 V 1.9 mA V(VSENSE) falling (fault) 91 POWER-GOOD (PWRGD PIN) VSENSE threshold V(VSENSE) rising (good) 93 V(VSENSE) rising (fault) 109 V(VSENSE) falling (good) 107 Hysteresis V(VSENSE) falling 2 Output high leakage V(VSENSE) = V(VREF), V(PWRGD) = 5.5 V 7 On-resistance 56 Output low I(PWRGD) = 3 mA Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 µA Copyright © 2014, Texas Instruments Incorporated %V(VREF) %V(VREF) nA 100 0.3 0.650 Ω V 1.5 Submit Documentation Feedback V 7 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com 100000000 Electromigration fail mode Estimated Life (hours) 10000000 1000000 100000 10000 1000 100 80 90 100 110 120 130 Continuous Junction Temperature TJ (qC) 140 150 160 C021 (1) See data sheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) Enhanced plastic product disclaimer applies. Figure 1. TPS57114-EP Derating Chart 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 8.6 Typical Characteristics 510 Low Side Rdson Vin = 3.3 V High Side Rdson Vin = 3.3 V Low Side Rdson Vin = 5 V High Side Rdson Vin = 5 V 0.023 0.021 0.019 Switching Frequency (kHz) Static Drain-Source On-State Resistance (Ÿ) 0.025 0.017 0.015 0.013 0.011 0.009 505 500 495 490 485 480 0.007 0.005 475 ±75 ±50 ±25 0 25 50 75 100 125 150 Junction Temperature (ƒC) ±75 ±50 ±25 0 25 C001 RT = 400 kΩ 8.0 7.5 0.805 6.5 6.0 5.5 5.0 4.5 75 100 125 150 C002 VIN = 5 V Figure 3. Frequency vs Temperature 0.807 Voltage Reference (V) High Side Switching Current (A) Figure 2. High-Side and Low-Side rds(on) vs Temperature 7.0 50 Junction Temperature (ƒC) 0.803 0.801 0.799 0.797 0.795 4.0 VI VI = 3.3 V VI = = 55 V V VI 3.5 3.0 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) 0.793 0.791 ±75 150 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) C003 150 C004 VIN = 3.3 V Figure 5. Voltage Reference vs Temperature Figure 4. High-Side Current Limit vs Temperature 100 Nominal Switching Frequency (%) 2000 Switching Frequency (kHz) 1800 1600 1400 1200 1000 800 600 400 75 50 25 Vsense Falling Vsense Rising 0 200 80 180 280 380 480 580 Resistance (Ÿ) 680 780 880 980 C005 Figure 6. Switching Frequency vs RT Resistance, LowFrequency Range Copyright © 2014, Texas Instruments Incorporated 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Vsense (v) 0.8 C006 Figure 7. Switching Frequency vs VSENSE Submit Documentation Feedback 9 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Typical Characteristics (continued) 310 105 100 Transconductance (S) Transconductance (S) 290 270 250 230 210 190 90 85 80 75 70 65 60 170 55 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) 150 ±75 0 ±25 25 100 125 150 C008 Figure 9. Transconductance (Slow Start) vs Junction Temperature ±3.0 ±3.1 Vin = 3.3 V, Falling Pin Current (A) ±3.2 ±3.3 ±3.4 ±3.5 ±3.6 ±3.7 ±3.8 ±3.9 ±4.0 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) 150 ±75 ±50 0 ±25 25 50 75 100 125 Junction Temperature (ƒC) C009 VIN = 5 V Figure 10. EN Pin Voltage vs Temperature 150 C010 VEN = Threshold +50 mV Figure 11. EN Pin Current vs Temperature ±1.0 ±1.4 ±1.2 ±1.6 Charge Current (µA) ±1.4 Pin Current (µA) 75 VIN = 3.3 V Vin = 3.3 V, Rising ±75 ±1.6 ±1.8 ±2.0 ±2.2 ±2.4 ±2.6 ±1.8 ±2.0 ±2.2 ±2.4 ±2.6 ±2.8 ±2.8 ±3.0 ±3.0 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) VIN = 5 V VEN = Threshold –50 mV Figure 12. EN Pin Current vs Temperature 10 50 Junction Temperature (ƒC) Figure 8. Transconductance vs Temperature 1.30 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.19 1.18 1.17 1.16 1.15 ±50 C007 VIN = 3 V Threshold (V) 95 Submit Documentation Feedback 150 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 Junction Temperature (ƒC) C011 C012 VIN = 5 V Figure 13. Charge Current vs Temperature Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 Typical Characteristics (continued) 2.8 8 2.7 Shudown Supply Current (µA) UVLO Start Switching UVLO Stop Switching Input Voltage (V) 2.6 2.5 2.4 2.3 2.2 2.1 2.0 7 6 5 4 3 2 1 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) 150 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) C013 150 C014 VIN = 3.3 V Figure 14. Input Voltage vs Temperature Figure 15. Shutdown Supply Current vs Temperature 800 7 700 6 Supply Current (µA) Shutdown Supply Current (µA) 8 5 4 3 2 600 500 400 300 1 0 200 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) 6.0 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) C015 TJ = 25°C 150 C016 VIN = 3.3 V Figure 16. Shutdown Supply Current vs Input Voltage Figure 17. VIN Supply Current vs Junction Temperature 110 800 108 106 Threshold (% of Vref) Supply Current (µA) 700 600 500 400 104 102 Vsense Rising, Low Threshold (Good) Vsense Rising, High Threshold (Fault) Vsense Falling, Low Threshold (Good) Vsense Falling, High Threshold (Fault) 100 98 96 94 92 300 90 88 200 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) 6.0 C017 ±75 ±50 ±25 0 25 50 75 100 125 Junction Temperature (ƒC) 150 C018 TJ = 25°C Figure 18. VIN Supply Current vs Input Voltage Copyright © 2014, Texas Instruments Incorporated Figure 19. PWRGD Threshold vs Temperature Submit Documentation Feedback 11 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com 100 100 90 90 80 80 Vsense Offset (mV) Static Drain-Source On-State Resistance (Ÿ) Typical Characteristics (continued) 70 60 50 40 30 60 50 40 30 20 20 10 10 0 0 ±75 ±50 ±25 0 25 50 75 Junction Temperature (ƒC) 100 125 150 Figure 20. PWRGD On-Resistance vs Temperature Submit Documentation Feedback ±75 ±50 ±25 0 25 50 75 Junction Temperature (ƒC) C019 VIN = 5 V 12 70 VIN = 5 V 100 125 150 C020 SS = 0.4 V Figure 21. SS/TR to VSENSE Offset vs Temperature Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 9 Detailed Description 9.1 Overview The TPS57114-EP is a 6-V, 3.5-A, synchronous step-down (buck) converter with two integrated N-channel MOSFETs. To improve performance during line and load transients, the device implements a constantfrequency, peak-current mode control which reduces output capacitance and simplifies external frequencycompensation design. The wide switching-frequency range of 200 to 2000 kHz allows for efficiency and size optimization when selecting the output-filter components. Adjust the switching frequency using a resistor to ground on the RT/CLK pin. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the power-switch turn-on to the falling edge of an external system clock. The TPS57114-EP has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup current source; to adjust the input-voltage UVLO, use two external resistors on the EN pin. In addition, the pullup current provides a default condition, allowing the device to operate when the EN pin is floating. The total operating current for the TPS57114-EP is typically 515 µA when not switching and under no load. When the device is disabled, the supply current is less than 5.5 µA. The integrated 12-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous output currents up to 3.5 A. The TPS57114-EP reduces the external component count by integrating the boot recharge diode. A capacitor between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A UVLO circuit, which monitors the boot-capacitor voltage, turns off the high-side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS57114-EP to operate approaching 100% duty cycle. The output voltage can be stepped down to as low as the 0.8-V reference. The TPS57114-EP has a power-good comparator (PWRGD) with 2% hysteresis. The TPS57114-EP minimizes excessive output overvoltage transients by taking advantage of the overvoltage power-good comparator. The regulated output voltage exceeding 109% of the nominal voltage activates the overvoltage comparator, which turns off the high-side MOSFET and masks it from turning on until the output voltage is lower than 107% of the nominal voltage. The SS/TR (slow-start or tracking) pin minimizes inrush currents or provides power-supply sequencing during power-up. Connect a small-value capacitor to the pin for slow start. Discharging the SS/TR pin before the output powers up ensures a repeatable restart after an overtemperature fault, UVLO fault, or disabled condition. The use of a frequency-foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help limit the inductor current. L Ve Load Gate Drive VI Gate Drive VI Latch S Clock E/A PWM R Verror Figure 22. Peak Current Mode Control (See Application Note U-140) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com 9.2 Functional Block Diagram PWRGD EN VIN i1 Shutdown 91% ihys Thermal Shutdown Enable Comparator Logic UVLO Shutdown Shutdown Logic 109% Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum COMP Clamp ERROR AMPLIFIER PWM Comparator VSENSE SS/TR Current Sense BOOT Logic and PWM Latch Shutdown Logic S COMP Slope Compensation PH Frequency Shift Overload Recovery Maximum Clamp Oscillator with PLL GND TPS57114-EP Block Diagram AGND POWERPAD RT/CLK 9.3 Feature Description 9.3.1 Fixed-Frequency Pwm Control The TPS57114-EP uses an adjustable fixed-frequency peak-current mode control. An error amplifier, which drives the COMP pin, compares the output voltage through external resistors on the VSENSE pin to an internal voltage reference. An internal oscillator initiates the turn-on of the high-side power switch. The device compares the error-amplifier output to the high-side power-switch current. When the power-switch current reaches the COMP voltage level, the high-side power switch turns off and the low-side power switch turns on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level, and also implements a minimum clamp for improved transient-response performance. 9.3.2 Slope Compensation and Output Current The TPS57114-EP adds a compensating ramp to the switch-current signal. This slope compensation prevents subharmonic oscillations as the duty cycle increases. The available peak inductor current remains constant over the full duty-cycle range. 14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 Feature Description (continued) 9.3.3 Bootstrap Voltage (Boot) and Low-Dropout Operation The TPS57114-EP has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.1 µF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric and a voltage rating of 10 V or higher because of the stable characteristics over temperature and voltage. To improve dropout, the design of the TPS57114-EP is for operation at 100% duty cycle as long as the BOOT-toPH pin voltage is greater than 2.2 V. A UVLO circuit turns off the high-side MOSFET, allowing for the low-side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current sourced from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor; thus, the effective duty cycle of the switching regulator is high. 9.3.4 Error Amplifier The TPS57114-EP has a transconductance amplifier which it uses as an error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance of the error amplifier is 245 µS during normal operation. When the voltage of the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is typically greater than 79 µS, but less than 245 µS. 9.3.5 Voltage Reference The voltage-reference system produces a precise ±1% voltage reference over temperature by scaling the output of a temperature-stable band-gap circuit. The band-gap and scaling circuits produce 0.8 V at the non-inverting input of the error amplifier. 9.3.6 Adjusting the Output Voltage A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends using divider resistors with 1% tolerance or better. Start with 100 kΩ for the R1 resistor and use Equation 1 to calculate R2. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is more susceptible to noise, and voltage errors from the VSENSE input current are noticeable. vertical spacer æ ö 0.799 V R2 = R1 ´ ç ÷ è VO - 0.799 V ø (1) TPS57114-EP VO R1 VSENSE R2 0.8 V + Figure 23. Voltage-Divider Circuit Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Feature Description (continued) 9.3.7 Enable Functionality and Adjusting UVLO The VIN pin voltage falling below 2.6 V disables the TPS57114-EP. If an application requires a higher UVLO, use the EN pin as shown in Figure 24 to adjust the input voltage UVLO by connecting two external resistors. TI recommends using the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6 V. Set the rising threshold (VSTART) to provide enough hysteresis to allow for any input supply variations. The EN pin has an internal pullup current source that provides the default condition of the TPS57114-EP operating when the EN pin floats. When the EN pin voltage exceeds 1.25 V, the circuitry adds an additional 1.6 µA of hysteresis. Pulling the EN pin below 1.18 V removes the 1.6 µA. This additional current facilitates input voltage hysteresis. TPS57114-EP i hys VIN 1.6 mA i1 R1 1.6 mA EN R2 + - Figure 24. Adjustable UVLO æV ö VSTART ç ENFALLING ÷ - VSTOP è VENRISING ø R1 = æ V ö I1 ç1 - ENFALLING ÷ + Ihys V ENRISING ø è (2) vertical spacer R2 = R1´ VENFALLING VSTOP - VENFALLING + R1(I1 + Ihys ) (3) where • Ihys = 1.6 µA • I1 = 1.6 µA • VENRISING = 1.25 V • VENFALLING = 1.18 V 9.3.8 Slow-Start or Tracking Pin The TPS57114-EP regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow-start time. The TPS57114-EP has an internal pullup current source of 2 µA which charges the external slow-start capacitor. Equation 4 calculates the required slow-start capacitor value. vertical spacer Css(nF) = Tss(mS) ´ Iss(mA) Vref(V) where • • • 16 Tss is the desired slow-start time in ms Iss is the internal slow-start charging current of 2 µA Vref is the internal voltage reference of 0.8 V Submit Documentation Feedback (4) Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 Feature Description (continued) If during normal operation VIN goes below UVLO, the EN pin goes below 1.2 V, or a thermal shutdown event occurs, the TPS57114-EP stops switching. Upon VIN going above UVLO, the release or pulling high of EN, or the exit of a thermal shutdown, SS/TR discharges to below 60 mV before reinitiating a powering-up sequence. The VSENSE voltage follows the SS/TR pin voltage with a 54-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage, the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference. 9.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS57114-EP is adjustable over a wide range from 300 to 2000 kHz by placing a maximum of 700 kΩ or minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 6 or Equation 5. 235892 RT (kW ) = 1.027 fSW (kHz ) (5) vertical spacer fSW (kHz ) = 171032 0.974 RT(kW ) (6) To reduce the solution size, one would typically set the switching frequency as high as possible, but consider tradeoffs of the efficiency, maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is typically 65 ns at full-current load and 120 ns at no load and limits the maximum operating input voltage or output voltage. 9.3.10 Overcurrent Protection The TPS57114-EP implements a cycle-by-cycle current limit. During each switching cycle, the device compares the high-side switch current to the voltage on the COMP pin. When the instantaneous switch current intersects the COMP voltage, the high-side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. There is an internal clamp on the error-amplifier output. This clamp functions as a switch-current limit. 9.3.11 Frequency Shift To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS57114-EP implements a frequency shift. Without this frequency shift, during an overcurrent condition the low-side MOSFET may not turn off long enough to reduce the current in the inductor, causing a current runaway. With frequency shift, during an overcurrent condition there is a switching frequency reduction from 100% to 50%, then 25%, as the voltage decreases from 0.8 to 0 V on the VSENSE pin, to allow the low-side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the voltage on VSENSE increases from 0 to 0.8 V. See Figure 7 for details. 9.3.12 Reverse Overcurrent Protection The TPS57114-EP implements low-side current protection by detecting the voltage across the low-side MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into prebiased outputs. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Feature Description (continued) 9.3.13 Synchronize Using the RT/CLK Pin The RT/CLK pin synchronizes the converter to an external system clock (see Figure 25). To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns. If the pin goes above the PLL upper threshold, a mode change occurs, and the pin becomes a synchronization input. The device disables the internal amplifier, and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, the device re-enables the internal amplifier and the mode returns to the frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V, typically. The synchronization frequency range is 300 to 2000 kHz. The rising edge of PH synchronizes to the falling edge of the RT/CLK pin. TPS57114-EP SYNC Clock = 2 V / div PLL PH = 2 V / div RT/CLK Clock Source RT Time = 500 nsec / div Figure 25. Synchronizing to a System Clock Figure 26. Plot of Synchronizing to System Clock 9.3.14 Power Good (PWRGD Pin) The PWRGD pin output is an open-drain MOSFET. The output goes low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 107% of the internal voltage reference, the PWRGD output MOSFET turns off. TI recommends to use a pullup resistor between 1 to 100 kΩ with a voltage source that is 6 V or less. PWRGD is in a valid state after the VIN input voltage is greater than 1.1 V. 9.3.15 Overvoltage Transient Protection (OVTP) The TPS57114-EP incorporates an OVTP circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold, which is 109% of the internal voltage reference. The VSENSE pin voltage going greater than the OVTP threshold disables the high-side MOSFET, preventing current from flowing to the output and minimizing output overshoot. The VSENSE voltage dropping lower than the OVTP threshold allows the high-side MOSFET to turn on during the next clock cycle. 9.3.16 Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. When the die temperature decreases below 148°C, the device reinitiates the power-up sequence by discharging the SS pin to below 60 mV. The thermal shutdown hysteresis is 20°C. 18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 Feature Description (continued) 9.3.17 Small-Signal Model for Loop Response Figure 27 shows an equivalent model for the TPS57114-EP control loop which the user can model in a circuitsimulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 245 µS. The user can use an ideal voltage-controlled current source to model the error amplifier. Resistor R0 and capacitor C0 model the open-loop gain and frequency response of the amplifier. The 1-mV AC voltage source between nodes a and b effectively breaks the control loop for the frequency-response measurements. Plotting a or c versus frequency shows the small-signal response of the frequency compensation. Plotting a or b versus frequency shows the small-signal response of the overall loop. The user can check the dynamic loop response by replacing RL with a current source having the appropriate load-step amplitude and step rate in a time domain analysis. PH VO Power Stage 25 S a b R1 c R(ESR) R(L) COMP 0.8 V R3 C0 C2 C1 R0 VSENSE gm 245 µS C(OUT) R2 Figure 27. Small-Signal Model for Loop Response 9.3.18 Simple Small-Signal Model for Peak-Current Mode Control Figure 27 is a simple small-signal model that the user can use to understand how to design the frequency compensation. An approximation of a voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor can approximate the TPS57114-EP power stage. The control-to-output transfer function, shown in Equation 7, consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current divided by the change in COMP pin voltage (node c in Figure 27) is the power-stage transconductance. The gm for the TPS57114-EP is 25 S. The low-frequency gain of the powerstage frequency response is the product of the transconductance and the load resistance, as shown in Equation 8. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current (see Equation 9). The dashed line in the right half of Figure 28 highlights the combined effect. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it easier to design the frequency compensation. vertical spacer vertical spacer Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 19 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Feature Description (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 28. Simple Small-Signal Model and Frequency Response for Peak-Current Mode Control æ ç 1+ vo è 2p = Adc ´ vc æ ç 1+ è 2p ö s ÷ × ¦z ø ö s ÷ × ¦p ø (7) Adc = gmps ´ RL ¦p = ¦z = (8) 1 C OUT ´ R L ´ 2 p COUT (9) 1 ´ RESR ´ 2p (10) 9.3.19 Small-Signal Model for Frequency Compensation The TPS57114-EP uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency-compensation circuits. Figure 29 shows the compensation circuits. High-bandwidth power-supply designs most likely implement Type 2 circuits using low-ESR output capacitors. In Type 2A, inclusion of one additional high-frequency pole attenuates high-frequency noise. VO R1 VSENSE COMP gmea R2 Vref RO CO 5pF Type 2A R3 C2 Type 2B R3 C1 C1 Figure 29. Types of Frequency Compensation 20 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 Feature Description (continued) The design guidelines for TPS57114-EP loop compensation are as follows: 1. Calculate the modulator pole, ƒpmod, and the ESR zero, ƒz1, using Equation 11 and Equation 12. If the output voltage is a high percentage of the capacitor rating, it may be necessary to derate the output capacitor (COUT). Use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 13 and Equation 14 to estimate a starting point for the crossover frequency, ƒc. Equation 13 is the geometric mean of the modulator pole and the ESR zero and Equation 14 is the mean of the modulator pole and the switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover frequency. ¦ p m od = Iout m ax 2 p ´ Vout ´ Cout (11) vertical spacer ¦ z m od = 1 2 p ´ Resr ´ Cout (12) vertical spacer ¦C = ¦p mod ´ ¦ z mod (13) vertical spacer ¦C = ¦p mod ´ ¦ sw 2 (14) vertical spacer 2. Determine R3 with: 2p × ¦ c ´ Vo ´ COUT R3 = gmea ´ Vref ´ gmps where • • gmea is the amplifier gain (245 µS) gmps is the power stage gain (25 S) (15) vertical spacer ¦p = 3. Place a compensation zero at the dominant pole R ´ COUT C1 = L R3 1 C OUT ´ R L ´ 2 p . Determine C1 with: (16) vertical spacer 4. C2 is optional. Use it, if necessary, to cancel the 0 from the ESR of COUT. Resr ´ COUT C2 = R3 (17) 9.4 Device Functional Modes 9.4.1 RT (Resistor Timing) Mode External resistor to ground can be connected to the RT/CLK pin, which enables the user to adjust the switching frequency. The device has an internal PLL on the RT/CLK pin that synchronizes the power-switch turn on to the falling edge of an external system clock. The frequency is adjustable from 200 to 2000 kHz by using external resistor maximum of 700 kΩ or minimum of 85 kΩ (see Constant Switching Frequency and Timing Resistor (RT/CLK Pin)). Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Device Functional Modes (continued) 9.4.2 CLK (External Clock) Mode The RT/CLK pin synchronizes the converter to an external system clock. To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns. If the pin goes above the PLL upper threshold, a mode change occurs, and the pin becomes a synchronization input. The device disables the internal amplifier and the terminal is a high-impedance clock input to the internal PLL. If clocking edges stop, the device re-enables the internal amplifier and the mode returns to the frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V, typically. The synchronization frequency range is 300 to 2000 kHz. The rising edge of PH synchronizes to the falling edge of the RT/CLK pin. 22 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 10 Application and Implementation 10.1 Application Information 10.1.1 Sequencing The user can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. Implement the sequential method by using an open-drain or collector output of the power-on-reset pin of another device. Figure 30 shows the sequential method. Coupling power-good to the EN pin on the TPS57114-EP enables the second power supply after the primary supply reaches regulation. The user can accomplish ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, double the pullup current source in Equation 4. Figure 32 shows the ratiometric method. TPS57114-EP PWRGD EN EN EN1 SS SS EN2 PWRGD VO1 VO2 Figure 30. Sequential Start-Up Sequence Figure 31. Sequential Start-Up Using EN and PWRGD TPS57114-EP E EN1 N 1 EN SS/TR1 SS P PWRGD1 W R G D 1 VO1 VO2 TPS57114-EP E EN2 N 2 SS/TR2 P PWRGD2 W R G D 2 Figure 32. Schematic for Ratiometric Start-Up Sequence Copyright © 2014, Texas Instruments Incorporated Figure 33. Ratiometric Start-Up With Vout1 Leading Vout2 Submit Documentation Feedback 23 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Application Information (continued) The user can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 34 to the output of the power supply that requires tracking, or to another voltage reference source. Using Equation 18 and Equation 19 allows calculation of the tracking resistors to initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 20 is the voltage difference between Vout1 and Vout2. The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR-to-VSENSE offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the equations include Vssoffset and Iss as variables. To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 18 through Equation 20 for ΔV. Equation 20 results in a positive number for applications in which Vout2 is slightly lower than Vout1 when achieving Vout2 regulation. The requirement to pull the SS/TR pin below 60 mV before starting after an EN, UVLO, or thermal shutdown fault necessitates careful selection of the tracking resistors to ensure the device can restart after a fault. Make sure the calculated R1 value from Equation 18 is greater than the value calculated in Equation 21 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, Vssoffset becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference, as shown in Figure 33. vertical spacer R1 = Vout2 + D V Vssoffset ´ Vref Iss (18) vertical spacer R2 = Vref ´ R1 Vout2 + DV - Vref (19) vertical spacer DV = Vout1 - Vout2 (20) vertical spacer R1 > 2930 ´ Vout1- 145 ´ DV (21) vertical spacer TPS57114-EP EN1 VOUT1 EN1 SS/TR1 PWRGD1 SS2 Vout1 TPS57114-EP EN2 VOUT 2 Vout2 R1 SS/TR2 R2 PWRGD2 Figure 34. Ratiometric and Simultaneous Start-Up Sequence 24 Submit Documentation Feedback Figure 35. Ratiometric Start-Up Using Coupled SS/TR Pins Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 10.2 Typical Application U1 V(VIN) = 3 V to 6 V 16 VIN C1 1 C2 10 µF 1 R1 C3 0.1 µF 2 1 15 EN VSNS 6 R2 7 1 8 9 L1 1.5 µH VIN PH VIN PH VIN PH EN BOOT VSNS PWRGD COMP GND RT/CLK GND SS AGND 10 11 12 1 C6 0.1 µF C8 22 µF 13 14 VO = 1.8 V, 4 A 2 VOUT C9 22 µF R6 11.8 kW VSNS PWRGD 3 R7 10.0 kW 4 5 R3 7.68 kW C5 1 R5 182 kW C7 0.01 µF C4 3300 pF 1 NOT INSTALLED Figure 36. High-Frequency, 1.8-V Output Power-Supply Design With Adjusted UVLO 10.2.1 Design Requirements This example details the design of a high-frequency switching regulator using ceramic output capacitors. This design is available as the HPA375 evaluation module (EVM). To start the design process, it is necessary to know a few parameters. Determination of these parameters typically occurs at the system level. For this example, start with the following known parameters: Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Output voltage 1.8 V Transient response, 1- to 2-A load step ΔVout = 5% Maximum output current 3.5 A Input voltage 5 V nominal, 3 to 5 V Output-voltage ripple 2 ´ DIout ¦ sw ´ DVout where • • • Co > ΔIout is the change in output current ƒsw is the regulator switching frequency ΔVout is the allowable change in the output voltage 1 ´ 8 ´ ¦ sw (26) 1 Voripple Iripple where • • • ƒsw is the switching frequency Voripple is the maximum allowable output-voltage ripple Iripple is the inductor ripple current (27) Equation 28 calculates the maximum ESR an output capacitor can have to meet the output-voltage ripple specification. Equation 28 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic capacitor is much less than 55 mΩ. Factoring in additional capacitance deratings for aging, temperature, and DC bias increases this minimum value. This example uses two 22-µF, 10-V X5R ceramic capacitors with 3 mΩ of ESR. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the root-mean-square (rms) value of the maximum ripple current. Use Equation 29 to calculate the rms ripple current that the output capacitor must support. For this application, Equation 29 yields 333 mA. Voripple Resr < Iripple (28) Icorm s = Vout ´ (Vinm ax - Vout) 12 ´ Vinm ax ´ L1 ´ ¦ sw (29) 10.2.2.4 Input Capacitor The TPS57114-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at least 4.7 µF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance includes any DC-bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS57114EP. Calculate the input ripple current using Equation 30. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. The dielectrics are usually selected for power regulator capacitors are X5R and X7R ceramic because they have a high capacitance-to-volume ratio and are fairly stable over temperature. Also select the output capacitor with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. This design example requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum input voltage. The selections for this example are one 10-µF and one 0.1-µF 10-V capacitor in parallel. The input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple using Equation 31. Using the design example values, Ioutmax = 4 A, Cin = 10 µF, and ƒsw = 1 MHz, yields an inputvoltage ripple of 100 mV and an rms input-ripple current of 1.96 A. Icirms = Iout ´ Vout ´ Vinmin (Vinmin - Vout ) Vinmin (30) Ioutmax ´ 0.25 DVin = Cin ´ ¦ sw Copyright © 2014, Texas Instruments Incorporated (31) Submit Documentation Feedback 27 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com 10.2.2.5 Slow-Start Capacitor The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. Slow start is useful if a load requires a controlled rate of voltage slew. Slow start is also used if the output capacitance is large and would require large amounts of current to charge the capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor may make the TPS57114-EP reach the current limit, or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems. Calculate the slow-start capacitor value using Equation 32. For the example circuit, the slow-start time is not too critical because the output capacitor value is 44 µF, which does not require much current to charge to 1.8 V. The example circuit has the slow-start time set to an arbitrary value of 4 ms, which requires a 10-nF capacitor. In TPS57114-EP, Iss is 2.2 µA and Vref is 0.8 V. Tss(ms) ´ Iss(mA) Css(nF) = Vref(V) (32) 10.2.2.6 Bootstrap Capacitor Selection Connect a 0.1-µF ceramic capacitor between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V, or higher, voltage rating. 10.2.2.7 Output-Voltage and Feedback-Resistor Selection For the design example, the selection for R6 is 100 kΩ. Using Equation 33, calculate R7 as 80 kΩ. The nearest standard 1% resistor is 80.5 kΩ. Vref R7 = R6 Vo - Vref (33) Due to the internal design of the TPS57114-EP, a minimum output voltage limit exists for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, an output voltage limit may exist due to the minimum controllable on-time. In this case, Equation 34 gives the minimum output voltage. Voutmin = Ontimemin ´ Fsmax ´ (Vinmax - Ioutmin ´ 2 ´ RDS ) - Ioutmin ´ (RL + RDS ) where • • • • • • • Voutmin = Minimum achievable output voltage Ontimemin = Minimum controllable on-time (65 ns, typical; 120 ns, no load) Fsmax = Maximum switching frequency, including tolerance Vinmax = Maximum input voltage Ioutmin = Minimum load current RDS = Minimum high-side MOSFET on-resistance (15 to 19 mΩ) RL = Series resistance of output inductor (34) There is also a maximum achievable output voltage, which is limited by the minimum off-time. Equation 35 gives the maximum output voltage Voutmax = (1 - Offtimemax ´ Fsmax )´ (Vinmin - Ioutmax ´ 2 ´ RDS ) - Ioutmax ´ (RL + RDS ) where • • • • • • • 28 Voutmax = Maximum achievable output voltage Offtimeman = Maximum off-time (60 ns, typical) Fsmax = Maximum switching frequency, including tolerance Vinmin = Minimum input voltage Ioutmax = Maximum load current RDS = Maximum high-side MOSFET on-resistance (19 to 30 mΩ) RL = Series resistance of output inductor Submit Documentation Feedback (35) Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 10.2.2.8 Compensation Several industry techniques are used to compensate DC-DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60° and 90°. The method presented here ignores the effects of the slope compensation that is internal to the TPS57114-EP. Because of ignoring the slope compensation, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more-accurate design. To get started, calculate the modulator pole, ƒpmod, and the ESR zero, ƒz1, using Equation 36 and Equation 37. For Cout, derating the capacitor is not necessary, as the 1.8-V output is a small percentage of the 10-V capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, ƒc. For the example design, ƒpmod is 6.03 kHz and ƒzmod is 1210 kHz. Equation 38 is the geometric mean of the modulator pole and the ESR zero, and Equation 39 is the mean of the modulator pole and the switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of Equation 38 or Equation 39 as the approximate crossover frequency. For this example, ƒc is 56 kHz. Next, calculate the compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel with these two components forms the compensating pole (if needed). ¦ p m od = Iout m ax 2 p ´ Vout ´ Cout (36) 1 2 p ´ Resr ´ Cout (37) vertical spacer ¦ z m od = vertical spacer ¦C = ¦p mod ´ ¦ z mod (38) vertical spacer ¦C = ¦p mod ´ ¦ sw 2 (39) The compensation design takes the following steps: 1. Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value for the compensation network. In this example, the anticipated crossover frequency (ƒc) is 56 kHz. The power-stage gain (gmps) is 25 S, and the error-amplifier gain (gmea) is 245 µS. 2p × ¦ c ´ Vo ´ Co R3 = Gm ´ Vref ´ VIgm (40) 2. Place compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the capacitor for the compensation network using Equation 41. Ro ´ Co C3 = R3 (41) 3. The user can add an additional pole to attenuate high-frequency noise. In this application, it is not necessary to add it. From the preceding procedure, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor. 10.2.2.9 Power-Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous-conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead-time loss (Pd), switching loss (Psw), gate-drive loss (Pgd), and supply-current loss (Pq). Pcon = Io2 × rDS(on)_Temp Pd = ƒsw × Io × 0.7 × 60 × 10–9 Psw = 1 / 2 × Vin × Io × ƒsw× 8 × 10–9 Pgd = 2 × Vin × ƒsw× 2 × 10–9 Pq = Vin × 515 × 10–6 Copyright © 2014, Texas Instruments Incorporated (42) (43) (44) (45) (46) Submit Documentation Feedback 29 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com where: • IO is the output current (A) • rDS(on)_Temp is the on-resistance of the high-side MOSFET at a given temperature (Ω) • Vin is the input voltage (V) • ƒsw is the switching frequency (Hz) So Ptot = Pcon + Pd + Psw + Pgd + Pq (47) For a given TA, TJ = TA + Rth × Ptot (48) For a given TJMAX = 150°C, TAMAX = TJMAX – Rth × Ptot (49) where: • Ptot is the total device power dissipation (W) • TA is the ambient temperature (°C) • TJ is the junction temperature (°C) • Rth is the thermal resistance of the package (°C/W) • TJMAX is maximum junction temperature (°C) • TAMAX is maximum ambient temperature (°C) Additional power losses in the regulator circuit occur due to the inductor ac and dc losses and trace resistance that impact the overall efficiency of the regulator. 10.2.3 Application Curves 100 100 90 90 80 Vin = 5 V 80 Vin = 3.3 V 70 60 50 40 60 20 20 10 10 1 2 3 4 5 Vin, 1.8 Vout 40 30 0 3.3 Vin,1.8 Vout 50 30 0 30 Efficiency - % Efficiency - % 70 0 0.001 Output Current - A 0.1 Output Current - A Figure 37. Efficiency vs Load Current Figure 38. Efficiency vs Load Current Submit Documentation Feedback 0.01 1 10 Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 100 100 95 95 90 90 Vout = 1.8 V 85 Vout = 1.05 V Vout = 3.3 V 80 Efficiency - % Efficiency - % 85 75 70 65 Vout = 1.05 V 75 70 65 Vin = 5 V, fs = 1 MHz, TA = 25°C 60 55 50 Vout = 1.8 V 80 0 1 2 3 Vin = 3.3 V, fs = 1 MHz, TA = 25°C 60 55 4 50 1 0 3 2 Output Current - A Output Current - A Figure 39. Efficiency vs Load Current Figure 40. Efficiency vs Load Current VIN = 2 V/div VIN = 2 V/div EN = 1 V/div EN = 1 V/div 4 SS = 1 V/div SS = 1 V/div VOUT = 1 V/div VOUT = 1 V/div Time = 500 ms/div Time = 5 ms/div Figure 42. Power-Down VOUT, VIN Figure 41. Power-Up VOUT, VIN Vout = 100 mV / div (ac coupled) Vin = 5 V / div Vout = 2 V / div Iout = 1 A / div (0 A to 1.5 A load step) EN = 2 V / div PWRGD = 5 V / div Time = 200 usec / div Figure 43. Transient Response, 1.5-A Step Copyright © 2014, Texas Instruments Incorporated Time = 5 msec / div Figure 44. Power-Up VOUT, VIN Submit Documentation Feedback 31 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com Vin = 5 V / div Vout = 20 mV / div (ac coupled) Vout = 2 V / div PH = 2 V / div EN = 2 V / div PWRGD = 5 V / div Time = 500 nsec / div Time = 5 msec / div Figure 46. Output Ripple, 3.5 A Gain - dB Vin = 100 mV / div (ac coupled) PH = 2 V / div 60 180 50 150 40 120 30 90 20 60 10 30 0 0 –10 –30 –20 –60 –30 –90 –40 Phase - Degrees Figure 45. Power-Up VOUT, EN –120 –50 –60 10 Gain Phase 100 –150 1000 10k Frequency - Hz –180 1M 100k Time = 400 nsec / div Figure 48. Closed-Loop Response, VIN (5 V), 3.5 A Figure 47. Input Ripple, 3.5 A 0.4 0.4 0.3 0.3 Iout = 2 A Output Voltage Deviation - % Output Voltage Deviation - % Vin = 5 V 0.2 0.1 Vin = 3.3 V 0 -0.1 -0.2 0.1 0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 0 32 0.2 1 2 3 4 3 3.5 4 4.5 5 5.5 Output Current - A Input Voltage-V Figure 49. Load Regulation vs Load Current Figure 50. Regulation vs Input Voltage Submit Documentation Feedback 6 Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 11 Power Supply Recommendations This device is designed to operate from an input voltage supply range between 2.95 and 6 V. This input supply should be well regulated. If the input supply is located more than a few inches from the TPS57114-EP converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A tantalum capacitor with a value of 47 μF is a typical choice; however, this may vary depending upon the output power being delivered. 12 Layout 12.1 Layout Guidelines Layout is a critical portion of good power-supply design. There are several signal paths that conduct fastchanging currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. Take care to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Layout Example for a PCB layout example. Tie the GND pins and AGND pin directly to the thermal pad under the IC. Connect the thermal pad to any internal PCB ground planes using multiple vias directly under the IC. Use additional vias to connect the top-side ground area to the internal planes near the input and output capacitors. For operation at full-rated load, the top-side ground area along with any additional internal ground planes must provide adequate heat dissipating area. Locate the input bypass capacitor as close to the IC as possible. Route the PH pin to the output inductor. Because the PH connection is the switching node, locate the output inductor close to the PH pins and minimize the area of the PCB conductor to prevent excessive capacitive coupling. Also, locate the boot capacitor close to the device. Connect the sensitive analog ground connections for the feedback voltage divider, compensation components, slow-start capacitor, and frequency-set resistor to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise, so locate the RT resistor as close as possible to the IC and connect it with minimal lengths of trace. Place the additional external components approximately as shown. It may be possible to obtain acceptable performance with alternative PCB layout. However, this layout, meant as a guideline, produces good results. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 33 TPS57114-EP SLVSCG0 – JULY 2014 www.ti.com 12.2 Layout Example VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND VOUT OUTPUT FILTER CAPACITOR PH SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR TOPSIDE GROUND AREA COMPENSATION NETWORK VIA to Ground Plane 34 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS57114-EP www.ti.com SLVSCG0 – JULY 2014 13 Device and Documentation Support 13.1 Trademarks SWIFT, SwitcherPro are trademarks of Texas Instruments. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 35 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS57114MRTETEP ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 7114M V62/14612-01XE ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 7114M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of