TPS65168
SLVSAE5C – AUGUST 2010 – REVISED NOVEMBER 2014
High Resolution, Fully Programmable LCD Bias IC for TV
1
1 FEATURES
•
•
•
•
•
•
•
8.6 to 14.7V Input Voltage Range
6-Bit Boost Converter VDD: 12.8V to 19V
– 3.5A Switch Current Limit
Integrated Input-to-Output Isolation Switch
6-Bit Buck Converter HVDD: 6.4V to 9.55V
– 0.8A Switch Current Limit
3-Bit Buck Converter VI/O: 3V to 3.7V
– 2.8A Switch Current Limit
4-Bit Buck Converter VCORE: 0.9V to 2.4V
– 1A Switch Current Limit
2 x 4-Bit Positive Charge Pump Controller VGH:
– Low Temperature Voltage: 19V to 34V
– High Temperature Voltage: 17V to 32V
•
•
•
•
•
•
Temperature Compensation for VGH
6-Bit Negative Charge Pump Controller
VGL: –1.8V to –8.1V
Reset Signal With Programmable Delay Time
Programmable Delays For Flexible Sequencing (3
× 3 bits)
Thermal Shutdown
40-Pin 5-mm × 5-mm QFN Package
2 APPLICATIONS
•
•
LCD TVs
LCD monitors
spacing
3 DESCRIPTION
The TPS65168 provides an economic power supply solution for a wide variety of LCD bias applications. The
device provides all supply rails needed by a TFT-LCD panel. VI/O, VCORE and RST for the T-Con. VDD and HVDD
for the Source Driver and the Gamma Buffer. VGH and VGL for the Gate Driver or the Level Shifter. The VGH
voltage can be compensated for low and high adjustable temperatures, if GIP technology is used. The transition
from one programmed VGH value to another is made using an external thermistor connected to the IC. All output
rails and delay times are programmable by a Two-Wire interface: a single BOM can cover several panel types
and sizes whose desired output levels can be programmed in production and stored in a non-volatile memory
embedded into the TPS65168. Both VCORE and HVDD are generated by synchronous buck converters which
support chip inductors for an optimized solution size. The solution is delivered in a small 5x5 mm QFN package.
VIN
12 V
I²C
compatible
{
Buck Converter 1
Boost Converter
VI/O
3.3 V/2.0 A
VDD
(Integrated Isolation FET)
16 V/800 mA
Buck Converter 2
1.0 V/500 mA
Buck Converter 3
Positive Charge Pump
Temperature Compensation
Negative Charge Pump
Reset
VCORE
HVDD
8 V/500 mA
VGH
24 V/100 mA
VGL
-6 V/100 mA
RST
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65168
SLVSAE5C – AUGUST 2010 – REVISED NOVEMBER 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
4
TA
ORDERING
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65168RSB
40-Pin 5x5 QFN
TPS65168
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Input voltage range AVIN, PVINB1, PVINB3 (2)
Voltage range on pin CTRLP, FBN, VGH
(2)
UNIT
MIN
MAX
–0.3
20
V
–0.3
40
V
Voltage range on pins OUT3, SW, SWB1, SWB3, SWI, SWO (2)
–0.3
20
V
Voltage on pin A0, COMP, CTRLN, EN, OUT1, OUT2, RST, SCL, SDA, SS, SWB2, TCOMP,
VL (2)
–0.3
7
V
ESD rating HBM (Human Body Model)
2
kV
ESD rating MM (Machine Model)
200
V
ESD rating CDM (Charged Device Model)
700
V
Continuous power dissipation
See the Thermal Table
Operating junction temperature range
–40
150
°C
Storage temperature range
–65
150
°C
(1)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With respect to the GND pin.
5 THERMAL INFORMATION
TPS65168
THERMAL METRIC (1)
RSB
UNITS
40 PINS
θJA
Junction-to-ambient thermal resistance
33.9
θJCtop
Junction-to-case (top) thermal resistance
18.5
θJB
Junction-to-board thermal resistance
15.2
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
6.7
θJCbot
Junction-to-case (bottom) thermal resistance
1.9
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLVSAE5C – AUGUST 2010 – REVISED NOVEMBER 2014
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
AVIN
Input voltage range
CVL
Input capacitor on internal regulator input pin VL
MIN
TYP
MAX
8.6
12
14.7
1
UNIT
V
µF
BOOST CONVERTER
VDD
Boost output voltage range
12.8
19
V
L
Boost converter inductor
10
22
µH
CIN_BOOST
Input capacitor on boost converter input
20
COUT_BOOST
Output capacitor on boost converter output
30
µF
40
µF
BUCK 1 CONVERTER
VI/O
Buck 1 converter output voltage range
3.0
3.7
V
L1
Buck 1 converter inductor
10
22
µF
CIN_BUCK1
Input capacitor on buck 1 converter input pin PVINB1
10
COUT_BUCK1
Output capacitor on buck 1 converter output
30
µF
40
µF
BUCK 2 CONVERTER
VCORE
Buck 2 converter output voltage range
0.9
2.4
V
L2 (1)
Buck 2 converter inductor
1.0
2.2
µF
CIN_BUCK2
Input capacitor on buck 2 converter input pin OUT1
1.0
4.7
COUT_BUCK2
Output capacitor on buck 2 converter output
2.2
4.7
µF
20
µF
9.55
V
BUCK 3 CONVERTER
HVDD
L3
(1)
Buck 3 converter output voltage range
6.4
Buck 3 converter inductor
4.7
CIN_BUCK3
Input capacitor on buck 3 converter input pin PVINB3
COUT_BUCK3
Output capacitor on buck 3 converter output
6.8
10
10
4.7
10
µH
µF
20
µF
V
POSITIVE CHARGE PUMP CONTROLLER
VGH(COLD)
Positive charge pump output voltage range
19
34
VGH(HOT)
Positive charge pump output voltage range
17
32
CFLY_CPP
Positive charge pump flying capacitor
CEM_CPP
COUT_CPP
V
220
nF
Positive charge pump emitter capacitor
1
µF
Positive charge pump output capacitor
4.7
µF
NEGATIVE CHARGE PUMP CONTROLLER
VGL
Negative charge pump output voltage range
CFLY_CPN
Negative charge pump flying capacitor
–1.8
470
–8.1
V
CCOL_CPN
Negative charge pump collector capacitor
100
nF
COUT_CPN
Negative charge pump output capacitor
4.7
µF
nF
TEMPERATURE
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
For buck 2 and 3, if possible it is recommended to use shielded wire wounded chip inductors because of their stable performance over
temperature, current and frequency, and their good shielding preventing magnetic radiation.
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ELECTRICAL CHARACTERISTICS
AVIN = PVINB1 = PVINB3 = 12V, EN = VL, VDD = 16V, HVDD = 8V , VI/O = 3.3V, VCORE = 1V, VGH(COLD) = 28V, VGH(HOT) = 26V, VGL
= –5V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVIN
Input voltage range
IQ_AVIN
Supply quiescent current AVIN
Device not switching
8.6
2
mA
IQ_PVINB1
Supply quiescent current PVINB1
Device not switching
0.2
mA
IQ_PVINB3
Supply quiescent current PVINB3
Device not switching
0.6
mA
IQ_OUT1
Supply quiescent current OUT1
Device not switching
50
µA
ISD_AVIN
Supply shutdown current AVIN
EN = GND
900
µA
ISD_PVINB1
Supply shutdown current PVINB1
EN = GND
0.01
µA
ISD_PVINB3
Supply shutdown current PVINB3
EN = GND
400
AVIN rising
8.3
Hysterisis, AVIN falling
0.3
14.7
V
µA
8.6
8.9
0.8
1.3
V
UVLO
Undervoltage lockout
TSD
Thermal shutdown
TJ rising
140
°C
THYS
Thermal shutdown hysteresis
TJ falling
8
°C
V
LOGIC SIGNAL A0, EN, SCL, SDA
High level input voltage A0, EN
VIH
High level input voltage SCL, SDA
VIL
Low level input voltage
EN_pull_down
Internal pull-down resistor on EN pin
1.5
AVIN = 8.6 V to 14.7 V
V
1.2
AVIN = 8.6 V to 14.7 V
0.5
400
V
kΩ
INTERNAL OSCILLATOR
fOSC
Switching frequency of buck 1 and boost
converters
600
750
900
kHz
4.8
5.0
5.2
V
–2%
16
2%
V
90
165
mΩ
4.2
5
INTERNAL REGULATOR
VL
Internal regulator
IVL = 10 mA, EN = GND
BOOST CONVERTER [VDD]
VDD_ACC
Output voltage accuracy
VDD default value
rDS(on)
MOSFET on-resistance
ISW = current limit
ILIM
MOSFET current limit
ISS
Soft-start current
VSS = 1.230 V
Line regulation
AVIN = 8.6 V to 14.7 V, IOUT = 700 mA
0.001
%/V
Load regulation
IOUT = 0 A to 1 A
0.087
%/A
3.5
10
A
µA
ISOLATION SWITCH
rDS(on)
Isolation MOSFET on-resistance
ISWI = 1 A
170
mΩ
ISC_ISO
Short circuit current limit
VSWI = 12 V, VSWO = 0 V
350
mA
BUCK 1 CONVERTER [VI/O]
VI/O_ACC
Output voltage accuracy
VI/O default value
rDS(on)
MOSFET on-resistance
ISWB1 = current limit
ILIM
MOSFET current limit
4
–3%
2.6
3.3
3%
V
190
370
mΩ
3.4
4.2
A
Line regulation
AVIN = PVINB1 = 8.6 V to 14.7 V,
II/O = 200 mA
0.001
%/V
Load regulation
II/O = 200 mA to 800 mA
0.076
%/A
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ELECTRICAL CHARACTERISTICS (continued)
AVIN = PVINB1 = PVINB3 = 12V, EN = VL, VDD = 16V, HVDD = 8V , VI/O = 3.3V, VCORE = 1V, VGH(COLD) = 28V, VGH(HOT) = 26V, VGL
= –5V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK 2 CONVERTER [VCORE]
VCORE_ACC
Output voltage accuracy
VCORE default value
rDS(on)
MOSFET on-resistance
ISWB2 = current limit
ILIM
MOSFET current limit
fSWB2
Switching frequency buck 2 converter
–3%
1.1
1.0
3%
V
250
450
mΩ
1.4
1.8
A
3.7
MHz
0.8
Line regulation
VOUT1 = 3.0 V to 3.7 V
ICORE = 300 mA
0.004
%/V
Load regulation
ICORE = 0 A to 500 mA
0.470
%/A
BUCK 3 CONVERTER [HVDD]
HVDD_ACC
Output voltage accuracy
HVDD default value
rDS(on)
P-MOSFET on-resistance
ISWB3 = current limit
MOSFET current limit – source
ILIM
fSWB3
–3%
8
3%
V
320
450
mΩ
0.8
1.4
2
MOSFET current limit – sink
-0.8
-1.4
-2
Switching frequency buck 3 converter
0.25
2
A
MHz
Line regulation
AVIN = PVINB3 = 8.6 V to 14.7 V,
IOUT = 300 mA
0.015
%/V
Load regulation
IOUT = –500 mA to 500 mA
0.006
%/A
POSITIVE CHARGE PUMP CONTROLLER [VGH]
VGH(COLD)_ACC
VGH(HOT)_ACC
Output voltage accuracy
ICTRLP_SC
Base current during short circuit
ICTRLP
Base current
VGH(COLD) default value
–3.5%
28
3.5%
VGH(HOT) default value
–3.5%
26
3.5%
V
75
µA
VGH = GND
40
1
Line regulation
AVIN = 8.6 V to 14.7 V, IGH = 50 mA
Load regulation
IGH = 0 A to 100 mA
2
V
mA
0.001
%/V
2.32
%/A
NEGATIVE CHARGE PUMP CONTROLLER [VGL]
VGL
Programmable output voltage range
negative charge pump
-1.8
VFBN
Feedback regulation voltage
-4%
IFBN
Feedback input bias current
VFBN = 0 V
ICTRLN_SC
Base current during short circuit
VCTRLN = 0.6 V, VFBN = 20 mV
ICTRLN
Base current
VCTRLN = 0.6 V
Line regulation
AVIN = 8.6 V to 14.7 V, IGL = 50 mA
Load regulation
IGL = 0 A to 100 mA
900
200
-8.1
V
+4%
mV
0.1
µA
440
5
µA
mA
0.006
%/V
1.83
%/A
RESET GENERATOR [RST] (1)
VRST(ON)
Low voltage level
I/RST(ON) = 1 mA
ILEAK_RST
Leakage current
V/RST(ON) = VI/O = 3.3 V
(1)
0.5
V
2
µA
External pull-up resistor to be chosen so that the current flowing into /RST Pin when active (V/RST = 0 V) is below I/RST(ON) = 1 mA.
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I2C INTERFACE TIMING CHARACTERISTICS
8
PARAMETER
fSCL
(2)
TEST CONDITIONS
SCL clock frequency
tLOW
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
MIN
TYP
MAX
UNIT
Standard mode
100
kHz
Fast mode
400
kHz
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
Fast mode
600
ns
Bus free time between a STOP and
START condition
Standard mode
4.7
µs
Fast mode
1.3
µs
Hold time for a repeated START
condition
Standard mode
4.0
µs
Fast mode
600
ns
Setup time for a repeated START
condition
Standard mode
4.7
µs
Fast mode
600
ns
tsu;DAT
Data setup time
Standard mode
250
ns
thd;DAT
Data hold time
tBUF
thd;STA
tsu;STA
tRCL1
Fast mode
100
Standard mode
0.05
3.45
ns
µs
Fast mode
0.05
0.9
µs
Rise time of SCL signal after a
repeated START condition and after
an acknowledge bit
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
1000
ns
tRCL
Rise time of SCL signal
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
ns
tFCL
Fall time of SCL signal
Standard mode
20 + 0.1CB
300
ns
Fast mode
20 + 0.1CB
300
ns
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
ns
Standard mode
20 + 0.1CB
300
ns
Fast mode
20 + 0.1CB
300
ns
tRDA
Rise time of SDA signal
tFDA
Fall time of SDA signal
tsu;STO
Setup time for STOP condition
CB
(2)
Standard mode
4.0
Fast mode
600
µs
ns
Capacitive load for SDA and SCL
400
pF
Industry standard I2C timing characteristics. Not tested in production.
8.1 I2C TIMING DIAGRAMS
SDA
tf
tLOW
tsu;DAT
tr
tf
tBUF
tr
thd;STA
SCL
S
thd;STA
thd;DAT
tsu;STA
HIGH
tsu;STO
Sr
P
S
Figure 1. Serial Interface Timing for F/S-Mode
6
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SLVSAE5C – AUGUST 2010 – REVISED NOVEMBER 2014
9 DEVICE INFORMATION
NC
PVINB1
PVINB1
NC
SWB1
SWB1
NC
OUT1
SWB2
PGND2
QFN 40 pin
5mm x 5mm
(TOP VIEW)
40
39
38
37
36
35
34
33
32
31
EN
1
30
OUT2
TCOMP
2
29
SDA
VL
3
28
SCL
AGND
4
27
A0
AVIN
5
26
RST
PVINB3
6
25
NC
NC
7
24
CTRLN
SWB3
8
23
NC
OUT3
9
22
FBN
21
VGH
PowerPAD®
Exposed Thermal Die
16
17
18
19
20
SWO
NC
CTRLP
PNGD
15
SWI
COMP
14
SW
13
SW
12
PNGD
11
SS
10
PGND3
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
I
Device enable pin. Set this pin high to enable the device. See the sequencing section for more
information
TCOMP
2
I
Temperature compensation input pin. Connect the thermistor / resistors network to this pin
3
O
Internal regulator output pin. Connect an output capacitor of 1 µF to this pin
VL
AGND
4, exposed
pad
AVIN
5
I
Internal regulator supply pin
PVINB3
6
I
Buck 3 converter (HVDD) power input pin
NC
Analog ground pin. Connect this pin to the PowerPAD™
The PowerPAD™ needs to be soldered onto the ground copper plane of the PCB board for proper
power dissipation
7, 19, 23, 25,
34, 37, 40
Not connected
SWB3
8
I/O
OUT3
9
I
Buck 3 converter (HVDD) switch pin
PGND3
10
SS
11
O
Boost converter (VDD) soft-start pin. Connect a capacitor to this pin if a soft-start is needed. Open = no
soft-start
COMP
12
I/O
Boost converter (VDD) compensation pin
Buck 3 converter (HVDD) output voltage sense pin
Buck 3 converter (HVDD) power ground pin
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PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
PGND
13, 14
SW
15, 16
I/O
SWI
17
I
Isolation switch input pin. The SWI pin is connected to the internal overvoltage protection comparator of
the Boost converter
SWO
18
O
Isolation switch output pin (VDD)
CTRLP
20
O
Positive charge pump (VGH) base drive signal pin
VGH
21
I
Positive charge pump (VGH) output voltage sense pin
FBN
22
I
Negative charge pump (VGL) feedback pin
CTRLN
24
O
Negative charge pump (VGL) base drive signal pin
/RST
26
O
Reset generator open drain output pin
A0
27
I
I2C slave address select pin
SCL
28
I/O
I2C clock pin
SDA
29
I/O
I2C data pin
OUT2
30
I
PGND2
31
SWB2
32
Boost converter (VDD) power ground pin
Buck 2 converter (VCORE) output voltage sense pin
Buck 2 converter (VCORE) power ground pin
I/O
OUT1
33
I
SWB1
35, 36
I/O
PVINB1
38, 39
I
8
Boost converter (VDD) switch pin
Buck 2 converter (VCORE) switch pin
Buck 1 converter (VI/O) output voltage sense
Buck 1 converter (VI/O) switch pin
Buck 1 converter (VI/O) input supply pin
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SLVSAE5C – AUGUST 2010 – REVISED NOVEMBER 2014
VIN
8.6V to 14.7V
SWO
SWI
SW
SW
VDD
16.5V / 800mA
Boost Converter
(VDD)
+
Isolation Switch
COMP
SS
AVIN
Internal
Supply
VL
DAC
+
I²C controller
AGND
PGND
PGND
VI/O
SDA
I²C
SCL
A0
HVDD
8V / ±300mA
PVINB3
SWB3
Synchronous Buck Converter 3
(HVDD)
OUT3
PGND3
VI/O
3.3V / 400mA
SWB1
PVINB1
PVINB1
SWB1
Buck Converter 1
(VI/O)
OUT1
EN
VI/O
VCORE
1.0V / 600mA
RST
SWB2
RST
Reset
(RST)
VL
Synchronous
Buck Converter 2
(VCORE)
OUT2
PGND2
TCOMP
SWB1
Positive
Charge Pump
Controller
(VGH)
VDD
SW
VGH
26V / 100mA
+
Temperature
VGL
-5V / 100mA
Negative CTRLN
Charge Pump
Controller
FBN
(VGL)
CTRLP
VGH
VI/O
Figure 2. Simple Application Schematic
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10 TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
PARAMETER
Conditions
Figure
Buck 1 Converter
Efficiency vs. Load Current
VIN = 12 V, VI/O = 3.3 V
L = 10 µH
Figure 3
PWM Switching – Light Load
VIN = 12 V, VI/O = 3.3 V/50 mA
L = 10 µH
Figure 4
PWM Switching – Heavy Load
VIN = 12 V, VI/O = 3.3 V/ 500 mA
L = 10 µH
Figure 5
Load Transient Response
VIN = 12 V, VI/O = 3.3 V/100 ~ 500 mA
L = 10 µH, COUT = 40 µF
Figure 6
Efficiency vs. Load Current
VIN = 12 V, VCORE = 1.0 V, 1.2 V, 1.5 V, 1.8 V
L = 2.2 µH
Figure 7
PWM Switching – Light Load
VIN = 12 V, VCORE = 1.0 V/0 A
L = 2.2 µH
Figure 8
PWM Switching – Heavy Load
VIN = 12 V, VCORE = 1.0 V/500 mA
L = 2.2 µH
Figure 9
Load Transient Response
VIN = 12 V, VCORE = 3.3 V/100~ 500 mA
L = 2.2 µH, COUT = 10 µF
Figure 10
Efficiency vs. Load Current
VIN = 12 V, HVDD = 8 V
L = 6.8 µH
Figure 11
PWM Switching – Light Load
VIN = 12 V, HVDD = 8 V/0 A
L = 6.8 µH
Figure 12
PWM Switching – Heavy Load (Source)
VIN = 12 V, HVDD = 8 V/500 mA
L = 6.8 µH
Figure 13
PWM Switching – Heavy Load (Sink)
VIN = 12 V, HVDD = 8 V/–500 mA
L = 6.8 µH
Figure 14
Load Transient Response
VIN = 12 V, HVDD = 3.3 V/–500 ~ +500 mA
L = 6.8 µH, COUT = 10 µF
Figure 15
Efficiency vs. Load Current
VIN = 12 V, VDD = 16 V
L = 10 µH
Figure 16
PWM Switching – Light Load
VIN = 12 V, VDD = 16 V/0 A
L = 10 µH
Figure 17
PWM Switching – Heavy Load
VIN = 12 V, VDD = 16 V/ 700 mA
L = 10 µH
Figure 18
Load Transient Response
VIN = 12 V, VDD = 16 V/ 50 ~ 500 mA
L = 10 µH, COUT = 40 µF
Figure 19
VIN = 12 V, VGH = 28 V/ 10 ~ 60 mA
COUT = 10 µF
Figure 20
VIN = 12 V, VGL = –5 V/ 10 ~ 50 mA
COUT = 10 µF
Figure 21
VGH(COLD)1 = 34 V, VGH(HOT)1 = 17 V
VGH(COLD)2 = 27 V, VGH(HOT)2 = 24 V
Figure 23
Buck 2 Converter
Buck 3 Converter
Boost Converter
Positive Charge Pump
Load Transient Response
Negative Charge Pump
Load Transient Response
Temperature Compensation
Voltage Adjustment - [–2°C ~ 25°C)
Temperature Adjustment - [VGH(COLD) = 28 V, VGH(HOT) T°C Variation1: 2 °C ~ 18 °C
= 22 V]
T°C Variation: 16 °C ~ 32 °C
Figure 24
Sequencing
Power On Sequencing
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VIN = 12 V, VI/O = 3.3 V, VCORE = 1.0 V, VGL= –5 V
VDD= 16 V, HVDD = 8 V, VGH = 26 V
Figure 22
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100
VIN = 12 V
VI/O = 3.3 V/50 mA
90
80
Efficiency – %
70
60
VSWB1
50
40
30
20
IL1
VIN = 12 V
VI/O = 3.3 V
L = 10 µH
10
0
0.001
0.010
0.100
1.000
Iout – Load Current – A
10.000
G001
G002
Figure 3. BUCK 1 (VI/O) EFFICIENCY vs LOAD CURRENT
VIN = 12 V
VI/O = 3.3 V/500 mA
Figure 4. BUCK 1 (VI/O) PWM SWITCHING – LIGHT LOAD
VIN = 12 V, COUT = 40 μF
VI/O = 3.3 V/100 ~ 500 mA
VI/O (AC)
VSWB1
IL1
IOUT1
G003
Figure 5. BUCK 1 (VI/O) PWM SWITCHING – HEAVY LOAD
G004
Figure 6. BUCK 1 (VI/O) LOAD TRANSIENT RESPONSE
100
90
80
VIN = 12 V
VCORE = 1.0 V/0 A
VCORE = 1.8 V
VCORE = 1.5 V
Efficiency – %
70
60
VSWB2
VCORE = 1.2 V
50
40
VCORE = 1.0 V
30
20
VIN = 12 V
10
L = 2.2 µH
0
0.001
0.010
0.100
Iout – Load Current – A
IL2
1.000
G005
G006
Figure 7. BUCK 2 (VCORE) EFFICIENCY vs LOAD CURRENT
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Figure 8. BUCK 2 (VCORE) PWM SWITCHING – LIGHT LOAD
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VIN = 12 V, COUT = 10 μF
VCORE = 1.0 V/100 ~ 500 mA
VIN = 12 V
VCORE = 1.0 V/500 mA
VCORE (AC)
VSWB1
IL1
IOUT2
G007
Figure 9. BUCK 2 (VCORE) PWM SWITCHING – HEAVY LOAD
G008
Figure 10. BUCK 2 (VCORE) LOAD TRANSIENT RESPONSE
100
VIN = 12 V
HVDD = 8 V/0 A
90
VSWB3
80
Efficiency – %
70
60
50
40
30
IL3
VIN = 12 V
20
HVDD = 8 V
10
L = 6.8 µH
0
-0.6
-0.5 -0.4
-0.3 -0.2
-0.2
0.0
0.1
0.2
0.3
Iout – Load Current – A
0.4
0.5
0.6
G009
G010
Figure 11. BUCK 3 (HVDD) EFFICIENCY vs LOAD CURRENT
VIN = 12 V
HVDD = 8 V/500 mA
Figure 12. BUCK 3 (HVDD) PWM SWITCHING - LIGHT LOAD
VIN = 12 V
HVDD = 8 V/–500 mA
VSWB3
VSWB3
IL3
IL3
G011
Figure 13. BUCK 3 (HVDD) PWM SWITCHING – HEAVY LOAD
(SOURCE)
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G012
Figure 14. BUCK 3 (HVDD) PWM SWITCHING – HEAVY LOAD
(SINK)
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100
VIN = 12 V, COUT = 10 µF
HVDD = 8 V/–500 ~ +500 mA
90
HVDD (AC)
80
Efficiency – %
70
60
50
40
30
VIN = 12 V
VDD = 16 V
L = 10 µH
20
IOUT3
10
0
0.001
0.010
0.100
1.000
10.000
Iout – Load Current – A
G014
G013
Figure 15. BUCK 3 (HVDD) LOAD TRANSIENT RESPONSE
Figure 16. BOOST (VDD) EFFICIENCY vs LOAD CURRENT
VSW
VSW
VIN = 12 V
VDD = 16 V/0 A
IL
IL
VIN = 12 V
VDD = 16 V/700 mA
G015
Figure 17. BOOST (VDD) PWM SWITCHING – LIGHT LOAD
VIN = 12 V, COUT = 40 µF
VDD = 16 V/50 ~ 500 mA
Figure 18. BOOST (VDD) PWM SWITCHING – HEAVY LOAD
VIN = 12 V, COUT = 10 µF
VDD = 26 V/10 ~ 60 mA
VDD (AC)
IOUT
VGH (AC)
IGH
G017
Figure 19. BOOST (VDD) LOAD TRANSIENT RESPONSE
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G016
G018
Figure 20. CPP (VGH) LOAD TRANSIENT RESPONSE
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VGL (AC)
VIN
VI/O
VIN = 12 V, COUT = 10 µF
VDD = –5 V/10 ~ 50 mA
VCORE
RST
VGL
VDD
IGL
HVDD
VGH
G019
G022
Figure 21. CPN (VGL) LOAD TRANSIENT RESPONSE
Figure 22. POWER ON SEQUENCE
30
34
29
30
VGH(COLD) = 34 V
VGH(HOT) = 17 V
28
Vout – Output Voltage – V
Vout – Output Voltage – V
32
VGH(COLD) = 27 V
VGH(HOT) = 24 V
26
24
22
20
18
NTC = NCP18WB473F10RB
R5 = 47 kΩ, R6 = 120 kΩ
16
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Temperature – °C
G020
Figure 23. TEMPERATURE COMPENSATION VOLTAGE
ADJUSTMENT
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28
27
R5 = 47 kΩ
R6 = 1.5 MΩ
26
25
24
R5 = 82 kΩ
R6 = 1.5 MΩ
23
22
NTC = NCP18WB473F10RB
VGH(COLD) = 28 V
21 V
GH(HOT) = 22 V
20
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34
Temperature – °C
G021
Figure 24. TEMPERATURE COMPENSATION
TEMPERATURE ADJUSTMENT
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11 OUTPUT VOLTAGE RANGE SUMMARY
All outputs are programmable using a Two-Wire interface.
Boost Converter (VDD)
Number of bit address: 6
Output voltage range: 12.8V…19V
Buck 1 Converter (VI/O)
Number of bit address: 3
Output voltage range: 3.0V…3.7V
Buck 2 converter (VCORE)
Number of bit address: 4
Output voltage range: 0.9V…2.4V
Buck 3 converter (HVDD)
Number of bit address: 6
Output voltage range: 6.4V…9.55V
Positive Charge Pump Controller (VGH(COLD) – low temperature)
Number of bit address: 4
Output voltage range: 19V…34V
Positive Charge Pump Controller (VGH(HOT) – high temperature)
Number of bit address: 4
Output voltage range: 17V…32V
Negative Charge Pump (VGL)
Number of bit address: 6
Output voltage range: –1.8V…–8.1V
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11.1 SEQUENCING
The power-up sequence delays are programmable with a Two-Wire interface. DLY1, DLY2 and DLY3 can be set
per steps of 5 ms, up to 35 ms.
DLY1, 2, 3
Number of bit address: 3
Timing delay range: 0ms…35ms
11.2 POWER-UP
1. When VIN > 8.6 V the device is enabled and the RST signal is set 'low', and VL goes into regulation.
2. When EN = 'high' the buck 1 (VI/O) and buck 2 (VCORE) converters start up.
3. When PG1 and PG2 are reached and DLY1 has passed, RST is released and the negative charge pump
controller (VGL) starts.
4. When PGN is reached and DLY2 has passed, the boost converter (VDD) and the buck 3 converter (HVDD)
start.
5. When PG is reached and DLY3 has passed, the positive charge pump controller (VGH) starts.
11.3 POWER-DOWN
1. When VIN falls down below the UVLO threshold, all blocks are disabled and discharge at a rate driven by the
output load and the output capacitors mainly
UVLO
UVLO
VIN
VL
EN
PG1
VI/O
PG2
VCORE
DLY1
RST
VGL
PGN
VDD
DLY2
PG
HVDD
DLY3
VGH
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12 DETAILED DESCRIPTION
12.1 BOOST CONVERTER (VDD)
The non-synchronous boost converter uses a current mode topology and operates at a fixed frequency of
750kHz. A typical application circuit is shown in Figure 27. The external compensation allows designers to
optimize the performance for individual applications, and is easily implemented by connecting a suitable
capacitor/resistor network between the COMP pin and AGND (see design procedure section for more details).
12.1.1 Enable Signal (DLY2)
The boost converter is enabled when the power good signal from the negative charge pump controller (VGL) is
asserted and the programmed DLY2 has passed (see the Appendix section to set DLY2 timing).
12.1.2 Startup (Boost Converter)
The startup of the boost converter block operates in two steps:
1. Input-to-output isolation switch (Iso)
As soon as the internal enable signal of the boost converter is activated, the isolation switch is slowly turned
on, ramping up smoothly the current flowing from VIN into the output capacitors. The startup current is limited
to 350 mA typically, increasing as the output voltage is getting higher. Once VSWI – VSWO ≤ 1.2 V, the
isolation switch is fully turned on and the boost converter starts switching. The soft-start function is also
enabled.
2. Soft-start (SS)
To minimize the inrush current during start-up an external capacitor connected to the soft-start pin SS is
used to slowly ramp up the internal current limit of the boost converter. It is charged with a constant current
of typically 10 µA. The inductor peak current limit is proportional to the SS voltage and the maximum load
current is available after the soft-start is completed (VSS = 0.8 V) or VDD has reached its Power Good value
(90% of its nominal voltage). The larger the SS capacitor, the slower the ramp of the current limit and the
longer the soft-start time. A 100-nF capacitor is usually sufficient for most of the applications. When the EN
pin is pulled low or the undervoltage lockout of the boost converter is reached, the soft-start capacitor is
discharged to ground.
12.1.3 Protections (Boost Converter)
The boost converter is protected against potentially damaging conditions such as overvoltage and short circuits.
1. Short-Circuit Protection
The boost converter integrates a short-circuit protection circuit to prevent the inductor or the rectifier diode
from overheating when the output rail is shorted to GND. If the boost output is shorted to GND and the
voltage difference between SWI and SWO exceeds the threshold voltage of 1.2 V typically, the boost
converter shuts down and the input-to-output isolation switch limits the current to 350 mA typically.
2. Overvoltage Protection
The boost converter integrates an overvoltage protection. If the output voltage VDD exceeds the OVP
threshold of 19.5 V typically, the boost converter stops switching. The output voltage will drop below the
hysteresis and the boost converter will autonomously recover and switch again.
NOTE
Since the positive charge pump is driven from the boost converter's switch node as well as
its output, an error condition on the boost converter's output will also cause the loss of VGH
until the circuit recovers.
The boost converter also stops switching while the positive charge pump is in a short
circuit condition. This condition is not latched and the boost converter autonomously
resumes normal operation once the short circuit condition has been removed from the
positive charge pump.
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BOOST CONVERTER (VDD) (continued)
12.1.4 Setting the Output Voltage VDD
The output voltage of the boost converter is programmable via a Two-Wire interface between 12.8 V and 19 V
with a 6-bit resolution. See the Appendix section to set the VDD voltage.
12.2 Boost Converter Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements. A simple approach is to estimate the converter
efficiency, by taking the efficiency number from the provided efficiency curves at the application's maximum load
or to use a worst case assumption for the expected efficiency, e.g., 85%.
1. Duty Cycle:
D=1 -
VIN_min ´ η
VS
2. Inductor ripple current: ΔIL =
VIN_min ´ D
fOSC ´ L
ΔIL ö
æ
3. Maximum output current: IOUT_max = ç I LIM_min - 2 ÷ ´ (1 - D)
è
ø
IOUT
ΔI
+ L
1 - D
2
η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒOSC = Boost converter switching frequency (750 kHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Boost converter switch current at the desired output current (must be < ILIM_min = 3.5 A)
ΔIL = Inductor peak-to-peak ripple current
4. Peak switch current of the application: ISWPEAK =
The peak switch current is the current that the integrated switch, the inductor and the external Schottky diode
have to be able to handle. The calculation must be done for the minimum input voltage where the peak switch
current is highest.
12.2.1 Inductor Selection (Boost Converter)
Saturation current: the inductor must handle the maximum peak current (IL_SAT > ISWPEAK, or IL_SAT > ILIM_max as
conservative approach)
DC Resistance: the lower the DCR, the lower the losses
Inductor value: with a fixed frequency of 750 kHz, the recommended values are 10 µH ≤ L ≤ 22 µH. The boost
converter is optimized to work with 10 µH. The higher the inductor value, the lower the inductor ripple and output
voltage ripple but the slower the transient response.
Table 2. Inductor Selection Boost / Buck 1
L
(µH)
SUPPLIER
COMPONENT CODE
SIZE
(L x W x H mm)
DCR TYP
(mΩ)
ISAT
(A)
10
Sumida
CDRH8D43
8.3 x 8.3 x 4.5
29
4
10
Murata
LQH6PPN100M43K
6.0 x 6.0 x 4.3
53
2.6
22
Sumida
CD105NP-100M
10.4 x 9.4 x 5.8
60
2.6
22
Sumida
CDRH129-220M
12.5 x 12.5 x 10
23
5
12.2.2 Rectifier Diode Selection (Boost Converter)
Diode type: Schottky type for better efficiency
Reverse voltage: VR of the diode must block VOVP voltage (20 V recommended)
Forward current: the diode’s averaged rectified forward current IF must handle the output current since IF = IOUT
(2A recommended as conservative approach, 1A sufficient for lower output current).
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Thermal characteristics: the diode must be chosen so that it can dissipate the power (PD = IF × VF, 500 mW
should be sufficient for most of the applications)
Table 3. Rectifier Diode Selection Boost / Buck 1
PART NUMBER
VR / IAVG
VF
RθJA
SIZE
COMPONENT SUPPLIER
MBRS320
20V / 3A
0.44V at 3A
46°C/W
SMC
International Rectifier
SL22
20V / 2A
0.44V at 2A
75°C/W
SMB
Vishay Semiconductor
SS22
20V / 2A
0.50V at 2A
75°C/W
SMB
Fairchild Semiconductor
12.2.3 Compensation (COMP)
The regulation loop can be compensated by adjusting the external components connected to the COMP pin. The
COMP pin is the output of the internal transconductance error amplifier. The compensation capacitor will adjust
the low frequency gain and the resistor value will adjust the high frequency gain. Lower output voltages require a
higher gain and therefore a lower compensation capacitor value. A good start, that will work for the majority of
the applications is RCOMP = 33 kΩ and CCOMP = 1 nF.
12.2.4 Input Capacitor Selection
For good input voltage filtering low ESR ceramic capacitors are recommended. TPS65168 has an analog input
AVIN. A 1-µF bypass is required as close as possible from AVIN to GND.
Two 10-µF (or one 22-µF) ceramic input capacitor is sufficient for most of the applications. For better input
voltage filtering this value can be increased. Refer to the Recommended Operation Conditions table, Table 4 and
the Typical Application section for input capacitor recommendations.
12.2.5 Output Capacitor Selection
For best output voltage filtering a low ESR output capacitor is recommended. Typically, four 10-µF (or two 22-µF)
ceramic output capacitors work for most of the applications. Higher capacitor values can be used to improve the
load transient response. A 10 µF capacitor is also required between the rectifier diode and the SWI pin (Refer to
the Recommended Operation Conditions table, Table 4 and the Typical Application section for output capacitor
recommendations).
Table 4. Input and Output Capacitor Selection Boost / Buck 1
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
COMPONENT CODE
COMMENTS
1µF/0603
16V
Taiyo Yuden
EMK107BJ105KA
AVIN bypass
10µF/1206
16V
Taiyo Yuden
EMK212BJ106KG
CIN
10µF/1206
25V
Taiyo Yuden
TMK316BJ106KL
COUT
22µF/1210
25V
Murata
GRM32ER61E226KE15
CIN / COUT
To calculate the output voltage ripple, the following equations can be used:
I
- VIN
V
´ OUT
ΔVC = DD
ΔVC_ESR = ISWPEAK ´ RC_ESR
VDD ´ fOSC
COUT
(1)
∆VC_ESR can be neglected in many cases since ceramic capacitors provide very low ESR.
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12.3 BUCK 1 CONVERTER (VI/O)
The buck 1 converter (step-down) used in TPS65168 is a non-synchronous type that runs at a fixed frequency of
750kHz. The converter features integrated soft-start, bootstrap, and compensation circuits to minimize external
component count.
12.3.1 Enable Signal (UVLO – EN)
The buck 1 converter is enabled when the VIN voltage exceeds the UVLO threshold of 8.3 V typically and if the
EN pin is pulled 'high'. If EN is pulled 'low', the entire IC shuts down.
12.3.2 Buck 1 Converter Operation
The buck 1 converter can operate in either continuous conduction mode (CCM) or discontinuous conduction
mode (DCM), depending on the load current. At medium and high load currents, the inductor current is always
greater than zero and the converter operates in CCM; at low load currents, the inductor current is zero during
part of each switching cycle, and the converter operates in DCM. The switch node waveforms for CCM and DCM
operation are shown in Figure 4 and Figure 5. Note that the ringing seen during DCM operation (at light load)
occurs because of parasitic capacitance in the PCB layout and is normal for DCM operation. However, there is
very little energy contained in the ringing waveform and it does not significantly affect EMI performance.
Equation 2 can be used to calculate the load current below which the buck converter operates in DCM.
( VIN - VLOG IC ) VLOG IC
´
IDCM =
2 ´ L ´ fSW
VIN
(2)
The buck 1 converter uses a skip mode to regulate VI/O at very low load currents. This mode allows the converter
to maintain its output at the required voltage while still meeting the requirement of a minimum on time. During
skip mode, the buck 1 converter switches for a few cycles, then stops switching for a few cycles, and then starts
switching again and so on, for as long as the output current is below the skip mode threshold. Output voltage
ripple can be a little higher during skip mode.
12.3.3 Startup and Short Circuit Protection (Buck 1 Converter)
The buck 1 converter is limiting its switching frequency when its output voltage VI/O is below a certain threshold
(fSWB1 = 1/4 × fosc for VFB_internal < 400mV and fSWB1 = ½ × fosc for VFB_internal < 800mV). This feature avoids run
away of the inductor in case of short circuit and helps smoothing the buck converter startup as well.
12.3.4 Setting the Output Voltage VI/O
The output voltage of the buck 1 converter is programmable via a Two-Wire interface between 3.0 V and 3.7 V
with a 3-bit resolution. See the Appendix section to set the VI/O voltage.
12.4 Buck 1 Converter Design Procedure
1. Duty Cycle:D =
VI/O
VIN ´ η
2. Inductor ripple current: ΔIL =
(VIN_max - VI/O ) ´ D
fOSC ´ L
3. Maximum output current:II/O_max = ILIM_min -
ΔIL
2
ΔI
4. Peak switch current:ISWPEAK = II/O_max + L
2
η = Estimated buck 1 converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒOSC = Buck 1 converter switching frequency (750 kHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Buck 1 converter switch current (must be < ILIM_min = 2.6 A)
ΔIL = Inductor peak-to-peak ripple current
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Buck 1 Converter Design Procedure (continued)
Because the negative charge pump is driven from the buck 1 converter's switch node, ant the buck 2 converter is
driven by the output rail of the buck 1 converter, the effective output current for design purposes is greater than
II/O alone. For best performance, the effective current calculated using the following equation should be used
during the design.
VG L ´ IGL
II/O (EFFECTIVE) = II/O +
+ IIN_CORE
VI/O
(3)
12.4.1 Inductor Selection (Buck 1 Converter)
Refer to the boost converter Inductor Selection.
Inductor value: as for the boost converter, the buck 1 converter is designed to work with an inductor range as
10 µH ≤ L ≤ 22 µH. The buck 1 converter is optimized to work with 10 µH.
12.4.2 Rectifier Diode Selection (Buck 1 Converter)
Refer to the boost converter rectifier Diode Rectifier Selection.
12.4.3 Input Capacitor Selection (Buck 1 Converter)
Two 10-µF (or one 22-µF) ceramic input capacitor is sufficient for most of the applications. For better input
voltage filtering this value can be increased. Refer to the Recommended Operation Conditions table, Table 4 and
the Typical Application section for input capacitor recommendations.
12.4.4 Output Capacitor Selection (Buck 1 Converter)
For best output voltage filtering a low ESR output capacitor is recommended. Typically, four 10-µF (or two 22-µF)
ceramic output capacitors work for most of the applications. Higher capacitor values can be used to improve the
load transient response. Refer to the Recommended Operation Conditions table, Table 4 and the Typical
Application section for input capacitor recommendations.
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12.5 BUCK 2 CONVERTER (VCORE)
The TPS65168 integrates a synchronous buck 2 (step-down) converter that includes a unique hysteric PWM
controller scheme which enables switch frequencies over 3MHz, excellent transient and ac load regulation as
well as operation with tiny and cost competitive external components like chip inductors. The TPS65168’s buck 2
converter offers adjustable output voltage down to 0.9 V, ideal to support the most recent timing controllers. The
internal switch current limit of 1.1 A minimum supports output currents of up to 1 A.
12.5.1 Enable Signal (UVLO – EN)
The buck 2 converter is enabled together with the buck 1 converter when the VIN voltage exceeds the UVLO
threshold of 8.3 V typically and if the EN pin is pulled 'high'. If EN is pulled 'low', the entire IC shuts down.
12.5.2 Buck 2 Converter Operation
The converter operates in a hysteretic mode. The high side transistor (PMOS) remains turned on until a minimum
on time of tON min expires and the output voltage trips the threshold of the error comparator or the inductor current
reaches the high side switch current limit. Once the high side switch turns off, the low side switch rectifier is
turned on and the inductor current ramps down. As the output voltage falls below the threshold of the error
comparator, a switch pulse is initiated and the high side switch is turned on again. If the inductor current falls
down to zero, will continue operating with tON min and tOFF min in order to maintain the proper output voltage.
12.5.3 Startup and Short Circuit Protection (Buck 2 Converter)
The buck 2 converter tracks the buck 1 converter output voltage during startup until it has reached its
programmed value. In the event of a short circuit, the converter will operate with maximum duty cycle and the
ouput current will be limited by the internal current limit.
12.5.4 Setting the Output Voltage VCORE
The output voltage of the buck 2 converter is programmable via a Two-Wire interface between 0.9 V and 2.4 V
with a 4-bit resolution. See the Appendix section to set the VCORE voltage.
12.6 Buck 2 Converter Design Procedure
1. Duty Cycle: D =
VCORE
VI/O ´ η
2. Inductor ripple current: ΔIL =
VI/O - VCORE
V
- VCORE
´ tO N = I/O
´ D
L
L ´ f
3. Maximum output current: ICORE_max = ILIM_min -
ΔIL
2
ΔIL
2
η = Estimated buck 2 converter efficiency (use the number from the efficiency plots or 80% as an estimation)
ƒ = Buck 2 converter switching frequency (use the frequency from the frequency plots)
L = Selected inductor value for the buck 2 converter (see the Inductor Selection section)
ISWPEAK = Buck 2 converter switch current (must be < ILIM_min = 1.1 A)
ΔIL = Inductor peak-to-peak ripple current
4. Peak switch current: ISWPEAK = ICORE_max +
The peak switch current is the steady state current that the integrated switches and the inductor have to be able
to handle.
12.6.1 Inductor Selection (Buck 2 Converter)
Refer to the boost converter inductor selection.
Inductor value: the buck 2 converter is designed to work with small inductors in the following range: 1.0 µH ≤ L ≤
2.2 µH. The buck 2 converter is optimized to work with 2.2 µH.
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Buck 2 Converter Design Procedure (continued)
Table 5. Inductor Selection Buck (Chip Inductors)
L
(µH)
SUPPLIER
COMPONENT CODE
SIZE
(LxWxH mm)
DCR TYP
(mΩ)
ISAT
(A)
2.2
Murata
LQM21PN2R2
2 x 1.2 x 0.55
340
0.6
2.2
FDK
MPSZ2012D2R2
2 x 1.2 x 1
230
0.7
1.0
FDK
MIPSZ2012D1R0
2 x 1.2 x 1
90
1.1
2.2
Murata
LQM2HPN2R2MG0
2.5 x 2 x 1
80
1.3
1.0
Murata
LQM2HPN1R0MG0
2.5 x 2 x 1
90
1.5
12.6.2 Input Capacitor Selection
Because of the nature of the buck 2 converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. For most applications a minimum of 1 µF ceramic capacitor is recommended. The input capacitor
connected as close as possible to the IC on OUT1 pin can be increased without any limit for better input voltage
filtering. Refer to Table 6 for the selection of the filtering capacitors.
12.6.3 Output Capacitor Selection
The unique hysteric PWM control scheme of the TPS65168’s buck 2 converter allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. Refer to Table 6 for the selection of the output capacitors.
Table 6. Input and Output Capacitor Selection Buck 2
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
COMPONENT CODE
COMMENTS
1µF/0603
16V
Taiyo Yuden
EMK107 BJ 105KA
CIN
4.7µF/0603
10V
Taiyo Yuden
LMK107 BJ 475KA
CIN
4.7µF/0603
6.3V
Taiyo Yuden
JMK107 BJ 475_A
COUT
Note: If the Buck 2 is not used, OUT2 (pin 30) must be connected to OUT1 (pin 33) for proper startup.
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12.7 BUCK 3 CONVERTER (HVDD)
The TPS65168 integrates also a synchronous buck 3 (step-down) converter that includes a unique hysteric PWM
able to sink and source current up to 500 mA. As the buck 2 converter, the buck 3 operates in a hysteretic mode.
A significant advantage of TPS65168’s buck 3 converter compared to other hysteretic PWM controller topologies
is its excellent AC load regulation capability providing superior transient response, ideal for output current loads
switching from +500 mA to –500 mA in worst case LCD patterns.
12.7.1 Enable Signal (DLY2)
The buck 3 converter is enabled together with the boost converter when the power good of the negative charge
pump (VGL) is asserted and that the DLY2 has passed. See the Appendix section to set the DLY2 timing.
12.7.2 Startup and Short Circuit Protection (Buck 3 Converter)
The buck 3 converter output voltage tracks the boost converter output voltage ratio metric pace value during
startup. To prevent Source Driver damages, the TPS65168 implements a protection feature that disables both
the boost (VDD) and the buck 3 (HVDD) converters when short-circuits or over voltages occur on one of the two
converters. The converters will autonomously recover after the failure gone.
12.7.3 Setting the output voltage HVDD
The output voltage of the buck 3 converter is programmable via a Two-Wire interface between 6.4 V and 9.55 V
with a 6-bit resolution. See the Appendix section to set the HVDD voltage.
12.8 Buck 3 Converter Design Procedure
1. Duty Cycle: D =
HVDD
VIN ´ η
2. Inductor ripple current: ΔIL =
3.2 ´ 10-6
L
3. Maximum output current: IHVDD_max = ILIM_min -
ΔIL
2
ΔIL
2
η = Estimated buck 3 converter efficiency (use the number from the efficiency plots or 80% as an estimation)
ƒ = Buck 3 converter switching frequency (use the frequency from the frequency plots)
L = Selected inductor value for the buck 3 converter (in µH – for value see the Inductor Selection section)
ISWPEAK = Buck 3 converter switch current (must be < ILIM_min = 0.8 A)
ΔIL = Inductor peak-to-peak ripple current
4. Peak switch current: ISWPEAK = IHVDD_max +
The peak switch current is the steady state current that the integrated switches and the inductor have to be able
to handle.
12.8.1 Inductor Selection (Buck 3 Converter)
Refer to the boost converter Inductor Selection section, for more details.
Inductor value: the buck 3 converter is designed to work with small inductors in the following range: 4.7µH ≤ L ≤
10 µH. The buck 3 converter is optimized to work with 6.8 µH.
NOTE
chip inductors (such as wounded type) work well with the converter providing a small
solution size together with low magnetic radiations (because well shielded) and do not
dissipate as much energy (do not get hot)as ferrite wire wounded types.
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Buck 3 Converter Design Procedure (continued)
Table 7. Inductor Selection Buck 3 (Chip Inductors)
L
(µH)
SUPPLIER
COMPONENT CODE
SIZE
(LxWxH mm)
DCR TYP
(mΩ)
ISAT
(A)
4.7, 6.8, 10
Taiyo Yuden
CBC2518T series
2.5 x 1.8 x 1.8
260 ~ 460
480 ~ 680
4.7, 6.8, 10
Taiyo Yuden
CBC3225T series
3.2 x 2.5 x 2.5
100 ~ 133
900 ~ 1250
For wire wounded inductors other than chip style, it is important to follow the layout recommendations
in the section PCB Layout Recommendations to minimize frequency variations.
12.8.2 Input Capacitor Selection
Typically, one 10-µF ceramic capacitor on PVINB3 pin is recommended. For better input voltage filtering this
value can be increased. Refer to the Recommended Operation Conditions table, Table 4 and the Typical
Application section for input capacitor recommendations.
12.8.3 Output Capacitor Selection
Typically, one 10-µF ceramic output capacitor works for most of the applications. Refer to the Recommended
Operation Conditions table, Table 4 and the Typical Application section for output capacitor recommendations.
12.9 POSITIVE CHARGE PUMP CONTROLLER (VGH) and TEMPERATURE COMPENSATION
The positive charge pump is driven directly from the boost converter's switch node and regulated by controlling
the current through an external PNP transistor. The TPS65168 also includes a temperature compensation
feature that controls the output voltage depending on the temperature sense by an external Negative Thermistor
(NTC).
12.9.1 Enable Signal (DLY3)
The positive charge pump controller is enabled when the boost and buck 3 converters’ power good signals are
asserted and that the DLY3 has passed. See the Appendix section to set the DLY3 timing.
12.9.2 Temperature Compensation
By connecting a fixed-value thermistor between [TCOMP and GND] and a fixed-value pull-up resistor between
[VL and TCOMP], the VGH voltage will vary from given VGH(COLD) voltage at a temperatures ≤ 0°C to a lower
voltage defined by VGH(HOT) for temperatures greater than 25°C (and reversely). The user has to provide
VGH(COLD) and VGH(HOT) and the temperatures can be adjusted using the external resistors.
NOTE
The internal temperature compensation system is made to work only with 47 kΩ NTC part
number NCP18WB473F10RB (see Table 10 in Appendix section).
VL
VGH(COLD)
R5
47 kW
VGH(HOT)
TCOMP
NTC
47 kW
0°C
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R6
120 kW
25°C
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POSITIVE CHARGE PUMP CONTROLLER (VGH) and TEMPERATURE
COMPENSATION (continued)
12.9.3 Positive Charge Pump Controller Operation
During normal operation, the TPS65168 is able to provide up to 1.5 mA of base current typically and is designed
to work best with transistors whose DC gain (hFE) is between 100 and 300. The charge pump is protected
against short-circuits on its output, which are detected when the voltage on the charge pump's internal feedback
is below 100 mV. During short-circuit mode, the base current available from the CTRLP pin is limited to 60 µA
typically. Note that if a short-circuit is detected during normal operation, boost converter and buck 3 switching is
also halted until the internal feedback voltage is above 100 mV. Typical application circuits are shown in
Figure 25.
Input Regulation
Output Regulation
Figure 25. Positive Charge Pump Application Circuits
12.9.4 Setting the output voltage VGH(COLD) and VGH(HOT)
The output voltage of the positive charge pump is programmable via a Two-Wire interface between 19 V and 34
V with a 4-bit resolution for VGH(COLD), and between 17 V and 32 V with a 4-bit resolution for VGH(HOT). See the
Appendix section to set the VGH(COLD) and VGH(HOT) voltage.
NOTE
In the case where VGH(COLD) ≤ VGH(HOT), whatever the temperature is, the output voltage
will be VGH(HOT).
12.10 Positive Charge Pump Design Procedure
The regulation of the positive charge pump (CPP) can be done either on the input (transistor placed between
VDD and the diode) or on the output. For better regulation and fewer interaction between the boost converter
and the CPP controller, it is recommended to place the transistor on the output. However, during the boost
converter’s startup some high current spikes might appears on the flying capacitor until the VDD voltage is
doubled (if CPP configured in doubler mode) – time needed to charge up all the output capacitors.
12.10.1 Diodes selection (CPP)
Small-signal diodes can be used for most low current applications (
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