TPS78412QDBVRQ1

TPS784-Q1 TPS784-Q1 SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 www.ti.com TPS784-Q1 300-mA, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable 1 Features 3 Description • The TPS784-Q1 ultra low-dropout regulator (LDO) is a small, low quiescent current LDO that can source 300 mA with excellent line and load transient performance. • • • • • • • • • • • AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA Device junction temperature: –40°C to +150°C, TJ Input voltage range: 1.65 V to 6.0 V Available output voltages: – Adjustable option: 1.2 V to 5.5 V – Fixed options: 0.65 V to 5.0 V Output accuracy: 0.5% typical, 1.7% maximum 50-dB PSRR out to 100 kHz Low IQ: 25 µA (typical) Ultra-low dropout: – 115 mV (max) at 300 mA (3.3 VOUT) Internal 500-µs soft-start time to reduce inrush current Active output discharge Functional Safety-Capable – Documentation available to aid functional safety system design Packages: – 3-mm × 3-mm wettable flank VSON (8) – 5-pin SOT-23 The low output noise and great PSRR performance make the device suitable to power sensitive analog loads. The TPS784-Q1 is a flexible device for post regulation because this device supports an input voltage range from 1.65 V to 6.0 V and offers an adjustable output range of 1.2 V to 5.5 V. The device also features fixed output voltages from 0.65 V to 5.0 V for powering common voltage rails. The TPS784-Q1 offers foldback current limit to reduce power dissipation during over current condition. The EN input helps with power sequencing requirements of the system. The internal soft-start provides a controlled startup reducing the inrush current allowing for lower input capacitance to be used. The TPS784-Q1 provides an active pulldown circuit to quickly discharge output loads when disabled. Device Information(1) 2 Applications • • • • PART NUMBER Automotive head units Hybrid instrument clusters Telematics control units DC/DC converters TPS784-Q1 BODY SIZE (NOM) Wettable flank VSON (8)(2) 3.00 mm × 3.00 mm SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package. 0.25 200 TJ 55qC 40qC 160 0qC 25qC 85qC 125qC 0.2 150qC Output Voltage Accuracy (%) 180 Dropout Voltage (mV) PACKAGE 140 120 100 80 60 40 20 0.15 0.1 0.05 0 -0.05 -0.1 TJ 55qC 40qC -0.15 0qC 25qC 85qC 125qC 150qC -0.2 0 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) Dropout vs IOUT for 5.0 V 0.3 -0.25 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) 0.3 Output Accuracy vs IOUT for 5.0 V An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS784-Q1 1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................5 6.4 Thermal Information ...................................................5 6.5 Electrical Characteristics ............................................6 6.6 Typical Characteristics................................................ 8 7 Detailed Description......................................................22 7.1 Overview................................................................... 22 7.2 Functional Block Diagrams....................................... 22 7.3 Feature Description...................................................23 7.4 Device Functional Modes..........................................26 8 Application and Implementation.................................. 27 8.1 Application Information............................................. 27 8.2 Typical Application.................................................... 34 9 Power Supply Recommendations................................35 10 Layout...........................................................................36 10.1 Layout Guidelines................................................... 36 10.2 Layout Examples.................................................... 37 11 Device and Documentation Support..........................38 11.1 Device Support........................................................38 11.2 Documentation Support.......................................... 38 11.3 Receiving Notification of Documentation Updates.. 38 11.4 Support Resources................................................. 38 11.5 Trademarks............................................................. 38 11.6 Electrostatic Discharge Caution.............................. 38 11.7 Glossary.................................................................. 38 12 Mechanical, Packaging, and Orderable Information.................................................................... 39 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2020) to Revision B (April 2021) Page • Reworded the VIN conditions to have more clarity on what 1.65 V or whichever is greater applies to.............. 6 • Added line item for 1.2 V ≤ VOUT < 1.5 V dropout voltage in the DRB package. ............................................... 6 Changes from Revision * (February 2020) to Revision A (November 2020) Page • Changed document status from advance information to production data.......................................................... 1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 5 Pin Configuration and Functions OUT 1 IN 1 GND 2 EN 3 5 NC 2 4 8 IN OUT NC Thermal Pad 7 EN NC 3 6 NC NC 4 5 GND Not to scale Figure 5-1. DBV Package (Fixed), 5-Pin SOT-23, Top View Figure 5-2. DRB Package (Fixed), 8-Pin VSON, Top View OUT 1 IN 1 GND 2 EN 3 5 FB 2 4 8 IN OUT FB Thermal Pad 7 EN NC 3 6 NC NC 4 5 GND Not to scale Figure 5-3. DBV Package (Adjustable), 5-Pin SOT-23, Top View Figure 5-4. DRB Package (Adjustable), 8-Pin VSON, Top View Table 5-1. Pin Functions PIN NAME EN DBV (Adjustable) DBV (Fixed) DRB (Adjustable) DRB (Fixed) I/O 3 3 7 7 Input Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. Do not float this pin. If not used, connect EN to IN. Feedback pin. Input to the control-loop error amplifier. This pin is used to set the output voltage of the device with the use of external resistors. Do not float this pin. For adjustable-voltage version devices only FB 4 — 2 — Input GND 2 2 5 5 — IN 1 1 8 8 Input NC — 4 3, 4, 6 2, 3, 4, 6 — OUT Thermal Pad 5 5 1 1 N/A N/A Pad Pad DESCRIPTION Ground pin. This pin must be connected to ground on the board. Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground; see the Recommended Operating Conditions table. Place the input capacitor as close to the input of the device as possible. No connect pin. This pin is not internally connected. Connect to ground for best thermal performance or leave floating. A 0.47-µF or greater effective capacitance is required from OUT to ground for stability. For best transient response, use a 1-µF or larger Output ceramic capacitor from OUT to ground. Place the output capacitor as close to output of the device as possible; see the Recommended Operating Conditions table. — The thermal pad is electrically connected to the GND pin. Connect the thermal pad to a large-area GND plane for improved thermal performance. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 3 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Supply, VIN Voltage (1) (2) 6.5 UNIT V Enable, VEN –0.3 6.5 V –0.3 VIN + 0.3(2) V –0.3 2 V Output, IOUT Temperature MAX Output, VOUT Feedback, VFB Current MIN –0.3 Internally limited Operating junction, TJ –40 150 °C Storage, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The absolute maximum rating is VIN + 0.3 V or 6.5 V, whichever is smaller. 6.2 ESD Ratings VALUE V(ESD) (1) 4 Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±500 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage Adjustable output 1.2 5.5 0.65 5.0 Output voltage CIN Input capacitor 0.1 COUT Output capacitor 1(1) CFF Feed-forward capacitor(2) 0 IOUT Output current 0 COUT,ESR Output capacitor ESR VEN Enable voltage FEN Enable toggle frequency TJ Junction temperature (1) (2) MAX 6.0 VOUT Fixed output NOM 1.65 1 V V µF 200 10 UNIT µF 100 nF 300 mA 0.001 1 Ω 0 6 V 10 kHz –40 150 °C The minimum effective capacitance is 0.47 µF. Feed-forward capacitor is optional and not required for stability. 6.4 Thermal Information TPS784-Q1 THERMAL METRIC(1) DRB (VSON) DBV (SOT-23) 8 PINS 5 PINS 61.8(2) 170.8(3) °C/W UNIT RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 74.1 93.1 °C/W RθJB Junction-to-board thermal resistance 34.3 10.2 °C/W ψJT Junction-to-top characterization parameter 6.2 17.5 °C/W ψJB Junction-to-board characterization parameter 34.1 40 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 18.1 n/a °C/W (1) (2) (3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The 1s0p RθJA value (based on JEDEC 51-3) is 226.5 ℃/W for the DRB package. The 1s0p RθJA value (based on JEDEC 51-3) is 277.3 ℃/W for the DBV package. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 5 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.5 Electrical Characteristics at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(nom) + 0.5 V or 1.65 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF, unless otherwise noted. All typical values at TJ = 25°C. PARAMETER VIN TEST CONDITIONS Input voltage VOUT Output voltage VOUT Output accuracy(1) Adjustable output Fixed output 1 mA ≤ IOUT ≤ 300 mA, VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V TJ = 25°C –40°C ≤ TJ ≤ 85°C –40°C ≤ TJ ≤ 150°C VOUT Line regulation VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V VOUT Load regulation 0.1 mA ≤ IOUT ≤ 300 mA Load transient response settling time(2) (3) COUT = 10 µF ΔVOUT tR = tF = 1 µs, COUT = 10 µF Ground current ISHDN Shutdown current 1.65 6.0 1.2 5.5 0.65 5.0 –0.5 0.5 –1 1 –1.7 1.7 0.3 5 –5 10 10 IOUT = 500 µA VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V TJ = 25°C 10% V % mV µs %VOUT –10% 15 25 30 –40°C ≤ TJ ≤ 85°C 33 –40°C ≤ TJ ≤ 150°C 40 33 43 –40°C ≤ TJ ≤ 85°C 45 –40°C ≤ TJ ≤ 150°C 48 TJ = 25°C 0.01 –40°C ≤ TJ ≤ 85°C µA 0.05 0.25 –40°C ≤ TJ ≤ 150°C µA 3 VFB Feedback voltage Adjustable output only 1.182 1.2 1.218 V IFB Feedback pin current Adjustable output only –0.05 0.01 0.05 µA ICL Output current limit VIN = VOUT(nom) + 1 V, VOUT = 0.9 x VOUT(nom) (4) 420 mA ISC Short-circuit current limit VOUT = 0 V 320 162.5 0.65 V ≤ VOUT < 0.8 V VDO Dropout voltage PSRR Power-supply rejection ratio Vn Output noise voltage VUVLO 6 V –2% IOUT = 210 mA to 90 mA TJ = 25°C UNIT mV –5 IOUT = 0 mA VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V VEN ≤ 0.3 V VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V MAX –40°C ≤ TJ ≤ 150°C IOUT = 0 mA to 300 mA IGND TYP –40°C ≤ TJ ≤ 85°C IOUT = 90 mA to 210 mA Load transient response overshoot, undershoot (3) (5) MIN UVLO threshold IOUT = 300 mA, VOUT = 0.95 x VOUT(nom) IOUT = 300 mA , VIN = VOUT + 1 V mA 900 0.8 V ≤ VOUT < 1.2 V 775 1.2 V ≤ VOUT < 1.5 V 300 1.5 V ≤ VOUT < 1.8 V 175 1.8 V ≤ VOUT < 2.5 V 140 2.5 V ≤ VOUT ≤ 5.0 V 115 1.2 V ≤ VOUT < 1.5 V, DRB Package only 320 f = 1 kHz 60 f = 100 kHz 45 f = 1 MHz 30 BW = 10 Hz to 100 kHz, VOUT = 1.2 V dB 30 µVRMS VIN rising 1.32 1.42 1.6 VIN falling 1.17 1.29 1.42 280 500 VUVLO(HYST) UVLO hysteresis VIN hysteresis tSTR Start-up time From EN low-to-high transition to VOUT = VOUT(nom) x 95% VEN(HI) EN pin logic high voltage VEN(LOW) EN pin logic low voltage 130 V mV 780 0.85 0.425 Submit Document Feedback mV µs V Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.5 Electrical Characteristics (continued) at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(nom) + 0.5 V or 1.65 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF, unless otherwise noted. All typical values at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IEN Enable pin current VIN = VEN = 6.0 V 10 nA RPULLDOWN Pulldown resistance VIN = 3.3 V 120 Ω TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing 170 TSD(reset) Thermal shutdown reset temperature Reset, temperature decreasing 155 (1) (2) (3) (4) (5) °C Resistor tolerance is not included in overall accuracy in the adjustable version. The settling time is measured from when IOUT is stepped from 90 mA to 210 mA to when the output voltage recovers to VOUT = VOUT(nom) - 5 mV. This specification is verified by design. The output is being forced to 90% of the nominal VOUT value. This specification is in relation to the change from the nominal output voltage (VOUT(nom)). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 7 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 0.25 0.25 0.2 0.15 0.1 0.05 0 TJ -0.05 55qC 40qC -0.1 0qC 25qC 85qC 125qC 150qC -0.15 Output Voltage Accuracy (%) Output Voltage Accuracy (%) 0.2 -0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 T 55qC 40qC -0.2 -0.25 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) -0.25 1.5 0.3 2 2.5 VOUT = 0.65 V Figure 6-1. Output Accuracy vs IOUT 5 5.5 6 Figure 6-2. Output Accuracy vs VIN TJ 55qC 40qC 0.15 0qC 25qC 85qC 125qC 0.2 150qC 0.15 Output Accuracy (%) Output Voltage Accuracy (%) 3.5 4 4.5 Input Voltage (V) 150qC 0.25 0.2 0.1 0.05 0 -0.05 -0.1 -0.15 0.1 0.05 0 -0.05 TJ -0.1 55qC 40qC -0.15 -0.2 -0.2 -0.25 -0.25 3.8 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) 0.3 4.05 4.3 VOUT = 1.2 V 0qC 25qC 85qC 125qC 4.55 4.8 5.05 5.3 Input Voltage (V) 150qC 5.55 5.8 6 VOUT = 3.3 V Figure 6-3. Output Accuracy vs IOUT Figure 6-4. Output Accuracy vs VIN 0.25 0.25 0.2 0.2 0.15 0.15 Output Accuracy (%) Output Voltage Accuracy (%) 85qC 125qC VOUT = 0.65 V 0.25 0.1 0.05 0 -0.05 -0.1 TJ 55qC 40qC -0.15 0qC 25qC 85qC 125qC 150qC -0.2 0.1 0.05 0 -0.05 -0.1 55qC 40qC -0.15 TJ 0qC 25qC 85qC 125qC 150qC -0.2 -0.25 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) 0.3 -0.25 5.5 5.55 VOUT = 5.0 V 5.6 5.65 5.7 5.75 5.8 5.85 Input Voltage (V) 5.9 5.95 6 VOUT = 5.0 V Figure 6-5. Output Accuracy vs IOUT 8 3 0qC 25qC Figure 6-6. Output Accuracy vs VIN Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 0.2 0.2 -55 qC -40 qC 0 qC 150 qC 0.15 0.1 0.1 Accuracy (%) Line Regulation (mV) 0.15 25 qC 85 qC 125 qC 0.05 0.05 0 -0.05 0 -0.1 -0.05 -0.15 -0.1 1.5 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 -0.2 -60 6 -40 0.2 0.15 0.1 0.1 Accuracy (%) Accuracy (%) 0.2 0.15 0.05 0 -0.05 0 -0.05 -0.1 -0.15 -0.15 0 20 40 60 80 Temperature qC 100 120 140 160 -0.2 -60 -40 VOUT = 1.2 V, IOUT = 100 mA -20 0 20 40 60 80 Temperature qC 100 120 140 160 VOUT = 1.2 V, IOUT = 300 mA Figure 6-9. Accuracy vs Temperature Figure 6-10. Accuracy vs Temperature 200 200 TJ 175 55qC 40qC 150 0qC 25qC 85qC 125qC TJ 180 150qC 55qC 40qC 160 Dropout Voltage (mV) Dropout Voltage (mV) 100 120 140 160 0.05 -0.1 -20 20 40 60 80 Temperature qC Figure 6-8. Accuracy vs Temperature Figure 6-7. 50-mA Line Regulation -40 0 VOUT = 1.2 V, IOUT = 50 mA VOUT = 1.2 V, IOUT = 50 mA -0.2 -60 -20 125 100 75 50 85qC 125qC 150qC 140 120 100 80 60 25 40 0 20 -25 0qC 25qC 0 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) 0.3 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) VOUT = 1.8 V 0.3 VOUT = 3.3 V Figure 6-11. Dropout Voltage vs IOUT Figure 6-12. Dropout Voltage vs IOUT Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 9 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 200 700 TJ 180 55qC 40qC 85qC 125qC 150qC 140 120 100 80 60 TJ 0qC 25qC 55qC 40qC 600 Ground Current (PA) Dropout Voltage (mV) 160 0qC 25qC 85qC 125qC 150qC 500 400 300 200 40 100 20 0 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Output Current (A) 0 0.0001 0.3 0.001 0.005 0.02 Output Current (A) 0.05 0.1 0.2 0.4 VOUT = 5.0 V Figure 6-13. Dropout Voltage vs IOUT Figure 6-14. IGND vs IOUT 100 38 36 55qC 40qC 0qC -100 TJ 25qC 85qC 125qC Ground Current (PA) Ground Current (PA) 0 150qC -200 -300 34 32 30 -400 -500 0 0.5 1 1.5 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 6 28 -60 -40 -20 0 IOUT = 500 µA 20 40 60 80 Temperature (qC) 100 120 140 160 IOUT = 500 µA Figure 6-15. IGND vs VIN Figure 6-16. 500-µA Ground Current vs Temperature 352 3.5 351 3 350 2.5 Quiescent Current (PA) Ground Current (PA) TJ 349 348 347 346 85qC 125qC 150qC 2 1.5 1 0.5 -0.5 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 6 VEN = 0.3 V IOUT = 50 mA Figure 6-17. 50-mA Ground Current vs Temperature 10 0qC 25qC 0 345 344 -60 55qC 40qC Submit Document Feedback Figure 6-18. ISHDN vs VIN Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 300 0.8 55qC 40qC 0qC 150qC VEN(HI) VEN(LO) 0.75 0.7 Enable Voltage (V) RPulldown Resistance (:) 250 TJ 25qC 85qC 125qC 200 150 100 0.65 0.6 0.55 50 0.5 0.45 -75 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 6 -50 -25 0 VEN = 0.3 V 25 50 75 Temperature (qC) 100 125 150 VIN = 2 V Figure 6-19. Pulldown Resistor (RPulldown) vs VIN Figure 6-20. VEN(HI) and VEN(LOW) Thresholds vs Temperature 1.6 0.85 VEN(HI) VEN(LO) 0.8 TJ 55qC 40qC 1.4 0qC 25qC 85qC 125qC 150qC Output Voltage (V) Enable Voltage (V) 1.2 0.75 0.7 0.65 1 0.8 0.6 0.4 0.6 0.2 0 -50 -25 0 25 50 75 Temperature (qC) 100 125 0 150 0.05 0.1 0.2 0.25 0.3 0.35 Output Current (A) 0.4 Figure 6-21. VEN(HI) and VEN(LOW) Thresholds vs Temperature 20 TJ 0qC 25qC 85qC 125qC 150qC AC-Coupled Output Voltage (mV) 55qC 40qC 5 4 3 2 1 5 17.5 4.5 15 4 12.5 3.5 10 3 VOUT 2.5 VIN 7.5 5 2 2.5 1.5 0 1 -2.5 0.5 -5 0 0 0.05 0.1 0.15 0.5 Figure 6-22. Foldback Current Limit vs IOUT and Temperature 7 6 0.45 VOUT = 1.2 V VIN = 6 V Output Voltage (V) 0.15 0.2 0.25 0.3 0.35 Output Current (A) 0.4 0.45 0.5 VOUT = 5.0 V Input Voltage (V) 0.55 -75 0 100 200 300 400 500 600 Time (Ps) 700 800 0 900 1000 VOUT = 3.3 V, IOUT = 1 mA, slew rate = 1 V/µs Figure 6-23. Foldback Current Limit vs IOUT and Temperature Figure 6-24. Line Transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 11 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 24 4 3.5 VOUT 3 VIN 2.5 2.5 0 2 -2.5 1.5 -5 1 -7.5 0.5 0 100 200 300 400 500 600 Time (Ps) 700 800 0 900 1000 18 2.4 12 1.8 6 1.2 0 0.6 -6 0 VOUT = 3.3 V, IOUT = 300 mA, slew rate = 1 V/µs Figure 6-25. Line Transient 6 1.2 0 0.6 400 AC-Coupled Output Voltage (mV) 1.8 Voltage (V) AC-Coupled Output Voltage (mV) 12 200 300 Time (Ps) 3 VOUT 2.4 100 0 500 2.4 12 1.8 6 1.2 0 0.6 0 3 6 1.2 0 0.6 0 500 VOUT = 1.2 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 25℃ AC-Coupled Output Voltage (mV) 1.8 Voltage (V) AC-Coupled Output Voltage (mV) 12 400 VIN 18 2.4 12 1.8 6 1.2 0 0.6 -6 0 100 200 300 Time (Ps) 400 0 500 VOUT = 1.2 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = -40℃ Figure 6-29. Line Transient 12 0 500 3 VOUT 2.4 200 300 Time (Ps) 400 24 VIN 18 100 200 300 Time (Ps) Figure 6-28. Line Transient 24 0 100 VOUT = 1.2 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 150℃ Figure 6-27. Line Transient -6 VIN 18 -6 VOUT = 1.2 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = -40℃ VOUT 0 500 24 VIN 18 0 400 Figure 6-26. Line Transient 3 -6 200 300 Time (Ps) VOUT = 1.2 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 25℃ 24 VOUT 100 Voltage (V) -10 VIN Voltage (V) 5 AC-Coupled Output Voltage (mV) 10 7.5 3 VOUT 4.5 Voltage (V) 5 Input Voltage (V) AC-Coupled Output Voltage (mV) 15 12.5 Figure 6-30. Line Transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 3 20 2.4 12 1.8 6 1.2 0 0.6 200 300 Time (Ps) 400 0 500 15 2.4 10 1.6 5 0.8 0 0 -5 -0.8 -10 0 VOUT = 1.2 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 150℃ 5 0.8 0 0 -5 -0.8 400 AC-Coupled Output Voltage (mV) 1.6 Voltage (V) AC-Coupled Output Voltage (mV) 10 200 300 Time (Ps) 3.2 VOUT 2.4 100 -1.6 500 2.4 10 1.6 5 0.8 0 0 -5 -0.8 0 35 4.8 30 4.2 20 3.6 15 3 10 2.4 5 1.8 0 1.2 -5 0.6 100 200 300 Time (Ps) 400 0 500 VOUT = 3.3 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 25℃ AC-Coupled Output Voltage (mV) 5.4 Voltage (V) AC-Coupled Output Voltage (mV) VIN 25 0 200 300 Time (Ps) 400 -1.6 500 Figure 6-34. Line Transient 35 -10 100 VOUT = 1.2 V, IOUT = 300 mA, slew rate = 1 V/µs, TJ = 150℃ Figure 6-33. Line Transient VOUT VIN 15 -10 VOUT = 1.2 V, IOUT = 300 mA, slew rate = 1 V/µs, TJ = -40℃ 30 -1.6 500 20 VIN 15 0 400 Figure 6-32. Line Transient 3.2 -10 200 300 Time (Ps) VOUT = 1.2 V, IOUT = 300 mA, slew rate = 1 V/µs, TJ = 25℃ Figure 6-31. Line Transient 20 VOUT 100 Voltage (V) 100 VIN 5.4 VOUT VIN 4.8 25 4.2 20 3.6 15 3 10 2.4 5 1.8 0 1.2 -5 0.6 -10 0 100 200 300 Time (Ps) 400 Voltage (V) 0 AC-Coupled Output Voltage (mV) VOUT 18 -6 3.2 VIN Voltage (V) AC-Coupled Output Voltage (mV) VOUT Voltage (V) 24 0 500 VOUT = 3.3 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = -40℃ Figure 6-35. Line Transient Figure 6-36. Line Transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 13 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 5.4 35 4.8 30 25 4.2 20 3.6 15 3 10 2.4 5 1.8 0 1.2 -5 0.6 -10 200 300 Time (Ps) 0 500 400 4.2 20 3.6 15 3 10 2.4 5 1.8 0 1.2 -5 0.6 -10 0 VOUT = 3.3 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 150℃ 100 20 3.6 15 3 10 2.4 5 1.8 0 1.2 -5 0.6 100 200 300 Time (Ps) AC-Coupled Output Voltage (mV) 4.8 4.2 -10 35 Voltage (V) AC-Coupled Output Voltage (mV) VIN 25 0 0 500 400 5.4 VOUT 30 4.2 20 3.6 15 3 10 2.4 5 1.8 0 1.2 -5 0.6 0 100 1800 1500 -40 1200 -60 900 -80 600 -100 300 -120 200 250 300 Time (Ps) 350 400 450 0 500 VIN = 5.5 V, VOUT = 5.0 V, IOUT slew rate = 1 A/µs Figure 6-41. IOUT Transient From 1 mA to 300 mA 14 40 AC-Coupled Output Voltage (mV) 0 -20 150 0 500 400 VOUT = 3.3 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 150℃ Output Current (mA) AC-Coupled Output Voltage (mV) 20 100 200 300 Time (Ps) Figure 6-40. Line Transient 2400 VOUT IOUT 2100 50 4.8 25 Figure 6-39. Line Transient 0 VIN -10 VOUT = 3.3 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = -40℃ 40 0 500 400 Figure 6-38. Line Transient 5.4 30 200 300 Time (Ps) VOUT = 3.3 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 25℃ Figure 6-37. Line Transient 35 VOUT 4.8 25 Voltage (V) 100 VIN 20 2400 VOUT IOUT 2100 0 1800 -20 1500 -40 1200 -60 900 -80 600 -100 300 -120 0 2.5 5 7.5 10 12.5 Time (Ps) 15 17.5 Output Current (mA) 0 5.4 VOUT Voltage (V) VIN AC-Coupled Output Voltage (mV) VOUT 30 Voltage (V) AC-Coupled Output Voltage (mV) 35 0 20 VIN = 5.5 V, VOUT = 5.0 V, IOUT slew rate = 1 A/µs Figure 6-42. IOUT Transient From 1 mA to 300 mA Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) 2400 VOUT IOUT 2100 40 1800 30 1500 20 1200 10 900 0 600 -10 300 2.5 5 7.5 10 12.5 Time (Ps) 15 0 20 17.5 2400 VOUT IOUT 2100 0 1800 -20 1500 -40 1200 -60 900 -80 600 -100 300 -120 0 VIN = 5.5 V, VOUT = 5.0 V, IOUT slew rate = 1 A/µs 150 200 250 300 Time (Ps) 350 400 450 0 500 Figure 6-44. IOUT Transient From 1 mA to 300 mA 2400 60 20 VOUT IOUT 2100 50 2400 VOUT IOUT 2100 0 1800 40 1800 -20 1500 30 1500 -40 1200 20 1200 -60 900 10 900 -80 600 0 600 -100 300 -120 0 2.5 5 7.5 10 12.5 Time (Ps) 15 AC-Coupled Output Voltage (mV) 40 Output Current (mA) AC-Coupled Output Voltage (mV) 100 VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs Figure 6-43. IOUT Transient From 300 mA to 1 mA 0 20 17.5 15 17.5 20 -10 300 -20 200 -30 100 0 500 VOUT = 1.2 V, IOUT = 0 mA to 100 mA , IOUT slew rate = 1 A/µs, TJ = 25℃ AC-Coupled Output Voltage (mV) 400 Output Current (mA) 0 400 10 12.5 Time (Ps) 600 VOUT 500 200 300 Time (Ps) 7.5 IOUT 10 100 5 Figure 6-46. IOUT Transient From 1-mA to 300-mA Falling Edge 600 0 2.5 0 20 VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 0.5 A/µs 20 -40 300 0 Figure 6-45. IOUT Transient From 1-mA to 300-mA Rising Edge VOUT -10 -20 VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs AC-Coupled Output Voltage (mV) 50 Output Current (mA) 0 20 IOUT 10 500 0 400 -10 300 -20 200 -30 100 -40 0 100 200 300 Time (Ps) 400 Output Current (mA) -20 40 AC-Coupled Output Voltage (mV) 50 Output Current (mA) AC-Coupled Output Voltage (mV) 60 Output Current (mA) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 0 500 VOUT = 1.2 V, IOUT = 0 mA to 100 mA , IOUT slew rate = 1 A/µs, TJ = -40℃ Figure 6-47. Load Transient Figure 6-48. Load Transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 15 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 500 0 400 -10 300 -20 200 -30 100 -40 0 500 400 20 2400 0 1800 -20 1200 -40 600 -60 0 VOUT = 1.2 V, IOUT = 0 mA to 100 mA , IOUT slew rate = 1 A/µs, TJ = 150℃ 100 0 1800 -20 1200 -40 600 200 300 Time (Ps) 400 AC-Coupled Output Voltage (mV) 2400 100 2400 VOUT Output Current (mA) AC-Coupled Output Voltage (mV) 60 IOUT 20 0 0 500 1800 -20 1200 -60 600 0 100 400 -5 300 -10 200 -15 100 120 Time (Ps) 160 VOUT = 1.2 V, IOUT = 90 mA to 200 mA, IOUT slew rate = 1 A/µs, TJ = 25℃ 0 200 AC-Coupled Output Voltage (mV) 500 0 80 600 VOUT IOUT 5 500 0 400 -5 300 -10 200 -15 100 -20 0 40 80 120 Time (Ps) 160 0 200 VOUT = 1.2 V, IOUT = 90 mA to 200 mA, IOUT slew rate = 1 A/µs, TJ = -40℃ Figure 6-53. Load Transient 16 0 500 10 Output Current (mA) AC-Coupled Output Voltage (mV) 600 VOUT IOUT 40 400 Figure 6-52. Load Transient 10 0 200 300 Time (Ps) VOUT = 1.2 V, IOUT = 0 mA to 300 mA , IOUT slew rate = 1 A/µs, TJ = 150℃ Figure 6-51. Load Transient -20 IOUT 20 -100 VOUT = 1.2 V, IOUT = 0 mA to 300 mA , IOUT slew rate = 1 A/µs, TJ = -40℃ 5 0 500 Figure 6-50. Load Transient 3000 -60 400 VOUT = 1.2 V, IOUT = 0 mA to 300 mA , IOUT slew rate = 1 A/µs, TJ = 25℃ Figure 6-49. Load Transient 40 VOUT 200 300 Time (Ps) Output Current (mA) 200 300 Time (Ps) IOUT Output Current (mA) 100 AC-Coupled Output Voltage (mV) VOUT 10 0 3000 IOUT Output Current (mA) AC-Coupled Output Voltage (mV) 40 600 VOUT Output Current (mA) 20 Figure 6-54. Load Transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 500 0 400 -5 300 -10 200 -15 100 80 120 Time (Ps) 160 0 200 700 10 600 0 500 -10 400 -20 300 -30 200 -40 100 -50 0 VOUT = 1.2 V, IOUT = 90 mA to 200 mA, IOUT slew rate = 1 A/µs, TJ = 150℃ 100 Figure 6-55. Load Transient 30 700 20 IOUT 600 0 500 -10 400 -20 300 -30 200 -40 100 -50 0 100 200 300 Time (Ps) 400 AC-Coupled Output Voltage (mV) 10 0 500 1000 VOUT 800 0 700 -10 600 -20 500 -30 400 -40 300 -50 200 -60 100 0 100 10 1000 -10 800 -30 600 -50 400 -70 200 200 300 Time (Ps) 400 0 500 VOUT = 3.3 V, IOUT = 0 mA to 300 mA, IOUT slew rate = 1 A/µs, TJ = 25℃ AC-Coupled Output Voltage (mV) 1200 Output Current (mA) AC-Coupled Output Voltage (mV) 50 1400 VOUT 30 100 400 Figure 6-58. Load Transient 1400 0 200 300 Time (Ps) 0 500 VOUT = 3.3 V, IOUT = 0 mA to 100 mA, IOUT slew rate = 1 A/µs, TJ = 150℃ IOUT -90 900 10 Figure 6-57. Load Transient VOUT IOUT -70 VOUT = 3.3 V, IOUT = 0 mA to 100 mA, IOUT slew rate = 1 A/µs, TJ = -40℃ 50 0 500 Figure 6-56. Load Transient 800 Output Current (mA) AC-Coupled Output Voltage (mV) 20 400 VOUT = 3.3 V, IOUT = 0 mA to 100 mA, IOUT slew rate = 1 A/µs, TJ = 25℃ 30 VOUT 200 300 Time (Ps) Output current (mA) 40 IOUT 20 IOUT 30 1200 10 1000 -10 800 -30 600 -50 400 -70 200 -90 0 100 200 300 Time (Ps) 400 Output Current (mA) -20 AC-Coupled Output Voltage (mV) VOUT 5 0 800 IOUT Output Current (mA) AC-Coupled Output Voltage (mV) 30 600 VOUT Output Current (mA) 10 0 500 VOUT = 3.3 V, IOUT = 0 mA to 300 mA, IOUT slew rate = 1 A/µs, TJ = -40℃ Figure 6-59. Load Transient Figure 6-60. Load Transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 17 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 1600 15 30 1400 10 700 10 1200 5 600 -10 1000 0 500 -30 800 -50 600 -70 400 -90 200 200 300 Time (Ps) 0 500 400 -5 400 -10 300 -15 200 -20 100 -25 0 100 VOUT = 3.3 V, IOUT = 0 mA to 300 mA, IOUT slew rate = 1 A/µs, TJ = 150℃ 600 0 500 -5 400 -10 300 -15 200 -20 100 -25 0 500 400 AC-Coupled Output Voltage (mV) 5 Output Current (mA) AC-Coupled Output Voltage (mV) 800 VOUT 700 200 300 Time (Ps) 15 IOUT 10 100 700 5 600 0 500 -5 400 -10 300 -15 200 -20 100 -25 0 100 80 Power Supply Rejejction Ratio (dB) Power Supply Rejection Ratio (dB) 90 80 70 60 50 40 30 10 0 10 100 1k 200 mA 300 mA 10k 100k Frequency (Hz) 1M VIN = 1.65 V, CIN = 0 µF, VOUT = 0.65 V 10M IOUT 1 mA 10 mA 50 mA 70 100 mA 200 mA 300 mA 60 50 40 30 20 10 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M VIN = 2.2 V, CIN = 0 µF, VOUT = 1.2 V Figure 6-65. PSRR vs Frequency and IOUT 18 400 Figure 6-64. Load Transient 90 1 mA 10 mA 200 300 Time (Ps) 0 500 VOUT = 3.3 V, IOUT = 90 mA to 200 mA, IOUT slew rate = 1 A/µs, TJ = 150℃ Figure 6-63. Load Transient IOUT 50 mA 100 mA IOUT 10 VOUT = 3.3 V, IOUT = 90 mA to 200 mA, IOUT slew rate = 1 A/µs, TJ = -40℃ 20 0 500 400 Figure 6-62. Load Transient 800 0 200 300 Time (Ps) VOUT = 3.3 V, IOUT = 90 mA to 200 mA, IOUT slew rate = 1 A/µs, TJ = 25℃ Figure 6-61. Load Transient 15 VOUT IOUT Output Current (mA) 100 AC-Coupled Output Voltage (mV) VOUT -110 0 800 IOUT Output Current (mA) AC-Coupled Output Voltage (mV) VOUT Output Current (mA) 50 Figure 6-66. PSRR vs Frequency and IOUT Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) 90 90 80 80 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 70 60 50 40 30 IOUT 50 mA 100 mA 1 mA 10 mA 20 200 mA 300 mA 10 0 10 100 1k 10k 100k Frequency (Hz) 1M 60 50 40 30 20 10 Figure 6-67. PSRR vs Frequency and IOUT 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 6-68. PSRR vs Frequency and COUT 90 100 200 mV 300 mV 90 VDO (mV) 400 mV 500 mV 600 mV 700 mV 1V 80 70 60 50 40 30 20 10 0 10 100 1k 10k 100k Frequency (Hz) 1M Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 10 PF VIN = 4.3 V, CIN = 0 µF, VOUT = 3.3 V, IOUT = 300 mA 110 80 70 60 50 40 30 100 10 µF 60 50 40 30 20 10 Output Voltage Noise (PV/—Hz) COUT 4.7 µF 70 0 10 10k 100k Frequency (Hz) 1M 10M Figure 6-70. PSRR vs Frequency and IOUT 90 1.0 µF 1k VIN = 6 V, CIN = 0 µF, VOUT = 5.0 V Figure 6-69. PSRR vs Frequency and VDO 80 200 mA 300 mA 10 0 10 10M IOUT 50 mA 100 mA 1 mA 10 mA 20 CIN = 0 µF, VOUT = 3.3 V, IOUT = 300 mA Power Supply Rejection Ratio (dB) COUT 4.7 PF 70 0 10 10M VIN = 4.3 V, CIN = 0 µF, VOUT = 3.3 V 1.0 PF 5 3 2 (VOUT), (PVRMS) (1.2 V), (29.6) (0.65V), (40.6) (3.3 V), (75.8) (5.0 V), (110.4) 1 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 100 1k 10k 100k Frequency (Hz) 1M VIN = 6 V, CIN = 0 µF, VOUT = 5.0 V, IOUT = 300 mA Figure 6-71. PSRR vs Frequency and COUT 10M 0.005 10 100 1k 10k 100k Frequency (Hz) 1M 10M VIN = VOUT(nom) + 1 V, IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz Figure 6-72. Output Noise vs Frequency and VOUT Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 19 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 10 (CFF (nF)), (PVRMS) (Open), (75.8) (1), (62.3) (4.7), (54.7) (10), (49.7) (100), (37.6) 0.1 0.05 0.03 0.02 1 0.5 0.2 0.1 0.05 0.02 0.01 0.01 0.005 10 0.005 10 100 1k 10k 100k Frequency (Hz) 1M 10M VIN = 4.3 V, VOUT = 3.3 V, IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz 10k 100k Frequency (Hz) 1M 10M Figure 6-74. Output Noise vs Frequency and CFF 40 8 40 7 20 7 20 6 0 6 0 5 -20 5 -20 4 -40 VIN VEN 3 VOUT IIN -60 2 -80 1 0 -1 0 0.1 0.2 0.3 0.4 0.5 0.6 Time (ms) 0.7 0.8 0.9 Voltage (V) 8 Input Current (mA) Voltage (V) 1k VIN = 6 V, VOUT = 5.0 V, IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz Figure 6-73. Output Noise vs Frequency and CFF 4 -40 VIN VEN 3 -100 1 -100 -120 0 -120 -140 -1 -140 1 0 0.3 0.4 0.5 0.6 Time (ms) 0.7 0.8 0.9 6 0 5 -80 4 -160 -240 -320 7 1 280 Input Voltage Enable Voltage 6 Voltage (V) 80 2 0.2 VIN = VEN = 5.5 V, CIN = 0 µF, COUT = 1 µF, VOUT = 5.0 V, IOUT = 0 mA Input Current (mA) Voltage (V) 160 7 VOUT IIN 0.1 Figure 6-76. Start-Up Inrush Current With COUT = 1 µF 8 VIN VEN -60 -80 Figure 6-75. Start-Up Inrush Current With COUT = 1 µF 3 VOUT IIN 2 VIN = 5.5 V, CIN = 0 µF, COUT = 1 µF, VOUT = 5.0 V, IOUT = 0 mA Output Voltage Output Current 240 5 200 4 160 3 120 2 80 1 -400 1 40 0 -480 0 0 -1 -560 0 0.1 0.2 0.3 0.4 0.5 0.6 Time (ms) 0.7 0.8 0.9 1 VIN = 5.5 V, CIN = 0 µF, COUT = 4.7 µF, VOUT = 5.0 V, IOUT = 0 mA -1 0 200 400 600 -40 800 1000 1200 1400 1600 1800 2000 Time (Ps) VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V, IOUT = 500 mA Figure 6-77. Start-Up Inrush Current With COUT = 4.7 µF 20 100 Input Current (mA) 0.5 0.3 0.2 2 Output Current (mA) 1 (CFF (nF)), (PVRMS) (Open), (110.4) (1), (91.1) (4.7), (79.2) (10), (70.7) (100), (42.1) 5 Output Voltage Noise (PV/—Hz) Output Voltage Noise (PV/—Hz) 5 3 2 Submit Document Feedback Figure 6-78. Start Up at –40°C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 6.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or 1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C 280 Input Voltage Enable Voltage 7 280 Input Voltage Enable Voltage Output Voltage Output Current 6 5 200 5 200 4 160 4 160 3 120 3 120 2 80 2 80 1 40 1 40 0 0 0 0 -1 0 200 400 600 Voltage (V) 240 Output Current (mA) Voltage (V) 6 Output Voltage Output Current -40 800 1000 1200 1400 1600 1800 2000 Time (Ps) -1 0 VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V, IOUT = 500 mA 200 400 600 240 Output Current (mA) 7 -40 800 1000 1200 1400 1600 1800 2000 Time (Ps) VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V, IOUT = 500 mA Figure 6-79. Start Up at 25°C Figure 6-80. Start Up at 150°C xx xxx xxxx xxx xxxx xxx xxxx xxx xx xxx xxxx xxx xxxx xxx xxxx xxx xx xxx xxxx xxx xxxx xxx xxxx xxx xx xxxx xxx xxxx xxx xxxx xxx xx 5 2 1 0.5 ESR (:) OFF ON -50 -25 0 25 50 75 100 125 Temperature (qC) 150 175 VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V, IOUT = 500 mA 200 0.2 0.1 0.05 Stable region 0.02 0.01 0.005 0.002 0.001 0.0005 0.5 x 1 2 3 4 5 67 10 20 30 50 70100 COUT (PF) x 200 500 COUT denotes nominal capacitor size (not effective capacitance) Figure 6-81. Thermal Shutdown Activation Figure 6-82. ESR vs COUT Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 21 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 7 Detailed Description 7.1 Overview The TPS784-Q1 is an ultra low-dropout, high PSRR, high-accuracy linear voltage regulator that is optimized for excellent transient performance. These characteristics make the device ideal for most automotive applications. This regulator offers foldback current limit, output enable, active discharge, undervoltage lockout (UVLO), and thermal protection. 7.2 Functional Block Diagrams Current Limit IN OUT 1.2-V Bandgap ± 120 Ÿ + UVLO FB Internal Controller Thermal Shutdown GND EN Figure 7-1. Adjustable Version Block Diagram Current Limit IN 1.2-V Bandgap OUT 2.18 M ± 120 Ÿ + UVLO 2.42 M 550 k Internal Controller Thermal Shutdown GND EN Figure 7-2. Fixed Version Block Diagram 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 7.3 Feature Description 7.3.1 Foldback Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table. For this device, VFOLDBACK = 0.4 × VOUT(NOM). The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brickwall current limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application report. Figure 7-3 shows a diagram of the foldback current limit. VOUT Brickwall VOUT(NOM) VFOLDBACK Foldback IOUT 0V 0 mA ISC IRATED ICL Figure 7-3. Foldback Current Limit 7.3.2 Output Enable The enable pin (EN) is active high. Enable the device by forcing the voltage of the enable pin to exceed the minimum EN pin high-level input voltage (see the Electrical Characteristics table). Turn off the device by forcing the voltage of the enable pin to drop below the maximum EN pin low-level input voltage (see the Electrical Characteristics table). If shutdown capability is not required, connect EN to IN. This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the output voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 23 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 7.3.3 Active Discharge The device has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin. Do not rely on the active discharge circuit to discharge the output voltage after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device, especially when a large output capacitor is used. Limit reverse current to no more than 5% of the device rated current for a short period of time. 7.3.4 Undervoltage Lockout (UVLO) Operation The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure 7-4 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts: • • • • • • • Region A: The device does not start until the input reaches the UVLO rising threshold. Region B: Normal operation, regulating device. Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output may fall out of regulation but the device remains enabled. Region D: Normal operation, regulating device. Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows. Region F: Normal operation followed by the input falling to the UVLO falling threshold. Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The output falls because of the load and active discharge circuit. UVLO Rising Threshold UVLO Hysteresis VIN C VOUT tAt tBt tDt tEt tFt tGt Figure 7-4. Typical UVLO Operation 7.3.5 Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. RDS(ON) = 24 VDO IRATED (1) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 7.3.6 Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed its operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 25 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 7.4 Device Functional Modes 7.4.1 Device Functional Mode Comparison The Device Functional Mode Comparison table shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. Table 7-1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) VIN < VUVLO VEN < VEN(LOW) Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device) 7.4.2 Normal Operation The device regulates to the nominal output voltage when the following conditions are met: • • • The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) • The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold 7.4.3 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. 7.4.4 Disabled The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Recommended Capacitor Types The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. 8.1.2 Input and Output Capacitor Requirements The device requires an input capacitor of 1.0 µF or larger as specified in the Recommended Operating Conditions table for stability. A higher value capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. The device also requires an output capacitor of 1.0 µF or larger as specified in the Recommended Operating Conditions table for stability. Dynamic performance of the device is improved by using a higher capacitor than the minimum output capacitor. 8.1.3 Adjustable Device Feedback Resistors The device requires external feedback divider resistors to set the output voltage. Figure 8-1 shows how the output voltage of an adjustable device can be configured from 1.2 V to 5.5 V by using a resistor divider network. Feed-Forward capacitor CFF is not required for stability (Optional) VIN OUT IN VOUT CFF CIN COUT R1 TPS784-Q1 FB GND EN GND R2 VEN GND Figure 8-1. Adjustable Operation Equation 2 calculates the values of the R1 and R2 resistors to set the output voltage: VOUT = VFB × (1 + R1 / R2) + IFB × R1 (2) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 27 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 To disregard the effect of the FB pin current error term in Equation 2 and to achieve best accuracy, choose R2 to be equal to or smaller than 550 kΩ so that the current flowing through R1 and R2 is at least 100 times larger than the IFB current listed in the Electrical Characteristics table. Lowering the value of R2 increases the immunity against noise injection. Increasing the value of R2 reduces the quiescent current for achieving higher efficiency at low load currents. Equation 3 calculates the setting that provides the maximum feedback divider series resistance. (R1 + R2) ≤ VOUT / (IFB × 100) (3) 8.1.4 Load Transient Response The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 8-2 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state. tAt tCt tDt B tEt tGt tHt F Figure 8-2. Load Transient Waveform During transitions from a light load to a heavy load, the: • • • • Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B) Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation (region C) Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F) Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor (region G) A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor. 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 8.1.5 Exiting Dropout Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up. As with other LDOs, the output can overshoot on recovery from these conditions. A ramping input supply causes an LDO to overshoot on start-up, as shown in Figure 8-3, when the slew rate and voltage levels are in the correct range. Use an enable signal to avoid this condition. Input Voltage Response time for LDO to get back into regulation. Load current discharges output voltage. VIN = VOUT(nom) + VDO Voltage Output Voltage Dropout VOUT = VIN - VDO Output Voltage in normal regulation. Time Figure 8-3. Start-Up Into Dropout Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to the correct voltage for proper regulation. Figure 8-4 illustrates what is happening internally with the gate voltage and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS) is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If these transients are not acceptable, then continue to add input capacitance in the system until the transient is slow enough to reduce the overshoot. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 29 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 Transient response time of the LDO Input Voltage Voltage Dropout VOUT = VIN - VDO Output Voltage Load current discharges output voltage VDO Output Voltage in normal regulation Time VGS voltage (pass device fully off) Input Voltage VGS voltage for normal operation VGS voltage for normal operation Voltage Gate Voltage VGS voltage in dropout (pass device fully on) Time Figure 8-4. Line Transients From Dropout 8.1.6 Dropout Voltage The device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as (VIN – VOUT) approaches dropout operation. 8.1.7 Reverse Current As with most LDOs, excessive reverse current can damage this device. Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device as a result of one of the following conditions: • Degradation caused by electromigration • Excessive heat dissipation • Potential for a latch-up condition 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V: • If the device has a large COUT and the input supply collapses with little or no load current • The output is biased when the input supply is not established • The output is biased above the input supply If reverse current flow is expected in the application, external protection must be used to protect the device. Figure 8-5 shows one approach of protecting the device. Schottky Diode IN CIN Internal Body Diode OUT Device COUT GND Figure 8-5. Example Circuit for Reverse Current Protection Using a Schottky Diode 8.1.8 Feed-Forward Capacitor (CFF) For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report. 8.1.9 Power Dissipation (PD) Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. Use Equation 4 to approximate PD: PD = (VIN – VOUT) × IOUT (4) Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS784-Q1 allows for maximum efficiency across a wide range of output voltages. The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. According to Equation 5, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). Equation 6 rearranges Equation 5 for output current. TJ = TA + (RθJA × PD) (5) IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (6) Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 31 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 of the planes. The RθJA recorded in the Recommended Operating Conditions table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the VSON package junction-to-case (bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper. 8.1.9.1 Estimating Junction Temperature The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 7 and are given in the Recommended Operating Conditions table. ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD (7) where: • • • PD is the power dissipated as explained in Equation 4 TT is the temperature at the center-top of the device package, and TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge 8.1.9.2 Recommended Area for Continuous Operation The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-6 and can be separated into the following parts: • • • • 32 Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level. See the Dropout Voltage section for more details. The rated output currents limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification. The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating causes the device to fall out of specification and reduces long-term reliability. – The shape of the slope is given by Equation 6. The slope is nonlinear because the maximum rated junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN – VOUT increases the output current must decrease. The rated input voltage range governs both the minimum and maximum of VIN – VOUT. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 Output current (A) Figure 8-6 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a RθJA as given in the Recommended Operating Conditions table. Output current limited by dropout Rated output current Output current limited by thermals Limited by maximum VIN Limited by minimum VIN VIN ± VOUT (V) Figure 8-6. Region Description of Continuous Operation Regime 8.1.9.3 Power Dissipation versus Ambient Temperature Figure 8-7 is based off of a JESD51-7 four-layer high-K board. The allowable power dissipation was estimated using the following equation. As disscussed in the An empirical analysis of the impact of board layout on LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%. 6# + 4à,# T 2& Q 150 °% (8) Maximum Power Dissipation (W) 1.6 DRB Package DBV Package 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 Ambient Temerature (qC) 100 120 140 Figure 8-7. Allowable Power Dissipation Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 33 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 8.2 Typical Application VIN IN VOUT OUT IN COUT OUT CIN COUT DC/DC Converter TPS784-Q1 GND GND EN GND GND VEN GND GND Figure 8-8. Operation From a DC/DC Converter 8.2.1 Design Requirements Table 8-1 summarizes the design requirement for this application. Table 8-1. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 3.8 V Output voltage 3.3 V, ±1.5% Output load 100 mA Output capacitor 10 µF Maximum ambient temperature 85°C 8.2.2 Detailed Design Procedure For this design example, the 3.3-V, fixed-version device is selected. The device is powered of a DC/DC converter connected to a battery. A 500-mV headroom between VIN and VOUT is used to keep the device within the dropout voltage specification and to ensure the device stays in regulation under all load and temperature conditions for this design. 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 8.2.3 Application Curves A 10-µF capacitor is used to reduce overshoot and undershoot of output voltage during load transients with ramps rates greater than 0.5 A/µs. Figure 8-9 and Figure 8-10 show captures of load transient behavior for this application. 800 20 700 10 600 0 500 -10 400 -20 300 -30 200 -40 100 -50 0 50 100 150 200 250 300 Time (Ps) 350 400 450 0 500 VIN = 3.8 V, VOUT = 3.3 V, COUT = 10 µF, IOUT slew rate = 1 A/µs 1000 VOUT IOUT 900 40 30 800 20 700 10 600 0 500 -10 400 -20 300 -30 200 -40 Output Current (mA) 30 50 AC-Coupled Output Voltage (mV) 1000 VOUT IOUT 900 40 Output Current (mA) AC-Coupled Output Voltage (mV) 50 100 -50 0 100 200 300 400 500 600 Time (Ps) 700 800 0 900 1000 VIN = 3.8 V, VOUT = 3.3 V, COUT = 10 µF, IOUT slew rate = 1 A/µs Figure 8-9. IOUT Transient From 0 mA to 100 mA Figure 8-10. IOUT Transient From 1 mA to 100 mA 9 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 1.65 V to 6.0 V. The input supply must be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. TI requires using a 1-µF or greater input capacitor to reduce the impedance of the input supply, especially during transients. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 35 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 10 Layout 10.1 Layout Guidelines • • • • Place input and output capacitors as close to the device as possible. Use copper planes for device connections in order to optimize thermal performance. Place thermal vias around the device to distribute the heat. Only place tented thermal vias directly beneath the thermal pad of the DRB package. An untented via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad. 10.1.1 Additional Layout Considerations 110 1oz PCB 2oz PCB 100 90 80 70 60 50 40 30 20 0 20 40 60 PCB Copper Area (cm ) 80 100 Junction-to-ambient thermal resistance (RTJA) (qC/W) Junction-to-ambient thermal resistance (RTJA) (qC/W) The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers and microprocessors); these capacitively-coupled signals may produce undesirable output voltage transients. In these cases, TI recommends using a fixed-voltage version of the device, or isolating the FB node by placing a copper ground plane on the layer directly underneath the LDO circuitry and FB pin to minimize any undesirable signal coupling. 110 1oz PCB 2oz PCB 100 90 80 70 60 50 40 30 20 0 20 4-layer PCB 1oz PCB 2oz PCB 35 30 25 20 15 40 60 PCB Cuppoer Area (cm ) 80 100 40 1oz PCB 2oz PCB 35 30 25 20 15 0 4-layer PCB 10 20 30 40 50 60 70 PCB Copper Area (cm ) 80 90 100 2-layer PCB Figure 10-3. Junction-to-Board Characterization Parameter (ψJB) vs PCB Copper Area 36 100 Figure 10-2. Junction-to-Ambient Thermal Resistance (RθJA) vs PCB Copper Area Junction-to-board characterization parameter (\JB) (qC/W) Junction-to-board characterization parameter (\JB) (qC/W) 40 20 80 2-layer PCB Figure 10-1. Junction-to-Ambient Thermal Resistance (RθJA) vs PCB Copper Area 0 40 60 PCB Copper Area (cm ) Figure 10-4. Junction-to-Board Characterization Parameter (ψJB) vs PCB Copper Area Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 10.2 Layout Examples COUT CFF R1 R2 COUT CIN OUT 1 8 IN FB 2 7 NC 3 NC 4 CIN OUT 1 8 IN EN NC 2 7 EN 6 NC NC 3 6 NC 5 GND NC 4 5 GND GND PLANE GND PLANE Represents a thermal via Represents a thermal via Figure 10-5. Layout Example for the DRB Package Adjustable Version CIN Figure 10-6. Layout Example for the DRB Package Fixed Version CIN COUT IN 5 1 GND 5 2 EN 5 3 5 5 OUT R1 CFF 4 FB 5 COUT IN 5 1 GND 5 2 EN 5 3 5 5 4 5 OUT NC R2 GND PLANE GND PLANE Figure 10-7. Layout Example for the DBV Package Adjustable Version Figure 10-8. Layout Example for the DBV Package Fixed Version Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 37 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature Table 11-1. Device Nomenclature (1) (2) PRODUCT(1) (2) VOUT TPS784xx(x)Pyyyz xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V). P indicates an active output discharge feature. All members of the TPS784-Q1 family actively discharge the output when the device is disabled. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. Output voltages from 0.65 V to 5.5 V in 50-mV increments are available. Contact the factory for details and availability. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Texas Instruments, Universal Low-Dropout (LDO) Linear Voltage Regulator MultiPkgLDOEVM-823 Evaluation Module user's guide • Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report • Texas Instruments, An empirical analysis of the impact of board layout on LDO thermal performance application report 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary 38 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 TPS784-Q1 www.ti.com SBVS387B – FEBRUARY 2020 – REVISED APRIL 2021 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS784-Q1 39 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS78401QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23JF TPS78401QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8401WQ TPS784075QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 84075W TPS78408QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 2BGF TPS784105QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 84105W TPS78410QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8410WQ TPS78411QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8411WQ TPS78412QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23KF TPS78412QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8412WQ TPS78415QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23LF TPS78415QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8415WQ TPS78417QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 2BHF TPS78418QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23MF TPS78418QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8418WQ TPS78425QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23NF TPS78425QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8425WQ TPS78428QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23OF TPS78429QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23PF TPS78430QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23QF TPS78430QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8430WQ Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 20-Aug-2021 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS78433QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 23RF TPS78433QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8433WQ TPS78450QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 2BIF TPS78450QWDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 8450WQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of