TPS92315
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SNVS904A – NOVEMBER 2012 – REVISED FEBRUARY 2013
Off-Line Primary-Side Sensing Controller
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FEATURES
DESCRIPTION
•
The TPS92315 flyback power supply controller
provides isolated output current regulation without the
use of an optical coupler. The devices process
operating information from the primary power switch
and an auxiliary flyback winding to provide precise
output current control. Low start-up current,
dynamically controlled operating states and a tailored
modulation profile support very low stand-by power
without sacrificing start-up time or output transient
response.
1
•
•
•
•
•
•
•
•
Primary-Side Regulation (PSR) eliminates
opto-coupler
±5% LED current regulation
130 kHz maximum switching frequency
enables high power density SSL drivers
designs
Quasi-resonant valley switching operation for
highest overall efficiency
Patent-pending frequency jitter scheme to
ease EMI compliance
Wide VCC range (35V) allows small bias
capacitor
Drive output for MOSFET
Protection functions: over-voltage, low-line,
and over-current
SOT23-6 package
Control algorithms in the TPS92315 allow operating
efficiencies to meet or exceed applicable standards.
The drive output interfaces to a FET power switch.
Discontinuous Conduction Mode (DCM) with valley
switching is used to reduce switching losses. A
combination of switching frequency and peak primary
current amplitude modulation is used to keep
conversion efficiency high across the full load and
input voltage range.
The controller has a maximum switching frequency of
130 kHz and always maintains control of the peak
primary current in the transformer. Protection features
help keep secondary and primary component stress
levels in check across the operation range.
APPLICATIONS
•
•
LED lighting driver applications
Small form factor LED light bulbs (E14, GU-10)
SIMPLIFIED APPLICATION DIAGRAM
85-264VAC
TPS92315
VCC
GATE
ISNS
VSNS
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS92315
SNVS904A – NOVEMBER 2012 – REVISED FEBRUARY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
(2) (3)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
Input voltage range
UNIT
MAX
VCC
38
Continuous gate current sink IGATE
50
Continuous gate current
source
IGATE
Self-limiting
Peak VSNS pin current
IVSNS
-1.2
Gate-drive voltage at GATE
IGATE
-0.5
Self-limiting
VSNS
–0.75
7
ISNS
–0.5
5
Voltage range
Electrostatic discharge
Human body model (HBM) QSS 009-105 (JESD22-A114A)
2000
Charged device model (CDM) QSS 009-147 (JESD22-C101B.01)
500
Junction temperature range, TJ
-55
150
Storage temperature range, Tstg
-65
150
Lead temperature 0.6 mm from case for 10 seconds
(1)
(2)
(3)
V
mA
V
V
°C
260
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
VCC
Bias supply operating voltage
CVCC
VCC bypass capacitor
RLC
ISNS pin line compensation programming resistor
0
kΩ
IVSNS
VSNS pin current
-1
mA
TJ
Operating junction temperature
2
9
35
V
0.047
1
µF
−20
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125
°C
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SNVS904A – NOVEMBER 2012 – REVISED FEBRUARY 2013
THERMAL INFORMATION
TPS92315
THERMAL METRIC (1)
DBV
UNITS
6 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
180.0
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
44.4
ψJT
Junction-to-top characterization parameter (5)
5.1
ψJB
Junction-to-board characterization parameter (6)
43.8
(1)
(2)
(3)
(4)
(5)
(6)
71.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VCC = 25V, -20°C ≤ TA ≤ 125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Bias Supply Input
IRUN
Supply current, run
IGATE = 0, run state
2.1
3.0
ISTART
Supply current, start
VVCC = 18V, IGATE = 0, start state
1.0
3.0
mA
µA
IFAULT
Supply current, fault
IGATE = 0, fault state
2.1
2.8
mA
Under-Voltage Lockout
VVCCON
VCC turn-on threshold
VVCC low to high
18
21
24
VVCCOFF
VCC turn-off threshold
VVCC high to low
7.70
8.10
8.45
VVSNSR
Regulating level
Measured at no-load condition, TJ = 25°C
4.0
4.05
4.1
V
VVSNSNC
Negative clamp level
IVSNS = -300 µA, volts below ground
190
250
325
mV
IVSNSB
Input bias current
VVSNS = 4V
-0.5
0
0.5
µA
VISNSTMAX
Max ISNS threshold voltage
VVSNS = 3.7V (1)
715
750
775
VISNSTMIN
Min ISNS threshold voltage
VVSNS = 4.35V (1)
230
250
270
KAM
AM control ratio
VISNSTMAX / VISNSTMIN
2.75
3.0
3.15
V/V
VCCR
constant-current regulating
level
CC regulation constant
310
319
329
mV
KLC
Line compensating current ratio
IVSNSLS = -300 µA, IVSNSLS / current out of
ISNS pin
23
25
28
A/A
TISNSLEB
Leading-edge blanking time
GATE output duration, VISNS = 1 V
195
235
275
ns
IGATE
GATE source current
VGATE = 8V, VVCC = 9V
20
25
RGATELS
GATE low-side drive resistance IGATE = 10 mA
VGATECL
GATE clamp voltage
RGATESS
GATE pull-down in start state
V
VSNS Input
ISNS Input
mV
GATE
VVCC = 35V
150
mA
Ω
6
12
14
16
V
200
230
kΩ
Timing
FSW(max)
Maximum switching frequency
VVSNS = 3.7V (1)
120
130
140
kHz
FSW(min)
Minimum switching frequency
VVSNS = 4.35V (1)
875
1000
1100
Hz
TZTO
Zero-crossing timeout delay
1.80
2.10
2.45
µs
(1)
4
These devices automatically vary the control frequency and current sense thresholds to improve EMI performance, these threshold
voltages and frequency limits represent average levels.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VCC = 25V, -20°C ≤ TA ≤ 125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Protection
VOVP
Over-voltage threshold
At VSNS input, TJ = 25°C
4.52
4.6
4.68
VOCP
Over-current threshold
At ISNS input
1.4
1.5
1.6
IVSNSL(run)
VSNS line-sense run current
Current out of VSNS pin – increasing
190
220
260
IVSNSL(stop)
VSNS line-sense stop current
Current out of VSNS pin – decreasing
70
80
95
KVSNSL
VSNS line-sense ratio
IVSNSL(run) / IVSNSL(stop)
2.5
2.8
3.05
TJ(stop)
Thermal shut-down
temperature
Internal junction temperature
V
µA
A/A
165
°C
DEVICE INFORMATION
Functional Block Diagram
POWER
& FAULT
MANAGEMENT
UVLO
21V/8V
VCC
OC FAULT
OV FAULT
TSD
LINE FAULT
VCC
5V
GND
4.05V
25 mA
+
CONTROL
LAW
E/A
VSNS
SAMPLER
GATE
VISNS
+
VALLEY
SWITCHING
14V
1 / fSW
200k
OV FAULT
VOVP
S
Q
R
Q
CURRENT
REGULATION
VISNS
LEB
IVSNSL
LINE
SENSE
ISNS
+
SECONDARY
TIMING
DETECT
IVSNSL
10k
IVSNSL / KLC
+
LINE
FAULT
OC
FAULT
+
1.5V
2.2V / 0.80V
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DBV PACKAGE
6 PIN
(TOP VIEW)
DNC
1
6
VSNS
VCC
2
5
GND
GATE
3
4
ISNS
Table 1. TERMINAL FUNCTIONS
PIN
6
I/O
DESCRIPTION
NAME
NO.
DNC
1
—
DNC, the Do Not Connect pin is only for device testing. For all end applications, this pin should left unconnected.
VCC
2
P
VCC is the supply pin to the controller. A carefully placed bypass capacitor to GND is required on this
pin. The turn on threshold is 21V and turn off threshold is 8V.
GATE
3
O
GATE is an output used to drive the gate of an external high voltage MOSFET switching transistor. The
driver output is limited to 14V with a 25 mA current source turn on and 6Ω turn off internal resistance.
ISNS
4
I
ISNS, current sense input connects to a ground-referenced current-sense resistor in series with the
power switch. The resulting voltage is used to monitor and control the peak primary current. A series
resistor can be added to this pin to compensate the peak switch current levels as the AC-mains input
varies. The current sense voltage range is 0.25V to 0.75V for the peak primary current range.
GND
5
P
The GND pin is both the reference pin for the controller and the low-side return for the drive output.
Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and
avoid any common trace length with analog signal return paths.
VSNS
6
I
VSNS, voltage sense is an input used to provide voltage and timing feedback to the controller. This pin
is connected to a voltage divider between an auxiliary winding and GND. The value of the upper resistor
of this divider is used to program low line shutdown thresholds and compensate the current sense
threshold at the ISNS pin across the AC input range.
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Detailed Pin Description
VCC (Device Bias Voltage Supply): The VCC pin is connected to a bypass capacitor to ground and a start-up
resistance to the input bulk capacitor (+) terminal. The VCC turn-on UVLO threshold is 21 V and turn-off UVLO
threshold is 8.1 V, with an available operating range up to 35 V.
GND (Ground): This is a single ground reference external to the device for the gate drive current and analog
signal reference. Place the VCC bypass capacitor close to GND and VCC with short traces to minimize noise on
the VSNS and ISNS signal pins.
VSNS (Voltage-Sense): The VSNS pin is connected to a resistor divider from the auxiliary winding to ground.
The output-voltage feedback information is sampled at the end of the transformer secondary current
demagnetization time to provide an accurate representation of the output voltage. Timing information to achieve
valley-switching and to control the duty cycle of the secondary transformer current is determined by the
waveform on the VSNS pin. Avoid placing a filter capacitor on this input which would interfere with accurate
sensing of this waveform.
The VSNS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. This information is sensed during the
MOSFET on-time. For the AC-input run/stop function, the run threshold on VSNS is 220 µA and the stop
threshold is 80 µA. The values for the auxilliary voltage divider upper-resistor RAUX1 and lower-resistor RAUX2 can
be determined by the equations below.
VIN(run) × 2
R AUX1 =
NPA × IVSNS(run)
where
•
•
•
NPA is the transformer primary-to-auxiliary turns ratio,
VIN(run) is the AC RMS voltage to enable turn-on of the controller (run),
IVSNSL(run) is the run-threshold for the current pulled out of the VSNS pin during the MOSFET on-time. (see
ELECTRICAL CHARACTERISTICS)
R AUX 2 =
(1)
R AUX1 × VVSNSR
NAS × (VOCV + VF ) − VVSNSR
where
•
•
•
•
•
VOCV is the converter regulated output voltage
VF is the output rectifier forward drop at near-zero current
NAS is the transformer auxiliary to secondary turns ratio
RAUX1 is the VSNS divider high-side resistance
VVSNSR is the CV regulating level at the VSNS input (see ELECTRICAL CHARACTERISTICS)
(2)
GATE (Gate Drive): The GATE pin is connected to the MOSFET gate pin, usually through a series resistor. The
gate driver provides a gate-drive signal limited to 14V. The turn-on characteristic of the driver is a 25 mA current
source which limits the turn-on dv/dt of the MOSFET drain and reduces the leading-edge current spike, but still
provides gate-drive current to overcome the Miller plateau. The gate-drive turn-off current is determined by the
low-side driver RDS(on) and any external gate-drive resistance. The user can reduce the turn-off MOSFET drain
dv/dt by adding external gate resistance.
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ISNS (Current Sense): The current-sense pin is connected through a series resistor (RLC) to the current-sense
resistor (RISNS). The series resistor RLC provides the function of feed-forward line compensation to eliminate
change in IPP (primary side peak current) due to change in di/dt and the propagation delay of the internal
comparator and MOSFET turn-off time. There is an internal leading-edge blanking time of 235 ns to eliminate
sensitivity to the MOSFET turn-on current spike. It should not be necessary to place a bypass capacitor on the
ISNS pin. The value of RISNS is determined by the target output current in constant-current (CC) regulation. The
values of RISNS and RLC can be determined by the equations below. The term ηXFMR is intended to account for
the energy stored in the transformer but not delivered to the secondary. This includes transformer resistance and
core loss, bias power, and primary-to-secondary leakage ratio.
Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%,
and bias power to output power ratio of 1.5%. The ηXFMR value is approximately: 1 - 0.05 - 0.035 - 0.015 = 0.9.
V
× NPS
RISNS = CCR
× ηXFMR
2IOCC
where
•
•
•
•
RLC =
VCCR is a current regulation constant (see ELECTRICAL CHARACTERISTICS),
NPS is the transformer primary-to-secondary turns ratio (a ratio of 7 to 8 is recommended for a 9V output),
IOCC is the target output current in constant-current regulation,
ηXFMR is the transformer efficiency.
(3)
K LC × R AUX1 × RISNS × TD × NPA
LP
where
•
•
•
•
•
•
8
RAUX1 is the VSNS pin high-side resistor value,
RISNS is the current-sense resistor value,
TD is the current-sense delay including MOSFET turn-off delay, add ~50 ns to MOSFET delay,
NPA is the transformer primary-to-auxiliary turns ratio,
LP is the transformer primary inductance,
KLC is a current-scaling constant (see ELECTRICAL CHARACTERISTICS).
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TYPICAL CHARACTERISTICS
At VCC = 25 V, unless otherwise noted.
10
10
Run State, VCC = 25 V
Run State
1
IVCC - Bias Supply Current (mA)
I VCC - Bias Supply Current (mA)
1
0.1
Wait State
0.01
VCC Turn ON
VCC Turn OFF
0.001
Wait State, VCC = 25 V
0.1
0.01
0.001
Start State, VCC = 18 V
0.0001
Start State
0.0001
-25
0.00001
0
5
10
15
20
25
30
0
35
25
50
TJ - Temperature
75
100
125
(o C)
VCC - Bias Supply Voltage (V)
Figure 1. Bias Supply Current vs. Bias Supply Voltage
Figure 2. Bias Supply Current vs. Temperature
4.10
300
250
VSNS Line Sense Current (µA)
VVSNSR - VSNS Regulation Voltage (V)
4.08
4.06
4.04
4.02
4.00
I VSNSL(run)
200
150
100
I VSNSL(stop)
50
3.98
0
3.96
-25
0
25
50
75
100
125
-25
0
25
50
TJ - Temperature
TJ - Temperature (oC)
Figure 3. VSNS Regulation Voltage vs. Temperature
75
100
125
(o C)
Figure 4. Line-Sense Current vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
At VCC = 25 V, unless otherwise noted.
330
VCCR - Constatnt Current Regulating Level (mA)
V ISNSTMIN - Minimum ISNS Threshold Voltage (mV)
270
265
260
255
250
245
240
235
230
325
320
315
310
-25
0
25
50
75
100
125
-25
0
TJ - Temperature (o C)
25
50
TJ - Temperature
Figure 5. Minimum ISNS Threshold Voltage vs. Temperature
75
100
125
(o C)
Figure 6. Constant-Current Regulating Level vs.
Temperature
1100
34
VGATE = 8V, VVCC = 9V
32
I GATE - GATE Source Current (mA)
FSW(min) - Minimum Switching Frequency (Hz)
1075
1050
1025
1000
975
950
925
28
26
24
22
900
20
875
-25
0
25
50
TJ - Temperature
75
100
125
-25
0
(o C)
25
50
TJ - Temperature
Figure 7. Minimum Switching Frequency vs. Temperature
10
30
75
100
125
(o C)
Figure 8. GATE Source Current vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
VOVP - VSNS Over-Voltage Threshold (V)
At VCC = 25 V, unless otherwise noted.
Figure 9. Over-Voltage Threshold vs. Temperature
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FUNCTIONAL DESCRIPTION
The TPS92315 is a flyback power supply controller which provides accurate voltage and constant current
regulation with primary-side feedback, eliminating the need for opto-coupler feedback circuits. The controller
operates in discontinuous conduction mode with valley-switching to minimize switching losses. The modulation
scheme is a combination of frequency and primary peak current modulation to provide high conversion efficiency
across the load range.
Another feature beneficial to achieve low quescient power without excessive start-up time is a wide operating
VCC range to allow a high-value VCC start-up resistance and low-value VCC capacitance. During low-power
operating ranges the device has power management features to reduce the device operating current at operating
frequencies below 44 kHz. The TPS92315 controller includes features in the modulator to reduce the EMI peak
energy of the fundamental switching frequency and harmonics. Accurate voltage and constant current regulation,
fast dynamic response, and fault protection are achieved with primary-side control. A complete LED driver
solution can be realized with a straightforward design process, low cost and low component count.
Primary-Side Voltage Regulation
Figure 10 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown.
The power train operation is the same as any DCM flyback circuit but accurate output voltage and current
sensing is the key to primary-side control.
Timing
IS
Bulk Voltage - VBULK
Primary
+ VF -
Secondary
VOUT
COUT
Auxiliary
RAUX1
VSNS
RAUX2
Discriminator
& Sampler
Zero Crossings
VCL
Control
Law
GD
GATE
־
Minimum
Period
And Peak
Primary
Current
ISNS
RISNS
Figure 10. Simplified Flyback Convertor
(with the main voltage regulation blocks)
In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer
energy to the secondary. As shown in Figure 11 it is clear there is a down slope representing a decreasing total
rectifier VF and resistance voltage drop (ISRS, where IS and RS are the current and equivalent resistance of the
secondary winding) as the secondary current decreases to zero. To achieve an accurate representation of the
secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage inductance reset
and ringing, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and
captures the error signal at the time the secondary winding reaches zero current. The internal reference on
VSNS is 4.05 V; the resistor divider is selected as outlined in the VSNS pin description.
12
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VSNS Sample
(VOUT + VF + ISRS) NA / NS
0V
(VBULK) NA / NP
Figure 11. Auxiliary Winding Voltage
The TPS92315 VSNS signal sampler includes signal discrimination methods to ensure an accurate sample of the
output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to
ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any
subsequent leakage inductance ring. Refer to Figure 12 below for a detailed illustration of waveform criteria to
ensure a reliable sample on the VSNS pin. The first detail to examine is the duration of the leakage inductance
reset pedestal, TLK_RESET in Figure 12. Since this can mimic the waveform of the secondary current decay,
followed by a sharp downslope, it is important to keep the leakage reset time less than 500 ns for IPRI minimum,
and less than 1.5 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform
following TLK_RESET. The peak-to-peak voltage at the VSNS pin should be less than approximately 100 mVp-p at
least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it
usually occurs during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on VSNS is
scaled up to the auxiliary winding voltage by RAUX1 and RAUX2, and is equal to 100 mV x (RAUX1 + RAUX2) / RAUX2.
TLK_RESET
TSMPL
VSNS ring p-p
TDM
Figure 12. Auxiliary Waveform Details
During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode
as illustrated in Figure 13 below. The internal operating frequency limits of the device are 130 kHz maximum and
1 kHz minimum. The transformer primary inductance and primary peak current chosen sets the maximum
operating frequency of the converter. The output preload resistor and efficiency at low power determines the
converter minimum operating frequency. There is no stability compensation required for the TPS92315 controller.
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Control Law Profile in Constant Voltage (CV) Mode
130 kHz
IPP (peak primary current)
fSW (1 / MINP)
IPP(max)
IPP
fSW
44 kHz
FM
AM
IPP(max) / 3
FM
fSW(min) = 1kHz
4.4 kHz
0.75 V 1.3 V
2.2 V
3.55 V
5V
Control Voltage, E/A Output - VCL
Figure 13. Frequency and Amplitude Modulation Modes
(during voltage regulation)
Primary-Side Current Regulation
Timing information at the VSNS pin and current information at the ISNS pin allow accurate regulation of the
secondary average current. The control law dictates that as power is increased in CV regulation and approaching
CC regulation the primary-peak current is at IPP(max). Referring to Figure 14 below, the primary-peak current,
turns ratio, secondary demagnetization time (tDM), and switching period (TSW) determine the secondary average
output current. Ignoring leakage inductance effects, the average output current is given by Equation 5. When the
average output current reaches the regulation reference in the current control block, the controller operates in
frequency modulation mode to control the output current at any output voltage at or below the voltage regulation
target as long as the auxiliary winding can keep VCC above the UVLO turn-off threshold.
IPP
tON
IS NS NP
tDM
TSW
Figure 14. Transformer Currents
IOUT =
14
IPP NP t DM
×
×
2 NS TSW
(5)
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Output Voltage VOUT
VOCV
Output Current IOUT IOCC
Figure 15. Typical Target Output V-I Characteristic
Valley-Switching
The TPS92315 utilizes valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI, and
to minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all load
conditions unless the VDS ringing has diminished.
Referring to Figure 16 below, the TPS92315 operates in a valley-skipping mode in most load conditions to
maintain an accurate voltage or current regulation point and still switch on the lowest available VDS voltage.
VDS
VGATE
Figure 16. Valley-Skipping Mode
Start-Up Operation
Upon application of input voltage to the converter, the start-up resistor connected to VCC from the bulk capacitor
voltage (VBULK) charges the VCC capacitor. During charging of the VCC capacitor the device bias supply current
is less than 1.5 µA. When VCC reaches the 21V UVLO turn-on threshold, the controller is enabled and the
converter starts switching. The initial three cycles are limited to IPP(min). This allows sensing any initial input or
output faults with minimal power delivery. After the initial three cycles at minimum IPP(min), the controller responds
to the condition dictated by the control law. The converter remains in discontinuous mode during charging of the
output capacitor(s), maintaining a constant output current until the output voltage is in regulation.
Fault Protection
There is comprehensive fault protection incorporated into the TPS92315. Protection functions include:
• Output Over Voltage
• Input Under Voltage
• Internal Over Temperature
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Primary Over-current fault
ISNS pin fault
VSNS pin fault
An UVLO reset and restart sequence applies for all fault protection events.
The output over-voltage function is determined by the voltage feedback on the VSNS pin. If the voltage sample
on VSNS exceeds 115% of the nominal VOUT, the device stops switching and keeps the internal circuitry enabled
to discharge the VCC capacitor to the UVLO turn-off threshold. After that, the device returns to the start state and
a start-up sequence ensues.
The TPS92315 always operates with cycle-by-cycle primary peak current control. The normal operating range of
the ISNS pin is 0.75V to 0.25V. There is additional protection if the ISNS pin reaches 1.5V. This results in a
UVLO reset and restart sequence. There is no leading-edge blanking on the 1.5V threshold on ISNS.
The line input run and stop thresholds are determined by current information at the VSNS pin during the
MOSFET on-time. While the VSNS pin is clamped close to GND during the MOSFET on-time, the current
through RAUX1 is monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and
stop thresholds allows clean start-up and shut-down of the power supply with the line voltage. The run current
threshold is 220 µA and the stop current threshold is 80 µA.
The internal over-temperature protection threshold is 165°C. If the junction temperature reaches this threshold
the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VSNS pin. If complete loss of feedback
information on the VSNS pin occurs, the controller stops switching and restarts.
16
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DESIGN PROCEDURE
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
TPS92315 family of controllers. Refer to the Figure 17 for component names and network locations. The design
procedure equations use terms that are defined below.
L1
DOUT
LED+
ZD1
CIN2
CIN1
T1
CIN3
R1
D1
LP
D2
LS
3–4
LEDs
COUT
85-264VAC
DVCC
LAUX
RAUX1
CVCC
LED-
RAUX2
CY
Q1
TPS92315
VCC
GATE
RLC
ISNS
VSNS
GND
RISNS
Figure 17. Design Procedure Application Example
Definition of Terms
Capacitance Terms in Farads
• CBULK: total input capacitance of CIN1, CIN2 and CIN3.
• CVCC: minimum required capacitance on the VCC pin.
• COUT: minimum output capacitance required.
Duty Cycle Terms
• DMAGCC: secondary diode conduction duty cycle in CC, 0.425.
• DMAX: MOSFET maximum on-time duty cycle.
Frequency Terms in Hertz
• fLINE: minimum line frequency.
• fMAX: target full-load maximum switching frequency of the converter.
• fMIN: minimum switching frequency of the converter, add 15% margin over the fSW(min) limit of the device.
• fSW(min): minimum switching frequency (see ELECTRICAL CHARACTERISTICS).
Current Terms in Amperes
• IOCC: converter output constant-current target.
• IPP(max): maximum transformer primary current.
• ISTART: start-up bias supply current (see ELECTRICAL CHARACTERISTICS).
• ITRAN : required positive load-step current.
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IVSNSL(run): VSNS pin run current (see ELECTRICAL CHARACTERISTICS).
Current and Voltage Scaling Terms
• KAM: maximum-to-minimum peak primary current ratio (see ELECTRICAL CHARACTERISTICS).
• KLC: current-scaling constant (see ELECTRICAL CHARACTERISTICS).
Transformer Terms
• LP: transformer primary inductance.
• NAS: transformer auxiliary-to-secondary turns ratio.
• NPA: transformer primary-to-auxiliary turns ratio.
• NPS: transformer primary-to-secondary turns ratio.
Power Terms in Watts
• PIN: converter maximum input power.
• POUT: full-load output power of the converter.
• PR1: VCC start-up resistor power dissipation.
Resistance Terms in Ω
• RISNS: primary current programming resistance.
• RESR: total ESR of the output capacitor(s).
• RAUX1: high-side VSNS pin resistance.
• RAUX2: low-side VSNS pin resistance.
• R1: maximum start-up resistance to achieve the turn-on time target.
Timing Terms in Seconds
• TD: current-sense delay including MOSFET turn-off delay; add 50 ns to MOSFET delay.
• TDMAG(min): minimum secondary rectifier conduction time.
• TON(min): minimum MOSFET on time.
• TR: the reciprocal of resonant frequency during the DCM (discontinuous conduction mode) operation.
• TSTR: converter start-up time requirement.
Voltage Terms in Volts
• VBULK: highest bulk capacitor voltage for quescient power measurement.
• VBULK(min): minimum voltage on CB1 and CB2 at full power.
• VCCR: constant-current regulating voltage (see ELECTRICAL CHARACTERISTICS).
• VISNSTMAX: ISNS pin maximum current-sense threshold (see ELECTRICAL CHARACTERISTICS).
• VISNSTMIN: ISNS pin minimum current-sense threshold (see ELECTRICAL CHARACTERISTICS).
• VVCCOFF: UVLO turn-off voltage (see ELECTRICAL CHARACTERISTICS).
• VVCCON: UVLO turn-on voltage (see ELECTRICAL CHARACTERISTICS).
• VOΔ: output voltage drop allowed during the load-step transient.
• VDSPK: peak MOSFET drain-to-source voltage at high line.
• VF: secondary rectifier forward voltage drop at near-zero current.
• VFA: auxiliary rectifier forward voltage drop.
• VLK: estimated leakage inductance energy reset voltage.
• VOCV: pre-set output voltage of the converter.
• VOUT: LED string voltage.
• VOCC: target lowest converter output voltage in constant-current regulation.
• VREV: peak reverse voltage on the secondary rectifier.
• VRIPPLE: output peak-to-peak ripple voltage at full-load.
• VVSNSR: CV regulating level at the VSNS input (see ELECTRICAL CHARACTERISTICS).
18
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AC Voltage Terms in VRMS
• VIN(max): maximum input voltage to the converter.
• VIN(min): minimum input voltage to the converter.
• VIN(run): converter input start-up (run) voltage.
Efficiency Terms
• ηSB: estimated efficiency of the converter at no-load condition, not including start-up resistance or bias losses.
For a E14 or GU-10 application, 70% to 75% is a good initial estimate.
• η: converter overall efficiency.
• ηXFMR: transformer primary-to-secondary power transfer efficiency.
Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input capacitance, CIN1 and CIN2 total, in order to determine the maximum
Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target.
V
×I
PIN = OCV OCC
η
(6)
The below equation provides an accurate solution for input capacitance based on a target minimum bulk
capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the
target capacitance.
CBULK
VBULK (min)
1
× arcsin
2PIN × 0.25 +
2×V
2π
IN(min)
=
2
2
2VIN(min) − VBULK(min) × fLINE
(
)
(7)
Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.
Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on
target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have
an estimate from previous designs. For the transition mode operation limit, the period required from the end of
secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs
assuming 500 kHz resonant frequency. DMAX can be determined using the equation below.
T
DMAX = 1 − R × fMAX − DMAGCC
2
(8)
Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation
below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It
is set internally by the TPS92315 at 0.425. The total voltage on the secondary winding needs to be determined;
which is the sum of VOCV and the secondary rectifier VF. For the E14 or GU-10 applications with VOUT of around
10V at an IOCC of 350 mA, a turns ratio range of 7 to 8 is typically used.
DMAX × VBULK(min)
NPS(max) =
DMAGCC × (VOCV + VF )
(9)
Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following
parameters.
The TPS92315 controller constant-current regulation is achieved by maintaining a maximum DMAG (the
secondary diode conduction duty cycle) of 0.425 at the maximum primary current setting. The transformer turns
ratio and constant-current regulating voltage determine the current sense resistor for a target constant current.
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Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term
is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias
power ratio to rated output power. For a typical E14 or GU-10 application, bias power of 1.5% is a good estimate.
An overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and
winding loss, and 1.5% bias power.
V
× NPS
RISNS = CCR
× ηXFMR
2IOCC
(10)
The primary transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency and output current and transformer power losses
are included in the equation below. Initially determine transformer primary current.
Primary current is simply the maximum current sense threshold divided by the current sense resistance.
V
IPP(max) = ISNSTMAX
RISNS
LP =
(11)
2( VOCV + VF ) × IOCC
2
η XFMR × IPP
(max) × fMAX
(12)
The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target
operating output voltage in constant-current regulation and the VVCCOFF of the TPS92315. There is additional
energy supplied to VCC from the transformer leakage inductance energy which allows a lower turns ratio to be
used in many designs.
V
+ VFA
NAS = VCCOFF
VOCC + VF
(13)
Transformer Parameter Verification
The transformer turns ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these
should be reviewed. The TPS92315 controller requires a minimum on time of the MOSFET (TON) and minimum
DMAG time (TDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of FMAX, LP
and RISNS affects the minimum TON and TDMAG.
The secondary rectifier and MOSFET voltage stress can be determined by the equations below.
VREV =
VIN(max) × 2
NPS
+ VOCV
(14)
For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.
(
)
VDSPK = VIN(max) × 2 + (VOCV + VF ) × NPS + VLK
(15)
The following equations are used to determine if the minimum TON target of 300 ns and minimum TDMAG target of
1.1 µs is achieved.
IPP(max) × VISNSTMIN
LP
×
TON(min) =
VISNSTMAX
VIN(max) × 2
(
TDMAG(min) =
)
(16)
TON(min) × VIN(max) × 2
NPS × ( VOCV + VF )
(17)
Output Capacitance
The output capacitance value is typically determined by the current ripple requirement of the LED current. For
example, some E14 or GU-10 applications requires the current ripple to be 30% of the LED current. Then the
equation below assumes that the switching frequency can be at the TPS92315 minimum of fSW(min).
20
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COUT
1
+ 150 µs
0.3 × IS
fSW (min)
=
VO∆
(18)
Another consideration of the output capacitor(s) is the ripple voltage requirement which is reviewed based on
secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation
below.
V
× 0.8
RESR = RIPPLE
IPP(max) × NPS
(19)
VCC Capacitance, CVCC
The capacitance on VCC needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain
the voltage to the TPS92315. The total output current available to the load and to charge the output capacitors is
the constant-current regulation target. The equation below assumes the output current of the flyback is available
to charge the output capacitance until the minimum output voltage is achieved. There is an estimated 1 mA of
gate-drive current in the equation and 1V of margin added to VCC.
C
×C
(IRUN + 1mA ) × OUT OCC
IO
C VCC =
(VVCCON − VVCCOFF ) − 1V
(20)
VCC Start-Up Resistance, R1
Once the VCC capacitance is known, the start-up resistance from VBULK to achieve the turn-on time target can be
determined.
R1 =
ISTART
2 × VIN(max)
V
× C VCC
+ VCCON
TSTR
(21)
VSNS Resistor Divider
The VSNS divider resistors determine the output voltage regulation point of the flyback converter, also the highside divider resistor (RAUX1) determines the line voltage at which the controller enables continuous GATE
operation. RAUX1 is initially determined based on transformer auxiliary to primary turns ratio and desired input
voltage operating threshold.
R AUX1 =
VIN(run) × 2
NPA × IVSNS(run)
(22)
The low-side VSNS pin resistor is selected based on desired VOUT regulation voltage.
R AUX1 × VVSNSR
R AUX 2 =
NAS × (VOCV + VF ) − VVSNSR
(23)
The TPS92315 can maintain tight constant-current regulation over input line by utilizing the line compensation
feature. The line compensation resistor (RLC) value is determined by current flowing in RAUX1 and expected gate
drive and MOSFET turn-off delay. Assume a 50 ns internal delay in the TPS92315.
K × R AUX1 × RISNS × TD × NPA
RLC = LC
LP
(24)
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS92315DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T315
TPS92315DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T315
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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