TRF2443
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
Integrated IF Transceiver for Broadband Wireless Applications
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FEATURES
1
•
•
•
•
•
Integrated TX Chain (165–175 MHz / 330–350
MHz)
– Baseband Amplifiers
– Quadrature Modulator
– Digitally Controlled VGA
– TX Output IP3: 29.5 dBm
– TX Output Noise: –166 dBc/Hz
Integrated RX Chain (140–165 MHz / 280–330
MHz)
– IF Amplifiers
– Analog and Digital VGA
– Quadrature Demodulator
– Baseband Filters
– ADC Buffers
– IF SAW Filter Bypass
– RX Noise Figure: 4.3 dB
– RX Input IP3: 9.5 dBm
Integrated TX and RX Synthesizers
Integrated Cross-Polarization Interference
Cancellation (XPIC) Support
Auxiliary RX Chain
APPLICATIONS
•
•
•
•
Wireless Microwave Backhaul
Point-to-Point Microwave
Broadband Wireless Applications
WiMAX IF Transceiver
DESCRIPTION
The TRF2443 is a highly integrated full-duplex
intermediate frequency (IF) transceiver designed for
broadband point-to-point wireless communications
applications. The receiver chain integrates a
quadrature (IQ) demodulator and provides more than
90 dB of gain range, obtained via a combination of
analog- and digital-controlled VGAs. The integrated
programmable baseband low-pass filter gives the
TRF2443 the flexibility to receive signals with different
bandwidths, while also helping to remove interferer
signals before they reach the ADC. Additionally, the
TRF2443 gives the flexibility to add an external IF
filter to further remove unwanted signals. The
TRF2443 transmitter chain integrates a quadrature
(IQ) modulator driving a highly linear IF DVGA that
provides 35 dB of gain range controlled via a serial
programming interface (SPI). The TRF2443 includes
the two synthesizers for the receiver and transmitter
chains, removing the need for external LO generation
circuitry and simplifying the implementation of a
frequency-division duplexing (FDD) transceiver
design. The TRF2443 also provides crosspolarization interference cancellation (XPIC) support
via an integrated XPIC output amplifier and receiver
chain. The TRF2443 is an ideal building block for
implementing the IF transceiver function in the indoor
unit (IDU), which is connected via a coaxial cable
interface to the outdoor unit (ODU), of a point-to-point
microwave backhaul split-architecture system.
IF SAW
IF_OUT
RXAGC
IF_IN
XPIC
OUT
XPIC_IN
XPIC
AGC
XPIC_BBI
0/90
AGC
CNTL
XPIC_BBQ
from RXPLL
RXBBI
IFAMP
RX_IN
TEMPOUT
0/90
RXBBQ
RX VGA
Temperature
Sensor
RXPLL
VCCs
S
P
I
3
CLKSPI
DATASPI
LESPI
From SPI
7
TXI_IN
TX VGA
TX_OUT
TXPLL
GNDs
0/90
Level
Detect
TXQ_IN
TX_PWD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
TRF2443
SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TRF2443 DEVICE DESCRIPTION
IF SAW
IF_OUT
RXAGC
IF_IN
XPIC
OUT
XPIC_IN
XPIC
AGC
XPIC_BBI
0/90
AGC
CNTL
XPIC_BBQ
from RXPLL
RXBBI
IFAMP
RX_IN
TEMPOUT
0/90
RXBBQ
RX VGA
Temperature
Sensor
RXPLL
VCCs
S
P
I
3
CLKSPI
DATASPI
LESPI
From SPI
7
TXI_IN
TX VGA
TX_OUT
TXPLL
GNDs
0/90
TXQ_IN
Level
Detect
TX_PWD
Figure 1. TRF2443 Functional Block Diagram
RECEIVER DESCRIPTION
IF SAW
RX_AGC
IF_OUT
AGC
CNTL
IF_IN
BB AMP/FLT
RX VGA
RX_BBI
LNA
0/90
RX_IN
IFVGA1
IFVGA2
IFVGA3
RX _BBQ
From SPI
from RXPLL
From SPI
Figure 2. Receiver Chain Block Diagram
The TRF2443 features a highly linear low-noise receiver chain with over 60 dB of analog-controlled gain range
and more than 40 dB of gain range programmable via the serial programming interface (SPI) in 1-dB steps.
Moreover, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. Such
an external filter can be bypassed using an internal path that can be enabled via SPI. The first block of the
receiver chain is a low-noise, highly linear IF amplifier (LNA). Its input is differential and internally matched to 50
2
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Ω. The TRF2443 LNA attenuation is programmable from 0 dB to –19 dB, corresponding to an LNA gain of 17 dB
to –2 dB (1-dB steps). The LNA is followed by three analog-controlled VGAs that provide more than 60 dB of
gain range. The IFVGA1 output and IFVGA2 input can be connected externally (pins IFOUT and IFIN) through
an external IF filter. An internal switch gives the flexibility to bypass the external filter. The VGAs provide a gain
slope of 51 dB/V. The IFVGA3 drives the demodulator, which downconverts the IF input signal directly to
baseband in-phase and quadrature. The demodulator block includes the local oscillator in-phase and quadrature
generation circuitry followed by the LO buffer. The TRF2443 baseband section integrates a programmable-gain
amplifier (PGA) and programmable low-pass filter. The baseband PGA minimum gain is 9 dB, and the maximum
gain is 33 dB. The TRF2443 baseband low-pass filter cutoff frequency can be programmed from 2 MHz to 11
MHz by setting the cutoff-frequency control bits appropriately. The baseband output buffers (ADC drivers) are
designed to drive directly an analog-to-digital converter (ADC), either dc- or ac-coupled. The output common
mode of the ADC drivers is set externally via the RXBBCM pin (pin 40). When the TRF2443 is dc-connected to
the ADC, the same dc common mode can be used for both the ADC and the TRF2443 baseband output.
TRANSMITTER DESCRIPTION
VCC
From SPI
TX_OUT
From TX
PLL
To feedback
switch
TXI_IN
6
0/90
TXAMP
VCC
ATT
Level
Detect
TXQ_IN
TX_PWD
Figure 3. Transmitter Chain Block Diagram
The transmitter chain integrates an IQ modulator followed by a variable attenuator and the final transmitter
amplification stage. The last two blocks provide over 35 dB of gain range. A power-alarm circuit monitors the
level at the modulator output, and its digital output goes low if the signal level falls below the user-specified
threshold level relative to the expected level. The first block of the transmitter chain is the IQ modulator, which
upconverts the incoming in-phase and quadrature signals to the TX IF frequency. The TRF2443 can be either acor dc-coupled to the digital-to-analog converter (DAC). The IQ modulator drives a variable attenuator. This block
provides 5.5 dB of total attenuation range in 0.5-dB steps. The output amplifier integrates five attenuation steps
of 6 dB each for total of 30 dB. The output amplifier in combination with the variable attenuator provides over
35.5 dB of monotonic output power control (0.5-dB steps).
SYNTHESIZERS DESCRIPTION
TRF2443 integrates two complete integer synthesizers for the receiver and transmitter chain. The RXVCO
operates at 16 times the typical RX input frequency, and the TXVCO operates at 8 times the typical TX output
frequency.
Each synthesizer is composed of:
• High-frequency VCO (around 2720 MHz for the TX VCO and 2240 MHz for the RX VCO)
• N-divider (driven by the high-frequency VCO) done by an 8/9 prescaler followed by an A-B counter that drives
the phase-frequency detector
• Phase-frequency detector (PFD) (driven by the N-divider) that compares the VCO divided by N to the
reference clock divided by R signals
• Charge pump (driven by the PFD) which creates up and down current pulses, based on the incoming signals
from the PFD. Its output is filtered and transformed to voltage by the external loop filter and applied to the
VCO input control voltage.
• An external reference clock must be applied to the REFIN (pin 16). The incoming signal is buffered and goes
through a programmable divider (R-divider).
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The VCO output is then routed through a programmable divider by 8 or 16 to create the TX and RX LO signals.
The TRF2443 features a lock-detect output pin (LOCKDET, pin 5). This is a digital output that is high when both
RX and TX synthesizers are locked, and it is low if one or both synthesizers are unlocked (or lose lock).
XPIC DESCRIPTION
The TRF2443 provides cross-polarization interference cancellation (XPIC) support via an integrated XPIC output
amplifier and receiver chain. The XPIC output amplifier transmits the signal taken at the receiver demodulator
input. The XPIC receiver section downconverts the input signal to baseband I and Q. It includes an IF VGA
followed by a demodulator and a baseband amplifier.
PINOUT DIAGRAM
GNDRX
IFOUTP
IFOUTN
RDBKSPI
RXAGC
VCCRX
GND
RXINN
RXINP
GNDRX
GNDRX
CLKSPI
LESPI
VCCSPI
DATASPI
TXOUTP
VCCTX
GNDTX
TXOUTN
GNDTX
PFP Package
(Top View)
TXPWD
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
MIXINDN
2
59
GNDIFIN
MIXINDP
58
57
IFINN
PWRDET
3
4
LOCKDET
5
56
VCCIFIN
TXLOTEST
6
55
XPICOUTP
XPICOUTN
GNDVCOTX
7
8
54
53
RXLOTEST
VTUNETX
9
52
VCCVCORX
CPOUTX
10
51
GNDVCORX
GNDPLLTX
11
50
VTUNERX
VCCPLLTX
12
49
CPOUTRX
VCCDIGTX
13
48
GNDPLLRX
GNDDIGTX
14
47
VCCPLLRX
VCCREF
15
46
VCCDIGRX
VCCVCOTX
TRF2443
GNDIFIN
IFINP
REFIN
16
45
GDNDIGRX
GNDREFIN
17
44
RXBBIP
GND
18
43
RXBBIN
TXBBQN
19
42
RXBBQP
TXBBQP
20
41
RXBBQN
RXBBCM
GNDRX2
LDCAP
GND
TEMPOUT
XPICINP
XPICINN
GND
VCCXPIC2
GND
XPICAGC
VCCXPIC
XPICBBIP
XPICBBIN
XPICBBQP
XPICBBQN
XPICBBCM
GNDXPIC
TXBBIP
TXBBIN
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P0027-04
4
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
CLKSPI
73
I
SPI clock
CPOUTRX
49
O
RX PLL charge-pump output
CPOUTX
10
O
TX PLL charge-pump output
DATASPI
74
I
SPI data
18, 31,
32, 36,
66
–
Ground
GNDDIGRX
45
–
RX PLL digital ground
GNDDIGTX
14
–
TX PLL digital ground
GND
GNDIFIN
59, 60
–
RX chain ground
GNDPLLRX
48
–
RX PLL ground
GNDPLLTX
11
–
TX PLL ground
GNDREFIN
17
–
Reference clock ground
GNDRX
61, 70,
71
–
RX chain ground
GNDRX2
39
–
RX chain ground
GNDTX
79, 80
–
TX chain ground
GNDVCORX
51
–
RX VCO ground
GNDVCOTX
8
–
TX VCO ground
GNDXPIC
23
–
XPIC ground
IFINN
58
I
IFVGA2 input: negative terminal
IFINP
57
I
IFVGA2 input: positive terminal
IFOUTN
62
O
IFVGA1 output: negative terminal
IFOUTP
63
O
IFVGA1 output: positive terminal
LDCAP
38
I/O
PLL lock detector decoupling capacitor pin
LESPI
72
I
SPI latch enable
LOCKDET
5
O
PLL lock detect output (digital HIGH = locked, LOW = unlocked)
MIXINDN
2
O
TX mixer output collector: negative terminal
MIXINDP
3
O
TX mixer output collector: positive terminal
PWRDET
4
O
Power alarm output (digital HIGH = output power above threshold; LOW = output power below
threshold)
RDBKSPI
64
O
SPI data readback
REFIN
16
I
PLL reference clock input
RXAGC
65
I
RX AGC control input
RXBBCM
40
I
RX chain common-mode input
RXBBIN
43
O
RX baseband output I: negative terminal
RXBBIP
44
O
RX baseband output I: positive terminal
RXBBQN
41
O
RX baseband output Q: negative terminal
RXBBQP
42
O
RX baseband output Q: positive terminal
RXINN
69
I
RX input: negative terminal
RXINP
68
I
RX input: positive terminal
RXLOTEST
53
O
RX LO test pin
TEMPOUT
37
O
Temperature sensor output
TXBBIN
21
I
TX baseband I input: negative input
TXBBIP
22
I
TX baseband I input: positive input
TXBBQN
19
I
TX baseband Q input: negative input
TXBBQP
20
I
TX baseband Q input: positive input
TXLOTEST
6
O
TX LO test pin
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
TXOUTN
78
O
TX IF output: negative terminal
TXOUTP
77
O
TX IF output: positive terminal
TXPWD
1
I
TX power down
VCCDIGRX
46
–
RX PLL digital power supply
VCCDIGTX
13
–
TX PLL digital power supply
VCCIFIN
56
–
RX chain power supply
VCCPLLTX
12
–
TX PLL power supply
VCCPLLRX
47
–
RX PLL power supply
VCCREF
15
–
Reference clock power supply
VCCRX
67
–
RX chain power supply
VCCSPI
75
–
SPI power supply
VCCTX
76
–
TX power supply
VCCVCORX
52
–
RX VCO power supply
VCCVCOTX
7
–
TX VCO power supply
VCCXPIC
29
–
XPIC power supply
VCCXPIC2
33
–
XPIC power supply
VTUNERX
50
I
RX VCO input control voltage
VTUNETX
9
I
VCO tune voltage input
XPICAGC
30
I
XPIC AGC control input
XPICBBCM
24
I
XPIC common-mode input
XPICBBIN
27
O
XPIC baseband I output: negative terminal
XPICBBIP
28
O
XPIC baseband I output: positive terminal
XPICBBQN
25
O
XPIC baseband Q output: negative terminal
XPICBBQP
26
O
XPIC baseband Q output: positive terminal
XPICINN
34
I
XPIC input
XPICINP
35
I
XPIC input
XPICOUTN
54
O
XPIC output
XPICOUTP
55
O
XPIC output
6
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ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.3 to 5
V
ESD rating, HBM
2000
V
ESD rating, CDM
500
V
Input voltage range (2)
TJ
Junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
TRF2443
THERMAL METRIC (1)
θJA
Junction-to-ambient thermal resistance
22.9
θJCtop
Junction-to-case (top) thermal resistance
6.7
θJB
Junction-to-board thermal resistance
3.6
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
3.5
θJCbot
Junction-to-case (bottom) thermal resistance
0.4
(1)
UNITS
PFP (80 PINS)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
3.3
UNIT
VCC_3V
3.3-V power-supply voltage
3
3.6
V
V_RXAGC
Analog AGC voltage (pin 65)
0
2
V
V_XPICAGC
Analog AGC voltage (pin 30)
0
1
V
TJ
Operating junction temperature
0
125
°C
TA
Operating ambient temperature
–40
85
°C
MAX
UNIT
65
DC CHARACTERISTICS
VCC = 3.3 V; TJ = 65°C
PARAMETER
TEST CONDITIONS
MIN
TYP
TX on; RX on (SAW off); XPIC off
ICC
Total supply current
947
TX on; RX on (SAW on); XPIC off
965
TX on; RX on (SAW on); XPIC on
1085
mA
DIGITAL INTERFACE CHARACTERISTICS
VCC = 3.3 V; TJ = 65°C
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
MAX
UNIT
2
TYP
VCC
V
0
0.8
V
0.8 VCC
V
0.2 VCC
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RECEIVER CHARACTERISTICS
VCC_3V = 3.3 V ±5%, TJ = 65°C , IF SAW filter insertion loss = 10 dB (1) (unless otherwise noted)
PARAMETER
fIF
TEST CONDITIONS
MIN
Input IF frequency
TYP
MAX
140
UNIT
MHz
From RX_IN to RX_BBI/RX_ BBQ
(2)
Gmax
Gmin
(2)
Maximum voltage gain
Minimum voltage gain
LNA_ATT = 0; RXAGC = 2 V (3)
76
LNA_ATT = 0; RXAGC = 2 V (4)
69
LNA_ATT = 17; RXAGC = 2 V (3)
59
LNA_ATT = 17; RXAGC = 2 V (4)
52
12
25
(4)
12
27
LNA_ATT = 0; RXAGC = 0 V
LNA_ATT = 17; RXAGC = 0 V (3)
8
LNA_ATT = 17; RXAGC = 0 V (4)
10
(5)
LNA attenuation step
LNA_ATT = 17
Digital gain step
LNA attenuation setting through SPI
ΔGrange
Analog gain range
RXAGC from 0 V to 2 V (6)
Gain flatness
16.9
IP3
Input IP3
Γin
Input return loss
17.9
18.9
dB
dB
1.05
dB
62
dB
From 110 MHz to 170 MHz
1.5
dB
LNA_ATT = 0 (8)
4.5
6
18.5
23
54
Gain control slope
Noise figure (7)
dB
68
LNA_ATT = 0; RXAGC = 0 V (3)
ΔGstep
NF
86
51
(9)
LNA_ATT = 17 (10)
LNA_ATT = 0 (12)
LNA_ATT = 17
(11)
(13)
(14) (15)
Z0 = 50 Ω, differential
dB/V
-9.5
3
dBm
6.5
–25
dB
–12
dB
FROM RX_IN TO IF_OUT
Gmax
Maximum voltage gain
ΔGdig
Digital gain range
ΔGstep
Digital gain step
ΔGanalog
Analog gain range
Programmed by SPI
LNA_ATT = 0, RXAGC = 2 V
Input return loss
Z0 = 50 Ω, differential
(13)
(14)
(15)
8
dB
–13
Input IP3
(12)
34
19.5
Γin
(11)
dB
LNA_ATT = 17, RXAGC = 2 V
IP3
(10)
dB
1.05
3.5
Noise figure
(9)
dB
20
LNA_ATT = 0, RXAGC = 2 V
NF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
33
dB
dBm
–12
dB
10 dB includes SAW filter insertion loss plus matching/board loss
Gain measured from transformer input to RXBBI/Q output. External transformer insertion loss = 0.5 dB
SAW filter path enabled; baseband amplifier gain setting set to 9
SAW filter path disabled; baseband amplifier gain setting set to 0
Attenuation measured from LNA_ATT = 0 state.
Monotonicity of RX gain versus VAGC is specified up to the maximum voltage gain spec and not the maximum VAGC voltage.
Automated test equipment 1-sigma measurement uncertainty of 0.15 dB.
SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 55 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path enabled; baseband amplifier gain setting set to 3; total gain = 66 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 38 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path enabled; baseband amplifier gain setting set to 3; total gain = 49 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path enabled; baseband amplifier gain setting set to 9; total gain = 33 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 35 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path enabled; baseband amplifier gain setting set to 9; total gain = 16 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 18 dB (gain measured from transformer input to RXBBI/Q
output; external transformer insertion loss = 0.5 dB)
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RECEIVER CHARACTERISTICS (continued)
VCC_3V = 3.3 V ±5%, TJ = 65°C , IF SAW filter insertion loss = 10 dB(1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FROM IF_IN TO RX_BBI (OR RX_BBQ)
Gmax
Maximum voltage gain
RXAGC = 2 V, RXBB_GAIN = 9
58
dB
ΔGdig
Digital gain range
Programmed by SPI
24
dB
ΔGstep
Digital gain step
1
dB
ΔGanalog
Analog gain range
28
dB
NF
Noise figure
Image rejection
RXAGC = 2 V, RXBB_GAIN = 9
12.5
RXAGC = 0 V, RXBB_GAIN = 9
28
See RX Image Rejection section
-40
Output common mode
Baseband output load
Parallel capacitor
Parallel resistor
dB
dB
1.5
V
15
pF
1
kΩ
BASEBAND LOW-PASS FILTER
fC_ON
3-dB cutoff frequency
Filter on, programmed via SPI
ATT30M
Filter rejection at 30 MHz
Filter bypassed
3-dB point with fC = 2.3 MHz
2
(16)
2.2
3-dB corner-frequency step (17)
MHz
dB
MHz
25
kHz
Rejection at 8.75 MHz with fC = 2.3 MHz (16)
76
dB
Rejection at 17.5 MHz with fC = 2.3 MHz (16)
80
Rejection at 4.5 MHz with fC = 2.3 MHz
Filter rejection
11
1
(16)
3-dB point with fC = 8.5 MHz (16)
36
8.3
(16)
30
Rejection at 35 MHz with fC = 8.5 MHz (16)
65
Rejection at 18 MHz with fC = 8.5 MHz
Rejection at 70 MHz with fC = 8.5 MHz (16)
MHz
dB
80
(16) After room-temperature cutoff-frequency calibration
(17) Baseband filter 3-dB corner frequency control step via SPI around fC = 2.3 MHz
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TRANSMITTER CHARACTERISTICS
VCC_3V = 3.3 V ± 5%, TJ = 65°C (unless otherwise noted)
PARAMETER
fIout
TEST CONDITIONS
MIN
TYP
TX output frequency
MAX
340
UNIT
MHz
FROM TXBBI/Q INPUTS TO TX RFOUT
Pmax
Maximum output power
TX ATT set to 0 (1)
Pmin
Minimum output power
TX ATT set to 35
Grange
Gain range
Programmed by SPI
31
Gstep
1-dB gain step
Two consecutive 1-dB steps
0.8
Nout
Output noise floor
2.5
dBm
–28.5
dB
1.2
TX ATT set to 4 (2)
–139
–135
TX ATT set to 31 (2)
–166
–162
Two tones of –2.5 dBm each at TX
output (3)
27.5
Two tones of –29.5 dBm each at TX
output (3)
0.5
dBm
dB
dBm/Hz
29.5
OIP3
Output IP3
CS
Carrier leakage
Calibrated; TX ATT set to 4 (4)
–55
–35
dBm
SBS
Side-band suppression
Uncalibrated (5)
–50
–35
dB
HD2
Second harmonic level
See
(1)
HD3
Third harmonic level
See
(1)
τoff
TX turnoff time (6)
TX_PWD: low → high;
10
TX_PWD = high
30
TX off attenuation
VCM
ZBBin
Γout
(7)
dBm
dBc
dBc
μs
dB
1.4
V
Parallel resistor
10
kΩ
Parallel capacitor
0.1
pF
Z0 = 50 Ω
Output return loss
–50
100
Baseband input common-mode voltage (8)
TX differential input impedance
–55
(9)
–12
dB
(11)
dB
POWER ALARM DETECTOR (See the Power Alarm Detector section)
Detector threshold
Response time
(12)
See
(10)
(specified by design)
See
See
(11)
(11)
See
μs
(1)
(2)
(3)
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI (or TXBBQ) input level of –23 dBVrms
No signal applied to TRF2443. This parameter is assured by characterization and is not production tested.
Two tones of –26 dBVrms each at TXBBI and TXBBQ inputs at 5 MHz and 8 MHz; measured at transformer output (0.7-dB insertion
loss).
(4) Using internal common and dc offset control
(5) TXIQ_PHASE set to 8; SPI-3, register 1, B
(6) See the TX Output Power Ramp-Down section.
(7) Attenuation of output level from TX on.
(8) Common mode input is set internally. It is possible to disable internal bias through SPI and apply external common mode.
(9) Single-ended, measured at transformer output
(10) Delta output power level at TX fixed gain that forces detector output low (power alarm).
(11) Detector threshold and response time are fully programmable by the user. (See the Power Alarm Detector section.)
(12) If output power is lower than threshold for more than user-specified value, power-alarm detector output goes low.
10
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RF SYNTHESIZER CHARACTERISTICS
VCC_3V = 3.3 V ±5%, TJ = 65°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
TXVCO
ftxvco
ftxlo
TXVCO frequency range
TXLO frequency range
TXLO free-running phase noise
KvTX
See
(1)
2640
2800
Divide-by-8 mode
330
350
Divide-by-16 mode
165
175
fout = 340 MHz; offset = 10 kHz
–92.5
fout = 340 MHz; offset = 100 kHz
–117.5
fout = 340 MHz; offset = 1 MHz
–140
fout = 340 MHz; offset = 20 MHz
–150
TXVCO gain
MHz
dBc/Hz
45
MHz/V
20
MHz
TXPLL
fPFD
PFD frequency
TXLO closed-loop phase noise
fout = 340 MHz; offset = 20 kHz
–117
fout = 340 MHz; offset = 100 kHz
–116
fout = 340 MHz; offset = 1 MHz
–140
fout = 340 MHz; offset = 20 MHz
–150
Integrated TXLO noise
Integrated from 1 kHz to 12 MHz; fout = 340 MHz (2)
–56.5
Reference spur
Measured at TXLOTEST (2720 MHz)
Lock time
From unlocked state to locked state (includes digitalcalibration time) (3)
TXLO closed-loop phase noise
–121
fout = 165 MHz; offset = 100 kHz
–120
fout = 165 MHz; offset = 1 MHz
–141
TJ = 65°C
RXVCO frequency range
See
dBc
μs
300
fout = 165 MHz; offset = 20 kHz
PLL-lock minimum power supply
dB
–70
fout = 165 MHz; offset = 20 MHz
Vccmin
dBc/Hz
dBc/Hz
–147
2.8
V
RXVCO
frxvco
frxlo
RXLO frequency range
RXLO free-running phase noise
KvRX
(1)
2240
2640
Divide-by-8 mode
280
330
Divide-by-16 mode
140
165
fout = 140 MHz; offset = 10 kHz
–97.5
fout = 140 MHz; offset = 100 kHz
–122.5
fout = 140 MHz; offset = 1 MHz
–146
fout = 140 MHz; offset = 20 MHz
–150
RXVCO gain
MHz
MHz
dBc/Hz
45
MHz/V
20
MHz
RXPLL
fPFD
PFD frequency
Integrated RXLO noise
RXLO closed-loop phase noise
(1)
(2)
(3)
Integrated from 1 kHz to 12 MHz; fout = 140 MHz (2)
–62
Integrated from 1 kHz to 12 MHz; fout = 160 MHz (2)
–60
fout = 140 MHz; offset = 20 kHz
–122
fout = 140 MHz; offset = 100 kHz
–121
fout = 140 MHz; offset = 1 MHz
–146
fout = 140 MHz; offset = 20 MHz
–150
Reference spur
Measured at RXLOTEST (2240 MHz)
Lock time
From unlock state to lock state (includes digitalcalibration time) (3)
dB
dBc/Hz
–65
300
dBc
μs
Frequency range proven locked with PFD frequency = 20 MHz
Optimized for lowest integrated noise; see the Reference-Clock Characteristics table for recommended reference clock performance.
Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter optimized (see Application Schematic section)
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REFERENCE-CLOCK CHARACTERISTICS
VCC = 3.3 V
PARAMETER
fref
TEST CONDITIONS
MIN
Reference frequency
TYP
MAX
20
Phase noise
Reference-clock input level
1 kHz
–135
Floor
–160
REFIN pin, ac-coupled on board (internally dccoupled)
UNIT
MHz
dBc/Hz
0.8
2
3
MIN
TYP
MAX
VPP
XPIC CHARACTERISTICS
VCC_3V = 3.3 V ± 5%, TJ = 65°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UNIT
From RX_IN to XPIC_OUT
fin
Input frequency
Pout
Output power
Pin = –32 dBm, LNA ATT set to 0 (1)
Output power flatness
From 110 MHz to 170 MHz
Noise figure
LNA ATT set to 0, total gain = 20 dB
OIP3
Output IP3
Two tones of –16 dBm each at 136 MHz and 144
MHz (1) (2) (3)
Γout
Output return loss
Z0 = 75 Ω, single-ended
NF
140
–14
–12
MHz
–10
1
15
11.5
dBm
dB
22
13
dB
dBm
–12
dB
FROM XPIC_IN TO XPIC_BBI/Q
Maximum gain (4)
GMAX
GMIN
Minimum gain
(4)
XPIC_AGC = 0.7 V and XPICBB_GAIN set to 2
21
XPIC_AGC = 0 V and XPICBB_GAIN set to 2
5
Gain control slope
GDRange
NF
IP3
Γin
Digital gain range
Programmed via SPI
Gain flatness
Measured over 110 MHz to 170 MHz
Noise figure
XPICBB_GAIN set to 2; total gain = 21 dB
Input IP3
12
dB
22
6
9.5
25
dB
–12
1.5
Parallel capacitor
Parallel resistor
dB
dBm
–40
Output common mode
(1)
(2)
(3)
(4)
dB
1
XPICBB_GAIN set to 2; total gain = 10 dB
Z0 = 75 Ω, single-ended
dB
11
0
See RX Image Rejection section
10
dB/V
–4
Input return loss
dB
46
XPICBB_GAIN set to 2; total gain = 21 dB
Image rejection
Baseband output load
27
dB
V
15
pF
1
kΩ
RXAGC voltage to have RXBBI (or RXBBQ) output level = –17 dBVrms
LNA ATT set to 0; total power gain = 20 dB
Measured at XPIC_OUT balun output (75-Ω characteristic impedance)
Measured from differential output (XPICBBIP/N or XPICBBQP/N) to XPICINN input balun
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 140 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX GAIN
vs
RX AGC VOLTAGE
RX GAIN
vs
RX AGC VOLTAGE
90
90
TJ = 0°C
TJ = 65°C
TJ = 125°C
80
70
60
RX Gain (dB)
RX Gain (dB)
70
50
40
30
60
50
40
30
20
20
10
10
0
0
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
G001
Figure 4.
Figure 5.
RX INPUT IP3
vs
RX GAIN
RX INPUT IP3
vs
RX GAIN
10
G002
10
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0
−10
RX Input IP3 (dBm)
−10
RX Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
80
−20
−30
−40
−50
−60
−20
−30
−40
−50
−60
−70
−70
−80
−80
−90
−90
0
10
20
30
40
50
60
RX Gain (dB)
70
80
90
0
G003
Figure 6.
10
20
30
40
50
60
70
80
90
RX Gain (dB)
G004
Figure 7.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 140 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX NOISE FIGURE
vs
RX GAIN
RX NOISE FIGURE
vs
RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
RX Noise Figure (dB)
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
40
RX Noise Figure (dB)
45
35
30
25
20
15
35
30
25
20
15
10
10
5
5
0
0
0
10
20
30
40
50
RX Gain (dB)
60
70
80
90
0
G005
Figure 8.
14
10
20
30
40
50
RX Gain (dB)
60
70
80
90
G006
Figure 9.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 3, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX GAIN
vs
RX AGC VOLTAGE
RX GAIN
vs
RX AGC VOLTAGE
90
90
TJ = 0°C
TJ = 65°C
TJ = 125°C
80
70
60
RX Gain (dB)
RX Gain (dB)
70
50
40
30
60
50
40
30
20
20
10
10
0
0
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
G007
Figure 10.
Figure 11.
RX INPUT IP3
vs
RX GAIN
RX INPUT IP3
vs
RX GAIN
10
G008
10
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0
−10
RX Input IP3 (dBm)
−10
RX Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
80
−20
−30
−40
−50
−60
−20
−30
−40
−50
−60
−70
−70
−80
−80
−90
−90
0
10
20
30
40
50
60
RX Gain (dB)
70
80
90
0
G009
Figure 12.
10
20
30
40
50
60
70
80
90
RX Gain (dB)
G010
Figure 13.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 3, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX NOISE FIGURE
vs
RX GAIN
RX NOISE FIGURE
vs
RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
RX Noise Figure (dB)
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
40
RX Noise Figure (dB)
45
35
30
25
20
15
35
30
25
20
15
10
10
5
5
0
0
0
10
20
30
40
50
RX Gain (dB)
60
70
80
90
0
G011
Figure 14.
16
10
20
30
40
50
RX Gain (dB)
60
70
80
90
G012
Figure 15.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 6, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX GAIN
vs
RX AGC VOLTAGE
RX GAIN
vs
RX AGC VOLTAGE
100
100
TJ = 0°C
TJ = 65°C
TJ = 125°C
90
80
80
70
RX Gain (dB)
RX Gain (dB)
70
60
50
40
60
50
40
30
30
20
20
10
10
0
0
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
G013
Figure 16.
Figure 17.
RX INPUT IP3
vs
RX GAIN
RX INPUT IP3
vs
RX GAIN
10
G014
10
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0
−10
RX Input IP3 (dBm)
−10
RX Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
90
−20
−30
−40
−50
−60
−20
−30
−40
−50
−60
−70
−70
−80
−80
−90
−90
0
10
20
30
40
50
60
RX Gain (dB)
70
80
90
0
G015
Figure 18.
10
20
30
40
50
60
70
80
90
RX Gain (dB)
G016
Figure 19.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 6, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX NOISE FIGURE
vs
RX GAIN
RX NOISE FIGURE
vs
RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
RX Noise Figure (dB)
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
40
RX Noise Figure (dB)
45
35
30
25
20
15
35
30
25
20
15
10
10
5
5
0
0
0
10
20
30
40
50
RX Gain (dB)
60
70
80
90
0
G017
Figure 20.
18
10
20
30
40
50
RX Gain (dB)
60
70
80
90
G018
Figure 21.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX GAIN
vs
RX AGC VOLTAGE
RX GAIN
vs
RX AGC VOLTAGE
100
100
TJ = 0°C
TJ = 65°C
TJ = 125°C
90
80
80
70
RX Gain (dB)
RX Gain (dB)
70
60
50
40
60
50
40
30
30
20
20
10
10
0
0
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
G019
Figure 22.
Figure 23.
RX INPUT IP3
vs
RX GAIN
RX INPUT IP3
vs
RX GAIN
10
G020
10
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0
−10
RX Input IP3 (dBm)
−10
RX Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
90
−20
−30
−40
−50
−60
−20
−30
−40
−50
−60
−70
−70
−80
−80
−90
−90
0
10
20
30
40
50
60
70
RX Gain (dB)
80
90
100
0
G021
Figure 24.
10
20
30
40
50
60
70
80
90
100
RX Gain (dB)
G022
Figure 25.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RX NOISE FIGURE
vs
RX GAIN
RX NOISE FIGURE
vs
RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
RX Noise Figure (dB)
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
40
RX Noise Figure (dB)
45
35
30
25
20
15
35
30
25
20
15
10
10
5
5
0
0
0
10
20
30
40
50
60
RX Gain (dB)
70
80
90
100
0
G023
Figure 26.
20
10
20
30
40
50
60
RX Gain (dB)
70
80
90
100
G024
Figure 27.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 140 MHz (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
RX LNA ATTENUATION
vs
LNA ATTENUATION SETTING
RX LNA ATTENUATION
vs
LNA ATTENUATION SETTING
0
0
TJ = 0°C
TJ = 65°C
TJ = 125°C
−4
−6
−8
−10
−12
−14
−16
−18
2
4
6
8
10
12
14
16
18
−8
−10
−12
−14
−16
20
LNA Attenuation Setting (SPI-3, REG2)
0
2
4
6
8
10
12
14
16
18
20
LNA Attenuation Setting (SPI-3, REG2)
G037
Figure 28.
Figure 29.
RX LNA CUMULATIVE ATTENUATION ERROR
vs
LNA ATTENUATION SETTING
RX LNA CUMULATIVE ATTENUATION ERROR
vs
LNA ATTENUATION SETTING
RX LNA Cumulative Attenuation Error (dB)
RX LNA Cumulative Attenuation Error (dB)
−6
−20
0
2.0
1.0
−4
−18
−20
1.5
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−2
RX LNA Attenuation (dB)
RX LNA Attenuation (dB)
−2
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.5
0.0
−0.5
−1.0
−1.5
−2.0
G038
2.0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
LNA Attenuation Setting (SPI-3, REG2)
LNA Attenuation Setting (SPI-3, REG2)
G086
Figure 30.
G087
Figure 31.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 140 MHz (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
RX BASEBAND GAIN
vs
RXBB GAIN SETTING
32
30
TJ = 0°C
TJ = 65°C
TJ = 125°C
28
26
RX Baseband Gain (dB)
RX Baseband Gain (dB)
32
30
RX BASEBAND GAIN
vs
RXBB GAIN SETTING
24
22
20
18
16
14
12
10
8
28
26
24
22
20
18
16
14
12
10
8
0
2
4
6
8
10
12
14
16
18
20
22
RXBB Gain Setting (SPI-3, REG2)
24
2
6
8
10
12
14
16
18
20
22
G039
RX BASEBAND CUMULATIVE GAIN ERROR
vs
RXBB GAIN SETTING
RX BASEBAND CUMULATIVE GAIN ERROR
vs
RXBB GAIN SETTING
TJ = 0°C
TJ = 65°C
TJ = 125°C
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
2
4
6
8
10
12
14
16
18
20
22
24
3.0
2.5
24
G040
Figure 33.
RXBB Gain Setting (SPI-3, REG2)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
0
2
G088
Figure 34.
22
4
RXBB Gain Setting (SPI-3, REG2)
Figure 32.
3.0
2.5
0
0
RX Baseband Cumulative Gain Error (dB)
RX Baseband Cumulative Gain Error (dB)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
4
6
8
10
12
14
16
18
20
RXBB Gain Setting (SPI-3, REG2)
22
24
G089
Figure 35.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 280 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RXBBI GAIN
vs
RX AGC VOLTAGE
RXBBI GAIN
vs
RX AGC VOLTAGE
90
90
TJ = 0°C
TJ = 65°C
TJ = 125°C
80
70
RXBBI Gain (dB)
RXBBI Gain (dB)
70
60
50
40
30
60
50
40
30
20
20
10
10
0
0
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
G074
Figure 36.
Figure 37.
RXBBI INPUT IP3
vs
RX GAIN
RXBBI INPUT IP3
vs
RX GAIN
20
G075
20
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
10
RXBBI Input IP3 (dBm)
10
RXBBI Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
80
−10
−20
−30
−40
−50
−60
−70
0
−10
−20
−30
−40
−50
−60
−70
−80
−80
0
10
20
30
40
50
60
RX Gain (dB)
70
80
90
0
G076
Figure 38.
10
20
30
40
50
60
70
80
90
RX Gain (dB)
G077
Figure 39.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 280 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RXBBI NOISE FIGURE
vs
RX GAIN
RXBBI NOISE FIGURE
vs
RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
RXBBI Noise Figure (dB)
RXBBI Noise Figure (dB)
45
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
0
10
20
30
40
50
RX Gain (dB)
60
70
80
90
0
G078
Figure 40.
24
10
20
30
40
50
RX Gain (dB)
60
70
80
90
G079
Figure 41.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER TYPICAL CHARACTERISTICS
fin= 280 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RXBBI GAIN
vs
RX AGC VOLTAGE
RXBBI GAIN
vs
RX AGC VOLTAGE
90
90
TJ = 0°C
TJ = 65°C
TJ = 125°C
80
70
RXBBI Gain (dB)
RXBBI Gain (dB)
70
60
50
40
30
60
50
40
30
20
20
10
10
0
0
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
0
200
400
600
800 1000 1200 1400 1600 1800
RX AGC Voltage (mV)
G080
Figure 42.
Figure 43.
RXBBI INPUT IP3
vs
RX GAIN
RXBBI INPUT IP3
vs
RX GAIN
20
G081
20
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
10
RXBBI Input IP3 (dBm)
10
RXBBI Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
80
−10
−20
−30
−40
−50
−60
−70
0
−10
−20
−30
−40
−50
−60
−70
−80
−80
0
10
20
30
40
50
60
RX Gain (dB)
70
80
90
0
G082
Figure 44.
10
20
30
40
50
60
70
80
90
RX Gain (dB)
G083
Figure 45.
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RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 280 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless
otherwise noted)
RXBBI NOISE FIGURE
vs
RX GAIN
RXBBI NOISE FIGURE
vs
RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
RXBBI Noise Figure (dB)
RXBBI Noise Figure (dB)
45
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
0
10
20
30
40
50
RX Gain (dB)
60
70
80
90
0
G084
Figure 46.
26
10
20
30
40
50
RX Gain (dB)
60
70
80
90
G085
Figure 47.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS
(TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
0
−20
−40
BW = 1.8MHz
−60
−80
−100
0.01
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
BW = 1.8MHz
−60
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−80
0.1
1
Frequency (MHz)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX Low-Pass Filter Rejection (dB)
BW = 2.3MHz
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
Frequency (MHz)
10
10
G056
Figure 49.
−60
−100
0.01
−40
Figure 48.
−20
−80
−20
G055
0
−40
0
−100
0.01
10
Frequency (MHz)
RX Low-Pass Filter Rejection (dB)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX Low-Pass Filter Rejection (dB)
RX Low-Pass Filter Rejection (dB)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
0
−20
−40
BW = 2.3MHz
−60
−80
−100
0.01
G057
Figure 50.
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0.1
1
Frequency (MHz)
10
G058
Figure 51.
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RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued)
(TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
0
−20
−40
BW = 3.5MHz
−60
−80
−100
0.01
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
BW = 3.5MHz
−60
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−80
0.1
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX Low-Pass Filter Rejection (dB)
BW = 4.5MHz
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
10
10
G060
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
Frequency (MHz)
0
−20
−40
BW = 4.5MHz
−60
−80
−100
0.01
G061
Figure 54.
28
1
Frequency (MHz)
Figure 53.
−60
−100
0.01
−40
G059
−20
−80
−20
Figure 52.
0
−40
0
−100
0.01
10
Frequency (MHz)
RX Low-Pass Filter Rejection (dB)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX Low-Pass Filter Rejection (dB)
RX Low-Pass Filter Rejection (dB)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0.1
1
Frequency (MHz)
10
G062
Figure 55.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued)
(TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
0
−20
−40
BW = 8.5MHz
−60
−80
−100
0.01
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
BW = 8.5MHz
−60
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−80
0.1
1
Frequency (MHz)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX Low-Pass Filter Rejection (dB)
BW = 9MHz
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
Frequency (MHz)
10
10
G064
Figure 57.
−60
−100
0.01
−40
G063
−20
−80
−20
Figure 56.
0
−40
0
−100
0.01
10
Frequency (MHz)
RX Low-Pass Filter Rejection (dB)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX Low-Pass Filter Rejection (dB)
RX Low-Pass Filter Rejection (dB)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
0
−20
−40
BW = 9MHz
−60
−80
−100
0.01
G065
Figure 58.
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0.1
1
Frequency (MHz)
10
G066
Figure 59.
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RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued)
(TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
RX LOW-PASS FILTER REJECTION
vs
FREQUENCY
0.5
RX Low-Pass Filter Rejection (dB)
RX Low-Pass Filter Rejection (dB)
0.5
0.0
−0.5
−1.0
BW = 3.5MHz
−1.5
−2.0
−2.5
−3.0
0.01
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.1
1
Frequency (MHz)
10
0.0
−0.5
−1.0
BW = 3.5MHz
−1.5
−2.0
−2.5
−3.0
0.01
G092
Figure 60.
30
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0.1
1
Frequency (MHz)
10
G093
Figure 61.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
TRANSMITTER TYPICAL CHARACTERISTICS
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C,
VCC = 3.3 V, unless otherwise noted)
TX OUTPUT POWER
vs
TX ATTENUATION SETTING
TX OUTPUT POWER
vs
TX ATTENUATION SETTING
10
10
TJ = 0°C
TJ = 65°C
TJ = 125°C
0
−5
−10
−15
−20
−25
−30
0
−5
−10
−15
−20
−25
−30
fOUT = 340MHz
−35
0
5
10
fOUT = 340MHz
−35
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
0
5
10
15
20
25
30
35
TX Attenuation Setting (SPI-3, REG1)
G041
Figure 62.
Figure 63.
TX GAIN
vs
TX ATTENUATION SETTING
TX GAIN
vs
TX ATTENUATION SETTING
25
G042
25
TJ = 0°C
TJ = 65°C
TJ = 125°C
20
15
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
20
15
10
TX Gain (dB)
TX Gain (dB)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
5
TX Output Power (dBm)
TX Output Power (dBm)
5
5
0
−5
−10
10
5
0
−5
−10
−15
−15
fOUT = 340MHz
−20
0
5
10
fOUT = 340MHz
−20
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
0
G043
Figure 64.
5
10
15
20
25
30
35
TX Attenuation Setting (SPI-3, REG1)
G044
Figure 65.
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TRANSMITTER TYPICAL CHARACTERISTICS (continued)
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C,
VCC = 3.3 V, unless otherwise noted)
TX 0.5-dB GAIN STEP
vs
TX ATTENUATION SETTING
0.8
0.8
0.7
0.7
TX 0.5-dB Gain Step (dB)
TX 0.5-dB Gain Step (dB)
TX 0.5-dB GAIN STEP
vs
TX ATTENUATION SETTING
0.6
0.5
0.4
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.3
0.2
0
5
10
fOUT = 340MHz
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
0.5
0.4
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0.3
0.2
35
0
10
15
20
25
G047
Figure 66.
Figure 67.
TX 1-dB GAIN STEP
vs
TX ATTENUATION SETTING
TX 1-dB GAIN STEP
vs
TX ATTENUATION SETTING
30
35
G048
1.5
TJ = 0°C
TJ = 65°C
TJ = 125°C
1.3
fOUT = 340MHz
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
1.4
TX 1-dB Gain Step (dB)
1.4
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.3
fOUT = 340MHz
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.5
0
5
10
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
0
G049
Figure 68.
32
5
fOUT = 340MHz
TX Attenuation Setting (SPI-3, REG1)
1.5
TX 1-dB Gain Step (dB)
0.6
5
10
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
G050
Figure 69.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
TRANSMITTER TYPICAL CHARACTERISTICS (continued)
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C,
VCC = 3.3 V, unless otherwise noted)
TX CUMULATIVE GAIN ERROR
vs
TX ATTENUATION SETTING
TX CUMULATIVE GAIN ERROR
vs
TX ATTENUATION SETTING
0.5
TJ = 0°C
TJ = 65°C
TJ = 125°C
0.4
0.3
fOUT = 340MHz
TX Cumulative Gain Error (dB)
TX Cumulative Gain Error (dB)
0.5
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
0.3
fOUT = 340MHz
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.5
5
10
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
10
15
20
25
30
35
G090
G091
Figure 71.
UNCALIBRATED TX SIDEBAND SUPPRESSION
vs
TX ATTENUATION SETTING
UNCALIBRATED TX SIDEBAND SUPPRESSION
vs
TX ATTENUATION SETTING
TJ = 0°C
TJ = 65°C
TJ = 125°C
fOUT = 340MHz
50
45
40
35
30
0
5
TX Attenuation Setting (SPI-3, REG1)
Figure 70.
60
55
0
5
10
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
Uncalibrated TX Sideband Suppression (dB)
0
Uncalibrated TX Sideband Suppression (dB)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0.4
60
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
55
fOUT = 340MHz
50
45
40
35
30
0
G051
Figure 72.
5
10
15
20
25
30
35
TX Attenuation Setting (SPI-3, REG1)
G052
Figure 73.
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TRANSMITTER TYPICAL CHARACTERISTICS (continued)
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C,
VCC = 3.3 V, unless otherwise noted)
TX CARRIER LEAKAGE
vs
TX ATTENUATION SETTING
TX CARRIER LEAKAGE
vs
TX ATTENUATION SETTING
−40
TJ = 0°C
TJ = 65°C
TJ = 125°C
−50
TX Carrier Leakage (dBm)
TX Carrier Leakage (dBm)
−40
−60
−70
−80
−90
fOUT = 340MHz
−100
0
5
10
−60
−70
−80
−90
fOUT = 340MHz
−100
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
0
5
15
20
25
30
G094
Figure 74.
Figure 75.
TX OUTPUT IP3
vs
TX ATTENUATION SETTING
TX OUTPUT IP3
vs
TX ATTENUATION SETTING
35
G095
35
TJ = 0°C
TJ = 65°C
TJ = 125°C
30
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
30
TX Output IP3 (dBm)
25
20
15
10
5
25
20
15
10
5
fOUT = 340MHz
0
0
5
10
fOUT = 340MHz
0
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
0
G053
Figure 76.
34
10
TX Attenuation Setting (SPI-3, REG1)
35
TX Output IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−50
5
10
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
35
G054
Figure 77.
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SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
TRANSMITTER TYPICAL CHARACTERISTICS (continued)
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C,
VCC = 3.3 V, unless otherwise noted)
TX IM3
vs
TX ATTENUATION SETTING
80
80
75
75
70
70
65
65
TX IM3 (dBc)
TX IM3 (dBc)
TX IM3
vs
TX ATTENUATION SETTING
60
55
50
55
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
45
40
0
5
10
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
fOUT = 340MHz
15
20
25
30
40
35
TX Attenuation Setting (SPI-3, REG1)
0
5
10
fOUT = 340MHz
15
20
25
30
35
TX Attenuation Setting (SPI-3, REG1)
G072
G073
Figure 78.
Figure 79.
TX PROGRAMMABLE POWER-SHUTDOWN
vs
TIME
TX PROGRAMMABLE POWER-SHUTDOWN
vs
TIME
10
10
TJ = 0°C
TJ = 65°C
TJ = 125°C
−10
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
0
TX Output Power (dBm)
0
TX Output Power (dBm)
60
−20
−30
−40
−50
−60
−70
−10
−20
−30
−40
−50
−60
−70
SPI-3 REG3=
SPI-3 REG3=
−80
−80
0
10
20
30
40
50
60
70
Time (µs)
80
90
100
0
G067
Figure 80.
10
20
30
40
50
60
70
80
90
100
Time (µs)
G068
Figure 81.
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TRANSMITTER TYPICAL CHARACTERISTICS (continued)
Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C,
VCC = 3.3 V, unless otherwise noted)
TX OUTPUT NOISE
vs
TX ATTENUATION SETTING
−120
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
TX Output Noise (dBm/Hz)
−125
−130
−135
−140
−145
−150
−155
−160
−165
Note: No Input Signal
−170
0
5
10
15
20
25
30
TX Attenuation Setting (SPI-3, REG1)
G069
Figure 82.
PLL TYPICAL CHARACTERISTICS
Measured at TXLOTEST pin (6) and RXLOTEST pin (53). Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter
optimized (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
TX VCO PHASE NOISE
TX VCO PHASE NOISE
−90
−90
TJ = 0°C
TJ = 65°C
TJ = 125°C
−110
−120
BW = 2720MHz
−130
−140
−150
−160
0.01
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−100
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−100
−110
−120
BW = 2720MHz
−130
−140
−150
0.1
1
Frequency Offset (MHz)
10
100
−160
0.01
G096
Figure 83.
36
0.1
1
Frequency Offset (MHz)
10
100
G097
Figure 84.
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PLL TYPICAL CHARACTERISTICS (continued)
Measured at TXLOTEST pin (6) and RXLOTEST pin (53). Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter
optimized (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
RX VCO PHASE NOISE
RX VCO PHASE NOISE
−90
−90
TJ = 0°C
TJ = 65°C
TJ = 125°C
−110
−120
BW = 2240MHz
−130
−140
−150
−160
0.01
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−100
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−100
−110
−120
BW = 2240MHz
−130
−140
−150
0.1
1
10
Frequency Offset (MHz)
100
−160
0.01
G098
Figure 85.
0.1
1
10
100
Frequency Offset (MHz)
G099
Figure 86.
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XPIC RECEIVER TYPICAL CHARACTERISTICS
fin= 140 MHz, XPIC baseband gain setting = 2 (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
XPIC RX GAIN
vs
XPIC AGC VOLTAGE
XPIC RX GAIN
vs
XPIC AGC VOLTAGE
30
30
TJ = 0°C
TJ = 65°C
TJ = 125°C
20
15
10
5
20
15
10
5
0
0
0
100
200
300
400
500
600
700
XPIC AGC Voltage (mV)
0
200
300
400
500
G025
Figure 87.
Figure 88.
XPIC RX INPUT IP3
vs
XPIC RX GAIN
XPIC RX INPUT IP3
vs
XPIC RX GAIN
600
700
G026
14
TJ = 0°C
TJ = 65°C
TJ = 125°C
10
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
12
XPIC RX Input IP3 (dBm)
12
8
6
4
2
0
−2
10
8
6
4
2
0
−2
−4
−4
0
5
10
15
20
XPIC RX Gain (dB)
25
30
0
G027
Figure 89.
38
100
XPIC AGC Voltage (mV)
14
XPIC RX Input IP3 (dBm)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
25
XPIC RX Gain (dB)
XPIC RX Gain (dB)
25
5
10
15
20
XPIC RX Gain (dB)
25
30
G028
Figure 90.
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XPIC RECEIVER TYPICAL CHARACTERISTICS (continued)
fin= 140 MHz, XPIC baseband gain setting = 2 (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
XPIC RX NOISE FIGURE
vs
XPIC RX GAIN
XPIC RX NOISE FIGURE
vs
XPIC RX GAIN
50
50
TJ = 0°C
TJ = 65°C
TJ = 125°C
40
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
45
XPIC RX Noise Figure (dB)
XPIC RX Noise Figure (dB)
45
35
30
25
20
15
40
35
30
25
20
15
10
10
0
5
10
15
20
XPIC RX Gain (dB)
25
30
0
G029
Figure 91.
5
10
15
20
25
30
XPIC RX Gain (dB)
G030
Figure 92.
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INSERTION LOSSES TYPICAL CHARACTERISTICS
Measured after transformers (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted)
INPUT RETURN LOSS XPICIN
OUTPUT RETURN LOSS XPICOUT
−10
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−15
Output Return Loss XPICOUT (dB)
Input Return Loss XPICIN (dB)
−10
−20
−25
−30
−35
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−15
−20
−25
−30
−35
90
100 110 120 130 140 150 160 170 180 190
Frequency (MHz)
90
100 110 120 130 140 150 160 170 180 190
Frequency (MHz)
G031
Figure 93.
INPUT RETURN LOSS IFIN
OUTPUT RETURN LOSS IFOUT
−10
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
Output Return Loss IFOUT (dB)
Input Return Loss IFIN (dB)
−10
−15
−20
−25
−30
−35
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−15
−20
−25
−30
−35
90
100 110 120 130 140 150 160 170 180 190
Frequency (MHz)
90
100 110 120 130 140 150 160 170 180 190
Frequency (MHz)
G033
Figure 95.
OUTPUT RETURN LOSS TXOUT
−10
0
LNA_ATTN = 6
LAN_ATTN = 9
Output Return Loss TXOUT (dB)
LNA_ATTN = 0
LAN_ATTN = 3
Input Return Loss RXIN (dB)
G034
Figure 96.
INPUT RETURN LOSS RXIN
vs
LNA_ATT
−15
−20
−25
−30
−35
LNA_ATTN = 12
LAN_ATTN = 15
LNA_ATTN = 18
−40
90
100 110 120 130 140 150 160 170 180 190
Frequency (MHz)
VCC = 3.1V
VCC = 3.3V
VCC = 3.5V
−5
−10
−15
−20
−25
−30
−35
300
G035
Figure 97.
40
G032
Figure 94.
310
320
330
340
350
Frequency (MHz)
360
370
380
G036
Figure 98.
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SPI REGISTERS
The TRF2443 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift
register. There are a total of three signals that must be applied: the clock (CLKSPI), the serial data (DATASPI)
and the latch enable (LESPI). The TRF2443 has an additional pin (RDBKSPI) for readback functionality. This pin
is a digital pin and can be used to read back values of different internal registers.
The DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of the CLOCK. The latch enable is
asynchronous to the CLOCK, and at its rising edge the data in the shift register is loaded onto the selected
internal register. The 5 LSBs of the data field are the address bits to select the available internal registers (see
Figure 99).
The SPI can operate reliably at clock speeds up to 20 MHz (clock period = td
V1 = HIGH
PWRDET = HIGH
V1 = LOW
V1 = HIGH
PRE-ALARM MODE
PWRDET = HIGH
TIME COUNTER STARTS
TIME COUNTER < td
V1 = LOW
COUNTER ?
V1 ?
Figure 107. TX Power-Alarm Flow Chart
72
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TX OUTPUT POWER RAMP-DOWN
To avoid unwanted spurious emissions during power down of the transmitter, the power-down circuitry is
designed to ramp down the output power gradually. The ramp-down time constant is programmable.
PS_TC (SPI-3, register 3, B) allows selection of four different time constants.
PS_TC
POWER DOWN
00
28 μs
01
42 μs
10
57 μs
11
75 μs
The values shown in the preceding table are the typical times required for the output level to be attenuated
by 30 dB.
LOOPBACK
The TRF2443 integrates a loopback switch between the TX and the RX chains. The switch connects the TX
modulator output to the RX IFVGA3 input. This path can be used for three different functions:
• Loopback path for the transmitted signal
• RX baseband low-pass-filter corner-frequency calibration
• TX modulator LO leakage calibration
The loopback mode is enabled by setting EN_LB (SPI-3, register 1, B) to 1. When the switch is activated,
the TX amplifier, RX LNA, RX IFVGA1, and RX IFVGA2 are all turned off automatically.
The loopback path can be programmed with two different insertion losses:
• 20-dB insertion loss for the loopback path of the transmitted signal
• Minimum insertion loss for calibration mode
The attenuation mode is selected via EN_LB_ATT (SPI-3, register 1, B).
EN_LB_ATT = 1 → 20-dB attenuation
EN_LB_ATT = 0 → minimum insertion loss
TX Signal Loopback
The TRF2443 internal feedback path can be used to loop back the TX signal (1), which enables the RX chain to
be used to monitor the transmitted signal. This mode is controlled via the serial programming interface (SPI)
according the following possible steps:
1. Enable loopback switch with 20-dB attenuation
(a) EN_LB_ATT = 1 (SPI-3, register 1, B)
(b) EN_LB = 1 (SPI-3, register 1, B)
2. Program TXLO to 165 MHz (TXLO to 2640 MHz and TX divider to 16)
(a) TXRDIV = (SPI-1, register 1, B) [R = 1]
(b) TX_NINT = (SPI-1, register 2, B) [N = 66]
(c) TXDIV_SEL = 0 (SPI-1, register 2, B) [LO divider set to 16]
3. Program RXLO to 165 MHz (RXLO to 2640 MHz and RX divider to 16)
(a) RXRDIV = (SPI-2, register 1, B) [R = 1]
(b) RX_NINT = (SPI-2, register 2, B) [N = 132]
(c) RXDIV_SEL = 0 (SPI-2, register 2, B) [LO divider set to 16]
4. Set receiver baseband gain to 10 dB
(a) RXBB_GAIN = (SPI-3, register 2, B)
5. Program the receiver baseband-filter cutoff frequency to the appropriate value (depending on the TX signal
bandwidth).
(1)
For a TX loopback frequency of 165 MHz, the PLLs are locked to a 20-MHz PFD frequency.
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Baseband-Filter Cutoff-Frequency Calibration
The TRF2443 internal feedback path can be used to set up an automatic calibration of the RX baseband-filter
cutoff frequency. The procedure to calibrate the corner frequency to 3 MHz is described as follows.
1. Enable loopback switch with minimum insertion loss.
(a) EN_LB_ATT = 0 (SPI-3, register 1, B)
(b) EN_LB = 1 (SPI-3, register 1, B)
2. Program RXLO to 165 MHz (RXLO to 2640 MHz and RX divider to 16).
(a) RXRDIV = (SPI-2, register 1, B) [R = 1]
(b) RX_NINT = (SPI-2, register 2, B) [N = 132]
(c) RXDIV_SEL = 0 (SPI-2, register 2, B) [LO divider set to 16]
3. Set TXVCO divider to 16.
(a) TXDIV_SEL = 0 (SPI-1, register 2, B) [LO divider set to 16]
4. Set the TXPLL PFD frequency to 4 MHz (R divider = 5).
(a) TXRDIV = (SPI-1, register 1, B) [R = 5]
5. Apply a dc offset at the TRF2443 TX baseband inputs (to increase the TXLO leakage at the modulator
output).
6. Set the RX baseband amplifier gain to 22 dB.
(a) RXBB_GAIN = (SPI-3, register 2, B)
7. Set the RX baseband cutoff-frequency bit controls RXBB_FREQ = 011 1000 (typical value for fC = 3
MHz)
8. Program the TXLO frequency to 166 MHz (TXVCO = 2656 MHz).
(a) TX_NINT = (SPI-1, register 2, B) [N = 332]
9. Measure the RX baseband output-power level (at I or Q output): Pout1.
10. Program the TXLO frequency to 168 MHz (TXVCO = 2688 MHz).
(a) TX_NINT = (SPI-1, register 2, B) [N = 336]
11. Measure the RX baseband output power level (Pout2) and calculate attenuation: Att = Pout1 – Pout2.
12. If Att < 3 dB, then increase RXBB_FREQ and go back to 11); else if Att > 3 dB, then reduce RXBB_FREQ
and go back to 11). This is repeated until two sequential iterations result in the calculated attenuation being
above and below 3 dB. When this is observed, save the RXBB_FREQ value which results in an attenuation
value closer to 3 dB.
The TRF2443 baseband low-pass filter cutoff frequency can be programmed to any of 128 cutoff frequencies.
The cutoff frequency control consists of 7 bits, RXBB_FREQ, which are located in SPI-3, register 2,
B. RXBB_FREQ = corresponds to the minimum corner frequency. Figure 108 shows
the 3-dB bandwidth of the filter versus all possible SPI codes for a typical unit. Figure 109 shows the inverse of
the 3-dB bandwidth versus all possible SPI codes for a typical unit.
16
0.7
14
0.6
RXBB Filter 1/BW
RXBB Filter BW
12
10
8
RXBB I
6
4
0
0.3
RXBB I
0.2
0.0
0
0
10 20 30 40 50 60 70 80 90 100 110 120
LPF BW Adj (dec)
10 20 30 40 50 60 70 80 90 100 110 120
LPF BW Adj (dec)
G070
Figure 108. BW vs SPI Code (RXBB_FREQ
74
0.4
0.1
RXBB Q
2
RXBB Q
0.5
G071
Figure 109. 1/BW vs SPI Code (RXBB_FREQ
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Because the corner frequency is dependent on the on-chip capacitance, it is possible to observe variations from
unit to unit in the SPI code that yields a fixed corner frequency. Variations in capacitance from unit to unit result
in a unique 1/BW curve for each unit. If the same DUT is to be used at multiple corner frequencies, the user
should calibrate the DUT as described above to determine, at a minimum, 2 points on the 1/BW curve. From
these calibrated points, any other corner frequency can be extrapolated using linear regression.
TX LO Leakage Calibration
The TRF2443 internal feedback path can be used to set up an automatic calibration of the TX LO leakage
according the following potential procedure:
1. Enable loopback switch with minimum insertion loss.
(a) EN_LB_ATT = 0 (SPI-3, register 1, B)
(b) EN_LB = 1 (SPI-3, register 1, B)
2. Set RXLO = 330 MHz (RXVCO to 2640 MHz and RX divider to 8)
(a) RXRDIV = (SPI-2, register 1, B) [R = 1]
(b) RX_NINT = (SPI-2, register 2, B) [N = 132]
(c) RXDIV_SEL = 1 (SPI-2, register 2, B) [LO divider set to 8]
3. Set RX baseband in filter bypass mode and gain = 22 dB
(a) RXBB_GAIN = (SPI-3, register 2, B) [gain = 22 dB]
(b) RXBB_FLT_BYP = 1 (SPI-3, register 2, B) [bypass filter]
4. Program TX LO in normal mode (TXLO = 340 MHz).
(a) TXRDIV = (SPI-1, register 1, B) [R = 1]
(b) TX_NINT = (SPI-1, register 2, B) [N = 68]
(c) TXDIV_SEL = 1 (SPI-1, register 2, B) [LO divider set to 8]
5. Measure power level at RXBB output at 10 MHz = P1.
6. Change TX input dc offset until minimum P1 is achieved.
The TRF2443 TX baseband inputs can be ac- or dc-coupled to the external digital-to-analog converter (DAC). In
case of direct coupling, the DAC must provide the appropriate dc offset of step 6 to null the LO leakage. If an accoupled approach is selected, then the internal bias must be enabled by setting EN_TXCM = 1 (SPI-3, register 3,
B). In this case, the integrated dc DAC controls the baseband dc offset. The internal DAC is programmed
via the SPI. TXBBI (SPI-3, register 3, B) and TXBBQ (SPI-3, register 3, B) control
the internal DAC settings.
TXBBI = TXBBQ = corresponds to midrange, that is, no offset applied.
RX IMAGE REJECTION
The TRF2443 has been designed to provide optimal image rejection. Using symmetry in the design of the I and
Q paths of the receiver ensures that mismatch between the I and Q paths is minimized. Image rejection is a
function of the amplitude (A) mismatch and the phase error (Φ) from 90 degrees of the I and Q RX baseband
signals. Image rejection is calculated in the following manner:
é A 2 - 2Acosf + 1ù
Rejection(dB) = 10log ê 2
ú
êë A + 2Acosf + 1úû
DC-OFFSET CALIBRATION
The TRF2443 provides an automatic calibration procedure for adjusting the dc offset in the receiver and XPIC
baseband I/Q paths. The internal calibration requires a clock in order to function. This clock is derived internally
from the reference clock with a frequency divider, whose divider ratio is programmable. DCOFF_CLK (SPI3, register 5, B) and XDCOFF_CLK (SPI-3, register 5, B) set the division ratio for the dcoffset correction-loop clock for the receiver and XPIC chains, respectively.
The output full-scale range of the internal dc-offset-correction DAC is programmable using bits
DCOFF_BIAS (SPI-3, register 5, B) for the receiver chain and XPICDCOFF_BIAS (SPI-3,
register 5, B) for the XPIC chain. The range is shown in Table 11.
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Table 11. DC Offset Correction DAC Programmable Range
DCOFF_BIAS _B1
XPICDCOFF_BIAS _B1
DCOFF_BIAS _B0
XPICDCOFF_BIAS _B0
FULL SCALE
0
0
10 mV
0
1
20 mV
1
0
30 mV
1
1
40 mV
The I- and Q-channel output maximum dc-offset correction range can be calculated by multiplying the values in
Table 11 by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed
maximum correction range. The dc offset correction DAC output is affected by a change in the PGA gain, but if
the initial calibration yields optimum results, then the adjustment of the PGA gain during normal operation does
not significantly impair the dc offset balance.
The dc offset correction DACs are programmed from the internal registers when the RXBB_CALSELECT bit
(SPI-3, register 7, B) is set to 1 (default value at power on). At start-up, the internal registers are loaded at
half-scale, corresponding to a decimal value of 128. The autocalibration for the receiver chain is initiated by
setting the EN_BB_AUTOCAL bit (SPI-3, register 5, B) to 1. When the calibration is over, this bit is
automatically reset to 0. Similarly for the XPIC, by programming EN_XPIC_AUTOCAL (SPI-3, register 5, B)
to 1, the baseband dc-offset calibration starts. During calibration, the RX local oscillator must be on. At each
clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset and calculates
the new dc current for the DAC. After the 13th clock cycle, the calibration is complete and the EN_BB_AUTOCAL
(or EN_XPIC_AUTOCAL) bit is reset to 0. The dc-offset DAC state is stored in the internal registers and
maintained as long as the power supply is kept on or until a new calibration is started.
The required clock speed for the optimum calibration is determined by the internal detector behavior (integration
bandwidth, gain, sensitivity). The speed of the clock can be slowed down by selecting a clock divider ratio
DCOFF_CLK (SPI-3, register 5, B) and/or XDCOFF_CLK (SPI-3, register 5, B). The
detector has more averaging time the slower the clock; hence, it can be desirable to slow down the clock speed
for a given condition to achieve optimum results.
The internal registers controlling the internal dc current DAC for the receiver chain are accessible through the
SPI (SPI-3, register 7, B), providing a user-programmable method for implementing the dc-offset
calibration. To employ this option, the RXBB_CALSELECT (SPI-3, register 7, B) bit must be set to 0. During
this calibration, an external instrument monitors the output dc offset between the I/Q differential outputs and
programs the internal registers RXBBI_DCOFF (SPI-3, register 7, B
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