TRF3710
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
IQ DEMODULATOR
To Microcontroller
FEATURES
To Microcontroller
•
•
VOFFI
VCMI
Gain_B1
Gain_B2
NC
Gain_B0
MIXIoutn
NC
STROBE
1
VCCDIG
2
35
AGND
CHIP_EN
3
34
BBIoutp
VCCMIX
4
33
BBIoutn
NC
5
32
NC
MIXinp
6
31
LOip
MIXinn
7
30
LOin
NC
8
29
VCCLO
VCCMIX
9
28
BBQoutp
NC
10
27
BBQoutn
NC
11
26
AGND
NC
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VCCBBI
To ADC I
LOin
To ADC Q
VCCBBQ
VCMQ
VOFFQ
VCCBIAS
GNDBIAS
NC
REXT
NC
MIXQoutn
NC
NC
Wireless Infrastructure:
– WCDMA
– CDMA
Wireless Local Loop
High-Linearity Direct Downconversion
Receiver
MIXQoutp
TRF3710
APPLICATIONS
•
MIXIoutp
CLOCK
RFin
48 47 46 45 44 43 42 41 40 39 38 37
36
GNDDIG
NC
• Frequency Range: 1.7 GHz to 2 GHz
• Integrated Baseband Programmable-Gain
Amplifier
• On-Chip Programmable Baseband Filter
• High Cascaded IP3: 21 dBm at 1.9 GHz
• High IP2: 60 dBm at 1.9 GHz
• Hardware and Software Power Down
• 3-Wire Serial Programmable Interface
• Single Supply: 4.5-V to 5.5-V Operation
2
DATA
1
30 kW
DESCRIPTION
The TRF3710 is a highly linear and integrated direct-conversion quadrature demodulator optimized for
third-generation (3G) wireless infrastructure. The TRF3710 integrates balanced I and Q mixers, LO buffers, and
phase splitters to convert an RF signal directly to I and Q baseband. The on-chip programmable-gain amplifiers
allow adjustment of the output signal level without the need for external variable-gain (attenuator) devices. The
TRF3710 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating the
need for an external baseband filter.
Housed in a 7-mm × 7-mm QFN package, the TRF3710 provides the smallest and most integrated receiver
solution available for high-performance equipment.
AVAILABLE DEVICE OPTIONS (1)
(1)
PRODUCT
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKINGS
TRF3710
QFN-48
RGZ
–40°C to 85°C
TRF3710
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TRF3710IRGZR
Tape and reel, 2500
TRF3710IRGZT
Tape and reel, 500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
TRF3710
www.ti.com
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
Decoupling required
VCCDIG 2
VCCMIX 4 and 9
VCCBIAS 21
VCCBBQ 25
VCCBBI 36
VCCLO 29
OutBuffer
VCCs
PGA
Gnds
GNDDIG 1
GNDBIAS 22
AGND 26
AGND 35
DC Offset Cancel
PGA
Fast
Gain
Control
0°
90°
MIXinp
6
MIXinn
7
SPI
DC Offset Cancel
PGA
33
BBIoutn
34
BBIoutp
37
VCMI
38
VOFFI
48
CLOCK
47
DATA
46
STROBE
23
VOFFQ
24
VCMQ
27
BBQoutn
28
BBQoutp
OutBuffer
40
41
39
Gain_B2
Gain_B1
Gain_B0
30
31
Power
Down
LOin
3
LOip
CE
VCMI
Gain_B2
VOFFI
Gain_B0
Gain_B1
NC
NC
MIXIoutp
MIXIoutn
DATA
STROBE
CLOCK
RGZ Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
36
VCCBBI
GNDDIG
1
VCCDIG
2
35
AGND
CHIP_EN
3
34
BBIoutp
VCCMIX
4
33
BBIoutn
NC
5
32
NC
MIXinp
6
31
LOip
MIXinn
7
30
LOin
NC
8
29
VCCLO
VCCMIX
9
28
BBQoutp
NC
10
27
BBQoutn
NC
11
26
NC
25
12
13 14 15 16 17 18 19 20 21 22 23 24
2
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AGND
VCCBBQ
VCMQ
VOFFQ
GNDBIAS
REXT
VCCBIAS
NC
NC
MIXQoutn
MIXQoutp
NC
NC
NC
TRF3710
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3710
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
AGND
26, 35
I/O
DESCRIPTION
Analog ground; grounds can be tied together.
BBIoutn
33
O
Baseband I output: negative terminal
BBIoutp
34
O
Baseband I output: positive terminal
BBQoutn
27
O
Baseband Q output: negative terminal
BBQoutp
28
O
Baseband Q output: positive terminal
CHIP_EN
3
I
Chip enable; enabled = logic level 1, disabled = logic level 0
CLOCK
48
I
SPI clock input
DATA
47
I
SPI data input (programming data for baseband filter frequency setting, PGA gain settings, and dc
offset calibration).
Gain_B0
41
I
PGA fast-gain control bit 0
Gain_B1
40
I
PGA fast-gain control bit 1
Gain_B2
39
I
PGA fast-gain control bit 2
GNDBIAS
22
Bias-block ground. Grounds can be tied together.
GNDDIG
1
LOin
30
I
Digital ground. Grounds can be tied together.
Local oscillator input: negative terminal
LOip
31
I
Local oscillator input: positive terminal
MIXinn
7
I
Mixer input: negative terminal, connected to external balanced-to-unbalanced (balun) transformer;
balun type is frequency-specific.
MIXIoutn
44
O
Mixer I output: negative terminal (test pin). NC for normal operation
MIXIoutp
45
O
Mixer I output: positive terminal (test pin). NC for normal operation
MIXinp
6
I
Mixer input: positive terminal, connected to external balun; balun type is frequency-specific.
MIXQoutn
17
O
Mixer Q output: negative terminal (test pin). NC for normal operation
MIXQoutp
16
O
Mixer Q output: positive terminal (test pin). NC for normal operation
REXT
20
O
Reference-bias external resistor: 30 kΩ; used to set the bias of internal circuits of chip
STROBE
46
I
SPI enable (latches data into SPI after final clock pulse. Logic level = 1.
VCCBBQ
25
Baseband Q-chain power supply, 4.5 V to 5.5 V. Decoupled from other sources
VCCBIAS
21
Bias-block power supply, 4.5 V to 5.5 V. Decoupled from other sources
VCCDIG
2
Digital power supply, 4.5 V to 5.5 V. Decoupled from other sources
VCCLO
29
Local oscillator power supply, 4.5 V to 5.5 V. Decoupled from other sources
VCCMIX
4, 9
Mixer power supply, 4.5 V to 5.5 V. Decoupled from other sources
VCMQ
24
I
Baseband Q-chain input common mode, nominally 1.5 V
VOFFQ
23
I
Q-chain analog-offset correction input, 0 V to 3 V.
VCCBBI
36
VCMI
37
I
Baseband I chain input common mode, nominally 1.5 V
VOFFI
38
I
I-chain analog-offset correction input, 0 V to 3 V
Baseband I power supply, 4.5 V to 5.5 V. Decoupled from other sources
THERMAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
Soldered slug, no airflow
RθJA
Thermal derating, junction-to-ambient
RθJA (2)
RθJB
(1)
(2)
Thermal derating, junction-to-board
MIN
TYP
MAX
UNIT
26
Soldered slug, 200-LFM (1,016 m/s) airflow
20.1
Soldered slug, 400-LFM (2,032 m/s) airflow
17.4
7-mm × 7-mm, 48-pin PDFP
25
7-mm × 7-mm, 48-pin PDFP
12
°C/W
°C/W
Determined using JEDEC standard JESD-51 with high-K board
16 layers, high-K board
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply voltage range (2)
–0.3 to 5.5
V
Digital I/O voltage range
–0.3 to VCC + 0.5
V
TJ
Operating virtual junction temperature range
–40 to 150
°C
TA
Operating ambient temperature range
–40 to 85
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
VCC
Power supply voltage
MIN
NOM
4.5
5
Power supply voltage ripple
MAX
UNIT
5.5
V
940
µVpp
TA
Operating ambient temperature range
–40
85
°C
TJ
Operating virtual junction temperature range
–40
150
°C
MAX
UNIT
ELECTRICAL CHARACTERISTICS
Power supply = 5 V, LO = 0 dBm at 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
DC PARAMETERS
ICC
Total supply current
360
mA
Power-down current
5
mA
IQ DEMODULATOR AND BASEBAND SECTION
fRF
Frequency range
GminBB
Minimum gain
GmaxBB
Maximum gain
1700
43
Gain range
22
IIP3BB
Noise figure
Third-order input intercept
point
Gain setting = 15
Gain setting = 15
(3) (4)
OIP3BB
Output third intercept point
Gain setting = 15; two tones, 1 VPP each
OIP1BB
Output compression point
One tone (6)
IIP2BB
Second-order input intercept
point
fLPF
Baseband low-pass filter cutoff
1-dB point (8)
frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
dB
45
dB
24
13.5
dB
Gain setting = 15
dB
14.5
21
(5)
(7)
dB
dBm
32
dBVrms
3
dBVrms
60
0.615
MHz
20
1 (2)
Gain step
NFBB
2000
dBm
1.92
MHz
Balun used for measurements: Band 1: 1700-MHz balun = Murata LDB211G8005C-001; Band 2: 1800- to 1900-MHz balun = Murata
LDB211G9005C-001
Between two consecutive gain settings
Two CW tones of –30 dBm at ±900-kHz and ±1.7-MHz offset (baseband filter 1-dB cutoff frequency of minimum LPF).
Two CW tones of –30 dBm at ±2.7-MHz and ±5.9-MHz offset (baseband filter 1-dB cutoff frequency of maximum LPF).
Two CW tones at an offset from LO frequency smaller than the baseband filter cutoff frequency.
Single CW tone at an offset from LO smaller than the baseband filter cutoff frequency.
Two tones at fRF1 = fLO ± 900 kHz and fRF2 = fLO ± 1 MHz; IM2 product measured at 100-kHz output frequency (for minimum baseband
filter 1-dB cutoff frequency). The two tones are at fRF1 = fLO ± 2.7 MHz and fRF2 = fLO ± 2.8 MHz, and the IM2 product measured at
100-kHz output frequency (for maximum baseband filter 1-dB cutoff frequency).
Baseband low-pass filter 1-dB cutoff frequency is programmable through SPI between minimum and maximum values.
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
Power supply = 5 V, LO = 0 dBm at 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
615 kHz
Baseband relative attenuation
at minimum LPF cutoff
frequency (9)
900 kHz
10
1.7 MHz
50
5 MHz
100
1
2.7 MHz
10
5 MHz
50
20 MHz
Baseband filter amplitude
ripple
(10)
(10)
Sideband suppression
Output load impedance
Output common mode
1.8
Degrees
0.5
dB
35
Parallel resistance
Measured at I and Q channel baseband outputs
dB
1
Parallel capacitance
VCM
dB
100
RMS phase deviation from linear phase
See
dB
60
1.92 MHz
Baseband filter phase linearity
UNIT
1
20 MHz
Baseband relative attenuation
at maximum LPF cutoff
frequency (9)
MAX
kΩ
20
0.7
1.5
pF
4
V
LOCAL OSCILLATOR PARAMETERS
Local oscillator frequency
1700
LO input level
LO leakage
2000
0
At MIXinn/p
MHz
dBm
–58
dBm
VCC
V
0.8
V
DIGITAL INTERFACE
VIH
High-level input voltage
2
VIL
Low-level input voltage
0
VOH
High-level output voltage
VOL
Low-level output voltage
5
0.8 VCC
V
0.2 VCC
V
(9) Attenuation relative to passband gain
(10) Across-filter passband: 615 kHz (minimum baseband filter cutoff frequency) and 1.92 MHz (maximum baseband filter cutoff frequency).
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TIMING REQUIREMENTS
Power supply = 5 V, LO = 0 dBm at 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(CLK)
Clock period
50
ns
tsu1
Setup time, data
10
ns
th
Hold time, data
10
ns
tw
Pulse width, STROBE
20
ns
tsu2
Setup time, STROBE
10
ns
tsu1
th
t(CLK)
First Clock Pulse
CLOCK
DATA
DB0 (LSB)
Address Bit 1
DB1
Address Bit 2
DB2
Cmd Bit 3
DB3
Cmd Bit 4
DB29
Cmd Bit 30
DB30
Cmd Bit 31
DB31 (MSB)
Cmd Bit 32
tsu2
tw
STROBE
Figure 1. Serial Programming Timing
6
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS
VCC = 5 V, TA = 25°C, 1950 MHz, gain setting = 24 (unless otherwise stated).
(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
GAIN vs FREQUENCY
GAIN vs GAIN STATE
44
45
43
CDMA
CDMA
–40°C
41
43.5
39
37
–40°C
Gain – dB
Gain – dB
35
43
42.5
25°C
33
31
29
27
85°C
25
25°C
23
42
21
19
17
85°C
41.5
1820
1840
1860
1880 1900
1940
f – Frequency – MHz
1960
1980
15
2000
0
2
4
6
8
10 12
14
Gain State
Figure 2.
IIP3 vs FREQUENCY
CDMA
28
85°C
25°C
5.5 V
5V
24
IIP3 – dBm
IIP3 – dBm
24
WCDMA
26
24
22
20
22
20
4.5 V
18
18
16
16
14
14
12
12
10
1690 1700 1710 1720
10
1730 1740 1750 1760 1770
f – Frequency – MHz
1780 1790
1820
1840
1860
1880
Figure 4.
1900 1920 1940
f – Frequency – MHz
1960
1980
2000
1960
1980
2000
Figure 5.
IIP3 vs FREQUENCY
IIP3 vs FREQUENCY
30
30
WCDMA
28
26
WCDMA
26
24
85°C
25°C
24
22
IIP3 – dBm
IIP3 – dBm
22
IIP3 vs FREQUENCY
–40°C
20
20
30
26
28
18
Figure 3.
30
28
16
25°C
–40°C
18
22
85°C
20
18
–40°C
16
16
14
14
12
12
10
1690
1700 1710 1720 1730 1740 1750 1760 1770 1780 1790
f – Frequency – MHz
10
1820
1840
Figure 6.
1860
1880
1900
1920
1940
f – Frequency – MHz
Figure 7.
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SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, TA = 25°C, 1950 MHz, gain setting = 24 (unless otherwise stated).
(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
IIP2 vs FREQUENCY
IIP2 vs FREQUENCY
80
78
80
78
76
4.5 V
74
85°C
25°C
72
70
72
68
68
70
IIP2 – dBm
IIP2 – dBm
76
74
66
64
–40°C
62
60
58
5.5 V
66
5V
64
62
60
58
56
56
54
54
52
WCDMA
52
50
1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790
f – Frequency – MHz
50
1820
WCDMA
1840
1860
Figure 8.
IIP2 vs FREQUENCY
2000
IIP2 vs FREQUENCY
85°C
78
76
WCDMA
–40°C
76
74
74
25°C
72
72
70
70
IIP2 – dBm
IIP2 – dBm
1980
80
78
68
66
64
–40°C
68
66
62
60
60
58
58
56
56
54
WCDMA
52
50
1690
1700 1710
1720 1730 1740 1750 1760
f – Frequency – MHz
52
50
1820
1770 1780 1790
25°C
64
62
54
85°C
1840
1860
Figure 10.
1880 1900 1920 1940
f – Frequency – MHz
1960
1980
2000
Figure 11.
OIP3 vs FREQUENCY
OIP3 vs FREQUENCY
40
40
CDMA
38
38
25°C
36
WCDMA
25°C
36
85°C
85°C
34
OIP3 – dBVrms
34
OIP3 – dBVrms
1960
Figure 9.
80
32
30
–40°C
28
32
30
26
24
24
22
22
1840
1860
1880 1900 1920 1940
f – Frequency – MHz
1960
1980
2000
–40°C
28
26
20
1820
20
1820
1840
Figure 12.
8
1880 1900 1920 1940
f – Frequency – MHz
1860
1880 1900 1920 1940
f – Frequency – MHz
1960
1980
2000
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, TA = 25°C, 1950 MHz, gain setting = 24 (unless otherwise stated).
(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
OIP3 vs GAIN STATE
OIP3 vs GAIN STATE
40
40
WCDMA
38
25°C
36
85°C
34
OIP3 – dBVrms
34
OIP3 – dBVrms
CDMA
38
25°C
36
32
30
–40°C
28
32
85°C
30
28
26
26
24
24
22
22
20
–40°C
20
0
5
10
15
Gain State
20
25
0
30
5
10
Figure 14.
OIP3 vs LO POWER
30
4
6
IIP3 vs LO POWER
WCDMA
WCDMA
30
35
25
IIP3 – dBm
OIP3 – dBVrms
25
35
40
30
20
25
15
20
10
–4
–2
0
2
LO Power – dBm
4
5
–6
6
–4
–2
Figure 16.
0
2
LO Power – dBm
Figure 17.
IIP2 vs LO POWER
GAIN ERROR vs GAIN STATE
75
70
20
Figure 15.
45
15
–6
15
Gain State
0.018
WCDMA
1850 MHz
0.016
65
0.014
60
0.012
Gain Error – dB
IIP2 – dBm
55
50
45
40
35
0.01
0.008
0.006
0.004
30
25
0.002
20
0
15
–6
–4
–2
0
LO Power – dBm
2
4
6
–0.002
0
5
10
15
20
25
Gain State
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, TA = 25°C, 1950 MHz, gain setting = 24 (unless otherwise stated).
(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
GAIN vs BASEBAND FREQUENCY
GAIN vs BASEBAND FREQUENCY
42.6
60
Filter Gain Shape
25°C, (1.92 MHz)
BB Filter Setting = 7
40
Filter Gain Shape
25°C, (1.92 MHz)
BB Filter Setting = 7
42.5
42.4
42.3
0
Gain – dB
Gain – dB
20
Filter Gain Shape
25°C, (615 KHz)
BB Filter Setting = 90
–20
Filter Gain Shape
25°C, (615 KHz)
BB Filter Setting = 90
42.2
42.1
42
41.9
–40
41.8
–60
41.7
–80
0.01
0.1
1
10
41.6
0.01
100
0.1
Baseband Frequency – MHz
Figure 20.
10
Figure 21.
CORNER FREQUENCY vs BB – FREQUENCY SETTING
INTEGRATED NF vs GAIN STATE
3
30
CDMA Mode
1950 MHz
25°C
1 dB
5V
25°C
1950 MHz
2.5
25
2
4.5 V
Noise Figure – dB
f – Frequency – MHz
1
Baseband Frequency - MHz
1.5
1
20
5.5 V
15
5V
0.5
0
10
0
16
32
48
64
80
96
112
0
128
5
10
15
BB – Frequency Setting
Gain State
Figure 22.
Figure 23.
20
25
INTEGRATED NF vs GAIN STATE
30
CDMA Mode
1950 MHz
5V
Noise Figure – dB
25
85°C
20
25°C
–40°C
15
10
0
5
10
15
20
25
Gain State
Figure 24.
10
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TYPICAL CHARACTERISTICS
HISTOGRAM PLOTS
CONVERSION GAIN DISTRIBUTION
IIP3 DISTRIBUTION
80
60
CDMA
50
60
Distribution – %
Distribution – %
40
30
20
40
20
10
0
42.6
42.8
43
43.2
43.4
43.6
0
18.5
43.8
19
19.5
20
Gain – dB
Figure 25.
20.5
21
21.5
IIP3 – dBm
22
22.5
23
Figure 26.
IIP2 DISTRIBUTION
OIP3 DISTRIBUTION
35
40
CDMA
CDMA
30
WCDMA
WCDMA
25
Distribution – %
Distribution – %
30
20
20
15
10
10
5
0
54
58
62
66
70
IIP2 – dBm
74
78
0
29
82
30
31
Figure 27.
32
33
OIP3 – dBVrms
34
35
36
Figure 28.
NF DISTRIBUTION
70
60
Distribution – %
50
40
30
20
10
0
12.75
13
13.25
13.5
NF – dB
13.75
14
14.25
Figure 29.
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SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
The TRF3710 features a 3-wire serial programming interface (SPI) that controls an internal 32-bit shift register.
There are a total of three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin
46). DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of the CLOCK. STROBE is
asynchronous to CLOCK, and at its rising edge, the data in the shift register are loaded onto the selected internal
register. The first two bits (DB0–DB1) are the address to select the available internal registers. Figure 30 shows
the serial interface timing for the TRF3710.
tsu1
th
t(CLK)
First Clock Pulse
CLOCK
DATA
DB0 (LSB)
Address Bit 1
DB1
Address Bit 2
DB2
Cmd Bit 3
DB3
Cmd Bit 4
DB29
Cmd Bit 30
DB30
Cmd Bit 31
DB31 (MSB)
Cmd Bit 32
tsu2
tw
STROBE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(CLK)
Clock period
50
ns
tsu1
Setup time, data
10
ns
th
Hold time, data
10
ns
tw
Pulse width, STROBE
20
ns
tsu2
Setup time, STROBE
10
ns
Figure 30. Serial Interface Timing
12
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Register 0
Register Address
Bit0
Bit1
PWD
Mixer
PWD
LO Buff
PWD
Test
Buff
PWD
Filter
PWD
Output
Buff
RSVD
PWD
Dig Cal
Block
PWD
Ana
Cal
Block
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Baseband Freq Cutoff Settings Cont.
Bit16
Bit17
Bit18
Bit19
Bit20
RSVD
Bit21
Bit22
Bit23
Bit10
DC Detector
Bandwidth
Bit24
BB
Freq
Cutoff
Set
Baseband Gain Setting
Bit25
Bit11
Bit12
RSVD
Bit26
Bit27
Bit28
Bit13
Bit14
Bit15
Cal
Reset
Spare
Spare
Bit29
Bit30
Bit31
Figure 31. Register 0 Map
Table 1. Register 0: Device Setup
REGISTER 0
NAME
RESET
VALUE
WORKING DESCRIPTION
Bit0
ADDR_0
0
Bit1
ADDR_1
0
Bit2
PWD_MIX
0
Mixer power down (off = 1)
Bit3
PWD_LO
0
LO buffer power down (off = 1)
Bit4
PWD_BUF1
1
Test buffer power down (off = 1)
Bit5
PWD_FILT
0
Baseband filter power down (off = 1)
Bit6
PWD_BUF2
0
Output buffer power down (off = 1)
Bit7
Reserved
0
Bit8
PWD_DC_OFF_DIG
1
Digital calibration blocks power down (off = 1)
Bit9
PWD_DC_OFF_ANA
1
Analog calibration blocks power down (off = 1)
Bit10
BBGAIN_0
1
Bit11
BBGAIN_1
1
Bit12
BBGAIN_2
1
Bit13
BBGAIN_3
1
Bit14
BBGAIN_4
0
Sets baseband gain: the default power-on BBGAIN setting = 15 (corresponding to a
typical gain of 34 dB). There are 25 gain settings (0 to 24) in 1-dB increments. For a
desired device gain, the BBGAIN setting is determined by the following equation:
BBGAIN setting = 24 – [(typical device gain at BBGAIN = 24) – (desired device
gain)]. For example, for a desired device gain of 27 dB, the BBGAIN setting would
be 24 – (43 – 27) = 8, which is bits 14–10 .
Bit15
BBFREQ_0
1
Bit16
BBFREQ_1
0
Bit17
BBFREQ_2
1
Bit18
BBFREQ_3
0
Bit19
BBFREQ_4
1
Bit20
BBFREQ_5
0
Bit21
BBFREQ_6
1
Bit22
Reserved
1
Bit23
Reserved
0
Bit24
EN_FLT_B0
0
Bit25
EN_FLT_B1
0
Bit26
Reserved
0
Bit27
Internal use only
0
Bit28
Internal use only
0
Bit29
CAL_RESET
0
Bit30
Spare0
0
Bit31
Spare1
0
Address bits
Sets BB frequency cutoff; default = 85. Example: For CDMA, the corner frequency is
615 kHz. See the 1-dB corner frequency vs. frequency setting plot Figure 22 to
determine the setting, which is 90. Then set bit 15 through bit 21 to ,
which corresponds to 90.
DC detector bandwidth
Reset the internal calibration logic when = 1.
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•
•
•
Baseband PGA gain: BBGAIN_[4:0] (B[14:10]) sets the gain of the baseband programmable gain amplifier.
The acceptable values are from to . (See the Gain Control section for more information.)
Baseband filter cutoff frequency: BBFREQ_[6:0] (B[21:15]) controls the baseband 1-dB cutoff frequency.
An all-0s word sets the filter to its maximum cutoff frequency, whereas an all-1s word corresponds to
minimum filter bandwidth.
EN_FLT_B[0:1]: These bits control the bandwidth of the detector used to measure the dc offset during the
automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0
controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB
cutoff frequencies of the detector bandwidth are summarized in Table 2 (see the Application Information
section for more detail on the dc offset calibration and the detector bandwidth).
Table 2. Typical Cutoff Frequencies
14
EN_FLT_B1
EN_FLT_B0
Typical 3-dB Cutoff
Frequency
X
0
10 MHz
Maximum bandwidth; bypass R, C
0
1
10 kHz
Enable R
1
1
1 kHz
Minimum bandwidth; enable R, C
Notes
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Register 1
Register Address
Bit0
Bit1
Autocal
Enable
Autocal
Bit2
Bit3
Bit17
Bit4
Bit5
Bit6
DC Offset Digital
Cal. Resolution
for I Channel
DAC Bits CONT
Bit16
DAC Bits to Be Set During Manual Cal I/Q
Bit18
Bit19
Bit20
Bit21
Bit7
DC Offset Digital
Cal. Resolution
for Q Channel
Bit22
Bit23
Bit8
Bin
Search
Bit24
Bit9
Bit10
Bit11
Division Ratio for Clock
Divider
Bit25
Bit26
Bit27
Bit12
Cal Clk
Select
Bit28
Bit13
Bit14
Bit15
Internal Osc Freq Trimming
Bit29
Bit30
Bit31
Figure 32. Register 1 Map
Table 3. Register 1: Device Setup
REGISTER 1
NAME
RESET
VALUE
WORKING DESCRIPTION
Bit0
ADDR_0
1
Bit1
ADDR_1
0
Bit2
AUTO_CAL
1
Auto dc offset correction when = 1; otherwise manual
Bit3
EN_AUTOCAL
0
Autocalibration begins when bit = 1. This bit is reset after calibration completes.
Bit4
IDAC_BIT0
0
Bit5
IDAC_BIT1
0
Bit6
IDAC_BIT2
0
Bit7
IDAC_BIT3
0
Bit8
IDAC_BIT4
0
Bit9
IDAC_BIT5
0
Bit10
IDAC_BIT6
0
Bit11
IDAC_BIT7
1
Bit12
QDAC_BIT0
0
Bit13
QDAC_BIT1
0
Bit14
QDAC_BIT2
0
Bit15
QDAC_BIT3
0
Bit16
QDAC_BIT4
0
Bit17
QDAC_BIT5
0
Bit18
QDAC_BIT6
0
Bit19
QDAC_BIT7
1
Bit20
IDET_B0
1
Bit21
IDET_B1
1
Bit22
QDET_B0
1
Bit23
QDET_B1
1
Bit24
Bin Search
1
Bit25
CLK_DIV_RATIO0
0
Bit26
CLK_DIV_RATIO1
0
Bit27
CLK_DIV_RATIO2
0
Bit28
CAL_CLK_SEL
1
Bit29
OSC_TRIM0
1
Bit30
OSC_TRIM1
1
Bit31
OSC_TRIM2
0
Address bits
DAC bits to be set during manual cal I/Q
Set the dc offset digital calibration resolution for I channel.
Set the dc offset digital calibration resolution for Q channel.
Set to 1 for autocalibration; set to 0 for manual control.
DC offset autocalibration clock divider:
division ratios = 1, 8, 16, 128, 256, 1024, 2048, 16,684
Select internal oscillator when 1; select SPI clock when 0.
Internal oscillator frequency trimming
000 → 300 kHz
111 → 1.8 MHz
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•
•
•
•
•
•
16
AUTO_CAL (Bit2): When 1, the dc offset autocalibration is selected.
EN_AUTOCAL (Bit3): Setting this bit to 1 starts the dc offset autocalibration. At the end of the calibration, the
bit is reset to 0 (see the Application Information section for more details on dc offset correction).
IDET_B[1:0], QDET_B[1:0]: These bits control the maximum output dc voltage of the dc-offset correction
DAC (I and Q channels).
CLK_DIV_RATIO[2:0]: Frequency divider for the calibration clock. The incoming clock (either the serial
interface clock or the internal oscillator) divided by the divider ratio set by bits 25–27, generates the reference
clock used during the autocalibration.
CAL_CLK_SEL: Selects the internal oscillator or the external SPI clock as calibration clock
OSC_TRIM[2:0]: Bits 29–31 control the internal oscillator frequency.
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APPLICATION INFORMATION
GAIN CONTROL
The TRF3710 integrates a baseband programmable-gain amplifier (PGA) that provides 24 dB of gain range with
1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 0, bits 10–14). Alternatively, the
PGA can be programmed by a combination of 5 bits programmed through the SPI and three parallel external bits
(pins Gain_B2, Gain_B1, Gain_B0). The parallel bits allow a fast gain change (0 db to 7 dB by 1-dB steps)
without the need to reprogram the SPI registers.
The PGA gain control word (BBGAIN[0:4]) can be programmed to a setting between 0 and 24. This word is the
sum of the SPI programmed gain (register 0, bits 10–14) and the parallel external 3 bits as shown in Figure 33.
Setting the PGA gain setting above 24 is not valid. Typical applications set the PGA gain to 15, which allows
room to adjust the PGA gain up or down to maintain desired output signal to the analog-to-digital converter over
all conditions.
From SPI
Register 0, Bits 0–4
+
BBgain[0:4]
To PGA
Fgain[0:2]
From External Pins
Figure 33. PGA Gain Control Word
For example, if a PGA gain setting of 20 dB is desired, then the SPI can be programmed directly to 20.
Alternatively, the SPI gain register can be programmed to 15 and the parallel external bits set to 101 (binary),
corresponding to an additional 5 dB.
AUTOMATED DC OFFSET CALIBRATION
The TRF3710 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q paths.
The digital dc offset correction is engaged by setting the PWD_DC_OFF_DIG (register 0, bit 8) to 0 and the
PWD_DC_OFF_ANA (register 0, bit 9) to 1. The internal calibration requires a clock in order to function.
TRF3710 can use the internal relaxation oscillator or the external SPI clock. Using the internal oscillator is the
preferred method. Selecte the internal oscillator by setting the Cal_Sel_Clk (register 1, bit 28) to 1. The internal
oscillator frequency is set through the OSC_TRIM bits (register 1, bits 29–31). The frequency of the oscillator is
detailed in Table 4.
Table 4. Internal Oscillator Frequency Control
OSC_TRIM2
OSC_TRIM1
OSC_TRIM0
Frequency
0
0
0
300 kHz
0
0
1
500 kHz
0
1
0
700 kHz
0
1
1
900 kHz
1
0
0
1.1 MHz
1
0
1
1.3 MHz
1
1
0
1.5 MHz
1
1
1
1.8 MHz
The default setting of these registers corresponds to 900-kHz oscillator frequency; this setting is sufficient for
autocalibration and does not need to be modified.
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The internal dc offset correction DACs output full scale range is programmable (IDET_B[0:1] and QDET_B[0:1],
register 1, bits 20–23). The range is shown in Table 5.
Table 5. DC Offset Correction DAC Programmable
Range
I(Q)DET_B1
I(Q)DET_B0
Full Scale
0
0
10 mV
0
1
20 mV
1
0
30 mV
1
1
40 mV
The maximum dc offset correction range can be calculating by multiplying the values in Table 5 by the baseband
PGA gain. The LSB of the digital correction depends on the programmed maximum correction range. For
optimum resolution and best correction, the dc offset DAC range should be set to 10 mV for both the I and Q
channels with the PGA gain set for the nominal condition. The output of the dc-offset-correction DAC is affected
by a change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGA
gain during normal operation does not significantly impair the dc offset balance. For example, if the optimized
calibration yields a dc offset balance of 2 mV at a gain setting of 17, then the dc offset maintains less than 10-mV
balance as the gain is adjusted ±7 dB.
The dc offset correction DACs are programmed from the internal registers when the AUTO_CAL bit (register 1,
bit 2) is set to 1. At start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of
128. When an autocalibration is desired, verify that the Bin_Search bit (register 1, bit 24) is set to 1. Initiate the
autocalibration process by toggling the EN_AUTOCAL bit (register 1, bit 3) to 1. When the calibration is over, this
bit is automatically reset to 0. During calibration, the RF local oscillator must be applied.
At each clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset and
calculates the new dc current for the DAC. After the ninth clock cycle, the calibration is complete and the
AUTO_CAL bit is reset to 0. The dc offset DAC state is stored in the internal registers and maintained as long as
the power supply is kept on, or until the Cal Reset (register 1, bit 29) is toggled to 1 or a new calibration is
started.
The required clock speed for the optimum calibration is determined by the internal detector behavior (integration
bandwidth, gain, sensitivity). The input bandwidth of the detector can be adjusted by changing the cutoff
frequency of the RC low-pass filter in front of the detector (register 0, bits 24–25), corresponding to 3-dB
corner-frequency steps of 10 MHz, 10 kHz, and 1 kHz. The speed of the clock can be slowed down by
selecting a clock divider ratio (register 1, bits 25–27).
The detector has more averaging time the slower the clock; therefore, it can be desirable to slow down the clock
speed for a given condition to achieve optimum results. For example, if there is no RF present on the RF input
port, the detection filter can be left wide (10 MHz) and the clock divider can be left at div-by-1. The
autocalibration yields a dc offset balance between the differential baseband output ports (I and Q) that is less
than 15 mV. Some minor improvement may be obtained by increasing the averaging of the detector by
increasing the clock divider up to 256.
However, if there is a modulated RF signal present at the input port, it is desirable to reduce the detector
bandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1-kHz corner
frequency. With the modulated signal present, and with the detection bandwidth reduced, additional averaging is
required to get optimum results. A clock divider setting of 1024 yields optimum results.
An increase in the averaging is possible by increasing the clock divider at the expense of longer converging time.
The convergence time can be calculated by the following:
(Auto_Cal_Clk_Cycles) (Clk_Divider)
tc +
Osc_Freq
(1)
18
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With a clock divider of 1024 and with the nominal oscillator frequency of 900 kHz, the convergence time is:
(9) (1024)
tc +
+ 10.24 ms
900 kHz
(2)
ALTERNATE METHOD FOR ADJUSTING DC OFFSET
The internal registers controlling the internal dc current DAC are accessible through the SPI, providing a
user-programmable method for implementing the dc offset calibration. To employ this option, the Auto Cal bit
must be set to 0 and the Bin_Search set to 0. During this calibration, an external instrument monitors the output
dc offset between the I/Q differential outputs and programs the internal registers (IDAC_BIT[0:7] and
QDAC_BIT[0:7] bits, register 1, bits 4–19) to cancel the dc offset.
The TRF3710 also offers a third dc offset calibration option to control the output dc offset by an external voltage
(0–3 V) injected at the VOFFI and VOFFQ pins. Set PWD_DC_OFF_DIG (register 0, bit 8) to 1 (Off) and set
PWD_DC_OFF_ANA (register 0, bit 9) to 0 to engage the external analog voltage control of the output dc offset.
The analog voltage at the VOFFI and VOFFQ pins can be adjusted to provide the proper dc offset balance.
PCB LAYOUT GUIDELINES
The TRF3710 device is designed with a ground slug on the back of the package that must be soldered to the
printed-circuit board (PCB) ground with adequate ground vias to ensure a good thermal and electrical
connection. The recommended via pattern and ground pad dimensions are shown in Figure 34. The
recommended via diameter is 8 mils (0.203 mm). The ground pins of the device can be directly tied to the ground
slug pad for a low-inductance path to ground. Additional ground vias may be added if space allows. The NC (no
connect) pins can also be tied to the ground plane.
Decoupling capacitors at each of the supply pins is recommended. The high-frequency decoupling capacitors for
the RF mixers (VCCMIX) should be placed close to the respective pins. The value of the capacitor should be
chosen to provide a low impedance RF path to ground at the frequency of operation. Typically, this value is
around 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close to the
respective pins as possible.
The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCB
layout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. The I/Q
output traces should be routed as differential pairs and the lengths all kept equal to each other. Decoupling
capacitors for the supply pins should be kept symmetrical where possible. The RF differential input lines related
to the RF input and the LO input should also be routed as differential lines with the respective lengths kept equal.
If an RF balun is used to convert a single-ended input to a differential input, then the RF balun should be placed
close to the device. Implement the RF balun layout according to the manufacturer’s guidelines to provide best
gain and phase balance to the differential outputs. On the RF traces, maintain proper trace widths to keep the
characteristic impedance of the RF traces at a nominal 50 Ω.
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0.200 (5,08)
0.025 (0,635)
Ø 0.008 (0,203)
0.025
(0,635)
0.200
(5,08)
0.0125
(0,318)
Dimensions: inches (mm)
Figure 34. PCB Layout Guidelines
APPLICATION SCHEMATICS
The typical application schematic is shown in Figure 35. The RF bypass capacitors and coupling capacitors are
depicted with 10-pF capacitors. These values can be adjusted to provide the best high-frequency bypass based
on the frequency of operation.
20
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Gain_B2
Gain_B0
Gain_B1
SDAT
STROBE
SCLK
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
C1
0.1 mF
2
0.1 mF
CHIP_EN
C4
10 pF
7
37
VCMI
38
VOFFI
39
Gain_B2
Gain_B1
41
Gain_B0
40
42
NC
43
NC
44
MIXIoutn
MIXIoutp
45
46
DATA
MIXinp
LOip
U1
TRF3710
MIXinn
LOin
8 NC
NC
AGND
C2
35
1000 pF
34
BBIP
33
BBIN
VCCBBQ
To ADC I
32
31
LOP
30
LON
29
28
BBQP
27
BBQN
To SYNTHESIZER
VCC
C8
10 pF
To ADC Q
26
C10
25
VCMQ
1000 pF
VCC
24
VOFFQ
23
22
21
20
NC
14
13
NC
NC
GNDBIAS
BBQoutn
VCCBIAS
NC
REXT
BBQoutp
NC
11
12
VCCMIX
19
9
10
VCCLO
NC
10 pF
NC
NC
MIXQoutn
VCC
BBIoutn
18
C9
C7
VCCMIX
17
LDB21
6
BBIoutp
MIXQoutp
10 pF
10 pF
CHIP_EN
16
C6
C5
36
AGND
NC
RF in
5
VCC
VCC
VCCBBI
VCCDIG
15
10 pF
B1
3
4
STROBE
VCC
CLOCK
48
C3
1 GNDDIG
47
ADC_CM(~1.5V)
ADC_CM(~1.5V)
R1
30 kW
VCC
C11
0.1 mF
C12
0.1 mF
Figure 35. TRF3710 Application Schematic
The RF input port and the RF LO port require differential input paths. Single-ended RF inputs to these ports can
be converted with an RF balun that is centered on the band of interest. Linearity performance of the TRF3710
depends on the amplitude and phase balance of the RF balun; therefore, care should be taken with the selection
of the balun device and with the RF layout of the device. The recommended RF balun devices are listed in
Table 6.
Table 6. Recommended RF Balun Devices
MANUFACTURER
PART NUMBER
FREQUENCY RANGE (MHz)
UNBALANCE
IMPEDANCE
BALANCE
IMPEDANCE
Murata
LDB211G8005C-001
1800 ±100 MHz
50 Ω
50 Ω
Murata
LDB211G9005C-001
1900 ±100 MHz
50 Ω
50 Ω
ADC INTERFACE
The TRF3710 has an integrated ADC driver buffer that allows direct connection to an analog-to-digital converter
(ADC) without additional active circuitry. The common-mode voltage generated by the ADC can be directly
supplied to the TRF3710 through the VCMI/Q pins (pins 24, 37). Otherwise, a nominal common-mode voltage of
1.5 V should be applied to those pins. The TRF3710 device can operate with a common-mode voltage from 1.5
V to 2.8 V without any impairment to the output performance. Figure 36 illustrates the degradation of the output
compression point as the common mode voltage exceeds those values.
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3.5
3
P1dB – dBVrms
2.5
2
1.5
1
0.5
0
0.5
1
1.5
2
2.5
3
3.5
VCM – Common-Mode Voltage – V
Figure 36. P1dB Performance vs Common-Mode Voltage
APPLICATION FOR A HIGH-PERFORMANCE RF RECEIVER SIGNAL CHAIN
The TRF3710 is the centerpiece component in a high-performance direct downconverting receiver. The device is
a highly integrated direct downconverting demodulator that requires minimal additional devices to complete the
signal chain. A signal chain block diagram example is shown in Figure 37.
ADS5232
TRF371x
12
0
90
LNA
12
TRF3761
Figure 37. Block Diagram of Direct Downconverting Receiver
The lineup requires a low-noise amplifier (LNA) that operates at the frequency of interest with typical 1-db to
2-dB noise-figure (NF) performance. An RF band-pass filter (BPF) is selected at the frequency band of interest to
eliminate unwanted signals and images outside the band from reaching the demodulator. The TRF3710
incorporates the direct downconverter demodulation, baseband filtering, and baseband gain control functions. An
external synthesizer, such as the TRF3761, provides the local oscillator (LO) source to the TRF3710. The
differential outputs of the TRF3761 directly mate with the LO inputs of the TRF3710. The quadrature outputs
(I/Q) of the TRF3710 directly drive the input to the ADC. A dual ADC such as the ADS5232 12-bit, 65-MSPS
ADC mates perfectly with the differential I/Q output of the TRF3710. In addition, the common-mode output
voltage generated by the ADS5232 is fed directly into the common-mode ports (pins 24, 37) to ensure the
optimum dynamic range of the ADC is maintained.
22
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3710
TRF3710
www.ti.com
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
The cascaded performance of the TRF3710 with the ADS5232 and the TRF3761 was measured with WCDMA
modulated signals. A single channel WCDMA receive signal was injected into the TRF3710 at –100 dBm. This
power roughly corresponds to typical levels this device would see at sensitivity when an appropriate LNA and
filter are used. The error-vector magnitude (EVM) of the RX channel was measured as a gauge of the system
performance. The EVM percentage at –100 dBm is approximately 27.6% at 60 ksym/s. This result correlates with
the required signal-to-noise ratio (SNR) for the device with an appropriate LNA to meet or exceed the bit error
rate (BER) specification of 0.1% according to the standards at the input sensitivity level.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3710
23
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TRF3710IRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-40 to 85
TRF
3710
TRF3710IRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-40 to 85
TRF
3710
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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