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UCC27531-Q1
SLVSC82B – AUGUST 2013 – REVISED OCTOBER 2015
UCC27531-Q1 2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Low Cost Gate Driver (Offering Optimal Solution
for Driving Fet And Igbts)
Superior Replacement to Discrete Transistor Pair
Drive (Providing Easy Interface With Controller)
TTL and CMOS Compatible Input Logic
Threshold, (Independent of Supply Voltage)
Split Output Options Allow for Tuning of Turn-On
and Turn-Off Currents
Enable with Fixed TTL Compatible Threshold
High 2.5-A Source and 5-A Sink Peak Drive
Currents at 18-V VDD
Wide VDD Range From 10 V up to 35 V
Input and Enable Pins Capable of Withstanding up
to –5-V DC Below Ground
Output Held Low When Inputs are Floating or
During VDD UVLO
Fast Propagation Delays (17-ns Typical)
Fast Rise and Fall Times
(15-ns and 7-ns Typical With 1800-pF Load)
Undervoltage Lockout (UVLO)
Used as a High-Side or Low-Side Driver (if
Designed With Proper Bias and Signal Isolation)
Low-Cost, Space-Saving 6-Pin DBV (SOT-23)
Package Options
Operating Temperature Range of –40°C to 140°C
Automotive
Switch-Mode Power Supplies
DC-to-DC Converters
Solar Inverters, Motor Control, UPS
HEV and EV Chargers
Home Appliances
Renewable Energy Power Conversion
SiC FET Converters
3 Description
The UCC27531-Q1 is a single-channel, high-speed,
gate driver capable of effectively driving MOSFET
and IGBT power switches by using up to 2.5-A
source and 5-A sink (asymmetrical drive) peak
current. Strong sink capability in asymmetrical drive
boosts immunity against parasitic Miller turn-on effect.
The UCC27531-Q1 device can also feature a splitoutput configuration where the gate-drive current is
sourced through the OUTH pin and sunk through the
OUTL pin. This pin arrangement allows the user to
apply independent turn-on and turn-off resistors to the
OUTH and OUTL pins respectively and easily control
the switching slew rates.
The driver has rail-to-rail drive capability and an
extremely small propagation delay of typically 17 ns.
The input threshold of UCC27531-Q1 is based on
TTL and CMOS compatible low-voltage logic, which
is fixed and independent of VDD supply voltage. The
1-V typical hysteresis offers excellent noise immunity.
Device Information(1)
PART NUMBER
UCC27531-Q1
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
1.6 mm × 2.9 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Driving IGBT Without Negative Bias
UCC27531-Q1
EN
1
OUTH
6
IN
+
2
OUTL
5
VDD
GND
3
+
–
4
GND
Bouncing Up
to -6.5 V
18 V
ISENSE
Controller
VCE(sense)
VCC
+
–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27531-Q1
SLVSC82B – AUGUST 2013 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Applications ................................................ 17
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
11.3 Thermal Considerations ........................................ 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2013) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Original (August 2013) to Revision A
•
2
Page
Page
Changed document from Product Preview to Production Data.............................................................................................. 1
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5 Description (continued)
The driver has the EN pin with fixed TTL compatible threshold. The EN pin is internally pulled up; pulling the EN
pin low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional
input with the same performance as the IN pin.
Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the
application diagram, timing diagram and input and output logic truth table.
Internal circuitry on the VDD pin provides an UVLO function that holds output low until VDD supply voltage is
within operating range.
The UCC27531-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over wide
temperature range of –40°C to 140°C.
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
UCC27531-Q1
EN
1
6 OUTH
IN
2
5 OUTL
VDD
3
4 GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Enable (Pull EN to GND in order to disable output, pull it high or leave open to enable
output)
EN
1
I
GND
4
—
IN
2
I
Driver non-inverting input
OUTH
6
O
2.5-A Source Current Output of driver
OUTL
5
O
5-A sink current output of driver
VDD
3
I
Bias supply input
Ground (all signals are referenced to this node)
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply voltage
VDD
–0.3
35
V
Continuous
OUTH, OUTL, OUT
–0.3
VDD + 0.3
V
Pulse
OUTH, OUTL, OUT (200 ns)
–2
VDD + 0.3
V
–5
27
V
Continuous IN, EN, IN+, IN-, IN1, IN2
Pulse IN, EN, IN+, IN-, IN1, IN2 (1.5 µs)
–6.5
27
V
Operating virtual junction temperature, TJ
–40
150
°C
Lead temperature
Soldering, 10 sec.
300
Reflow
260
Storage temperature, Tstg
(1)
(2)
(3)
–65
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage range, VDD
10
18
32
V
Ambient temperature range
–40
140
°C
Input voltage, IN, IN+, IN-, IN1, IN2
–5
25
V
Enable, EN
–5
25
V
7.4 Thermal Information
UCC27531-Q1
THERMAL METRIC
(1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
178.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
109.7
°C/W
RθJB
Junction-to-board thermal resistance
28.3
°C/W
ψJT
Junction-to-top characterization parameter
14.7
°C/W
ψJB
Junction-to-board characterization parameter
27.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
Unless otherwise noted, VDD = 18 V, TA = –40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531-Q1. Typical condition
specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 7, IN, EN = VDD
100
200
300
IN, EN = GND
100
217
300
8
8.9
9.8
V
7.3
8.2
9.1
V
BIAS CURRENTS
IDDoff
Startup current
μA
UVLO
VON
Supply start threshold
VOFF
Minimum operating voltage
after supply start
VDD_H
Supply voltage hysteresis
0.7
V
INPUT (IN)
VIN_H
Input signal high threshold,
output high
Output High, EN = HIGH
1.8
2
2.2
V
VIN_L
Input signal low threshold,
output low
Output Low, EN = HIGH
0.8
1
1.2
V
VIN_HYS
Input signal hysteresis
1
V
ENABLE (EN)
VEN_H
Enable signal high threshold
Output High
1.7
VEN_L
Enable signal low threshold
Output Low
0.8
VEN_HYS
Enable signal hysteresis
1.9
2.1
V
1
1.2
V
0.9
V
–2.5 / +5
A
OUTPUTS (OUTH/OUTL)
ISRC/SNK
Source peak current (OUTH)/
sink peak current (OUTL)
CLOAD = 0.22 µF, f = 1 kHz
VOH
OUTH, high voltage
IOUTH = –10 mA
VOL
OUTL, low voltage
IOUTL = 100 mA
ROH
OUTH, pullup resistance
ROL
OUTL, pulldown resistance
VDD 0.2
TA = 25°C, IOUT = –10 mA
TA = –40°C to 140°C, IOUT = –10 mA
TA = 25°C, IOUT = 100 mA
TA = –40°C to 140°C, IOUT = 100 mA
VDD 0.12
VDD 0.07
V
V
0.065
0.125
11
12
12.5
7
12
20
0.45
0.65
0.85
0.3
0.65
1.25
Ω
Ω
7.6 Switching Characteristics
Unless otherwise noted, VDD = 18 V, TA = –40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531-Q1. Typical condition
specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tR
Rise time
CLOAD = 1.8 nF
15
ns
tF
Fall time
CLOAD = 1.8 nF
tD1
Turn-on propagation delay
CLOAD = 1.8 nF, IN = 0 V to 5 V
17
26
ns
tD2
Turn-off propagation delay
CLOAD = 1.8 nF, IN = 5 V to 0 V
17
26
ns
7
ns
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Figure 1. Timing Diagram (OUTPUT = OUTH tied to OUTL) INPUT = IN,
(EN = VDD), or INPUT = EN, (IN = VDD)
6
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7.7 Typical Characteristics
If not specified, INPUT refers to non-inverting input
25
12
10
Fall Time (ns)
Rise Time (ns)
20
15
8
6
10
4
5
2
0
10
20
30
40
Supply Voltage (V)
0
10
Figure 2. Rise Time vs Supply Voltage
30
40
C002
Figure 3. Fall Time vs Supply Voltage
21
27
OUT RISING, IN- 5V to
0V
OUT FALLING, IN- 0V
to 5V
TurnOn
IN- Input To Output Propagation Delay (ns)
Input To Output Propagation Delay (ns)
20
Supply Voltage (V)
C001
TurnOff
19
17
25
23
21
19
17
15
0
10
20
30
40
Supply Voltage (V)
15
0
C003
10
20
30
40
Supply Voltage (V)
C001
Figure 5. IN - Propagation Delay vs Supply
Figure 4. Propagation Delay vs Supply Voltage
30
300
VDD = 10V
25
VDD = 18V
EN=IN=Vdd
VDD = 32V
EN=IN=GND
Startup Current (µA)
Supply Current (mA)
250
20
15
10
200
150
5
100
0
0
100
200
300
400
500
-50
0
50
100
150
Temperature ( °C)
Frequency (kHz)
C005
C001
Figure 6. Operating Supply Current vs Frequency
Figure 7. Start-Up Current vs Temperature
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Typical Characteristics (continued)
If not specified, INPUT refers to non-inverting input
4.5
9.6
UVLO Rising
UVLO Falling
4.3
Vdd UVLO Threshold (V)
9.2
Idd (mA)
4.1
3.9
8.8
8.4
3.7
3.5
-50
0
50
100
8
150
-50
0
Temperature ( °C)
50
100
150
7HPSHUDWXUH Û&
C006
C007
Figure 8. Operating Supply Current vs Temperature (Output
Switching)
Figure 9. UVLO Threshold Voltage vs Temperature
2.4
2.4
Enable
Turn-On
Turn-Off
2.2
2
Enable Threshold (V)
2
Input Threshold (V)
Disable
2.2
1.8
1.6
1.4
1.8
1.6
1.4
1.2
1.2
1
1
0.8
0.8
-50
0
50
100
150
-50
0
7HPSHUDWXUH Û&
50
100
150
7HPSHUDWXUH Û&
C008
C009
Figure 10. Input Threshold vs Temperature
Figure 11. Enable Threshold vs Temperature
1.2
25
ROH
ROL
Output Pull-Down Resistance (Ω)
Output Pull-Up Resistance (Ω)
1
20
15
10
0.8
0.6
0.4
5
0.2
-50
0
50
100
150
-50
Temperature ( °C)
50
100
150
Temperature ( °C)
C010
Figure 12. Output Pullup Resistance vs Temperature
8
0
C011
Figure 13. Output Pulldown Resistance vs Temperature
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Typical Characteristics (continued)
If not specified, INPUT refers to non-inverting input
0.6
30
IN=HIGH
Turn-On
Turn-Off
0.5
25
Propagation Delay (ns)
Operating Supply Current (mA)
IN=LOW
0.4
0.3
20
15
0.2
10
-50
0
50
100
150
-50
0
Temperature ( °C)
50
100
150
Temperature ( °C)
C012
C013
Figure 14. Operating Supply Current vs Temperature
(Output in DC ON/OFF Condition)
Figure 15. Input-to-Output Propagation Delay vs
Temperature
16
30
OUT RISING, IN- 5V to 0V
OUT FALLING, IN- 0V to 5V
15
Rise Time (ns)
IN- Propagation Delay (ns)
26
22
18
14
13
12
14
11
10
-50
0
50
100
-50
150
0
50
100
C014
C003
Figure 17. Rise Time vs Temperature
Figure 16. IN- Input-to-Output Propagation Delay vs
Temperature
9
10
8
8
Supply Current (mA)
Fall Time (ns)
150
Temperature ( °C)
Temperature ( °C)
7
6
6
4
2
5
0
4
-50
0
50
100
150
0
10
20
30
40
Supply Voltage (V)
Temperature ( °C)
C016
C015
Figure 18. Fall Time vs Temperature
Figure 19. Operating Supply Current vs Supply Voltage
(Output Switching)
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Typical Characteristics (continued)
If not specified, INPUT refers to non-inverting input
70
140
60
120
Fall Time (ns)
Rise Time (ns)
50
100
80
40
30
60
20
Cload = 10nF
40
0
10
20
30
40
10
0
10
Supply Voltage (V)
20
30
40
Supply Voltage (V)
C017
C018
Figure 20. Rise Time vs Supply Voltage
10
Figure 21. Fall Time vs Supply Voltage
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8 Detailed Description
8.1 Overview
The UCC27531-Q1 is a single-channel, high-speed, gate driver capable of effectively driving MOSFET and IGBT
power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current. Strong sink capability in
asymmetrical drive boosts immunity against parasitic Miller turn-on effect. The UCC27531-Q1 device can also
feature a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk
through the OUTL pin. This pin arrangement allows the user to apply independent turn-on and turn-off resistors
to the OUTH and OUTL pins, respectively, and easily control the switching slew rates.
The driver has rail-to-rail drive capability and extremely small propagation delay, typically 17 ns.
The input threshold of UCC27531-Q1 is based on TTL and CMOS compatible low-voltage logic, which is fixed
and independent of VDD supply voltage. The 1-V typical hysteresis offers excellent noise immunity.
The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables
the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with
the same performance as the IN, IN+, IN1, and IN2 pins.
Table 1. UCC27531-Q1 Features and Benefits
FEATURE
BENEFIT
High source and sink current capability, 2.5 A
and 5 A (asymmetrical).
High current capability offers flexibility in employing UCC27531-Q1 device to drive a variety
of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay.
Extremely low pulse transmission distortion.
Wide VDD operating range of 10 V to 32 V.
Flexibility in system design.
Can be used in split-rail systems such as driving IGBTs with both positive and
negative(relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection.
Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at
power up and power down.
High UVLO of 8.9 V typical ensures that power switch is not on in high-impedance state
which could result in high power dissipation or even failures.
Outputs held low when input pin (INx) in
floating condition.
Safety feature, especially useful in passing abnormal condition tests during safety
certification
Split output structure option (OUTH, OUTL).
Allows independent optimization of turn-on and turn-off speeds using series gate resistors.
Strong sink current (5 A) and low pull-down
impedance (0.65 Ω).
High immunity to high dV/dt Miller turn-on events.
CMOS and TTL compatible input threshold
logic with wide hysteresis.
Enhanced noise immunity, while retaining compatibility with microcontroller logic level input
signals (3.3 V, 5 V) optimized for digital power.
Input capable of withstanding –6.5 V.
Enhanced signal reliability in noisy environments that experience ground bounce on the
gate driver.
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8.2 Functional Block Diagram
IN
VDD
2
VREF
EN
1
3
VDD
6
OUTH
5
OUTL
VDD
GND
4
UVLO
(EN Pullup Resistance to VREF = 500 kΩ, VREF = 5.8 V, in Pulldown Resistance to GND = 230 kΩ)
8.3 Feature Description
8.3.1 VDD UVLO
The UCC27531-Q1 device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. To ensure an acceptable power dissipation in the power switch, this UVLO prevents the operation
of the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than
VON during power-up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs
LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This
hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also
when there are droops or dips in the VDD bias voltage when the system commences switching and there is a
sudden increase in IDD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to
drive Si MOSFETs, IGBTs, and emerging SiC FETs.
VDD Threshold
VDD
IN
OUT
Figure 22. Power Up
8.3.2 Input Stage
The input pins of UCC27531-Q1 device are based on a TTL and CMOS compatible input threshold logic that is
independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the
logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider
hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations,
where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold
voltage levels which eases system design considerations and guarantees stable operation across temperature.
The very low input capacitance , typically 20 pF, on these pins reduces loading and increases switching speed.
12
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Feature Description (continued)
The device features an important safety function wherein, whenever the input pin is in a floating condition, the
output is held in the low state. This is achieved using pullup or pulldown resistors on the input pins as shown in
the block diagrams.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a separate daughter board or PCB layout has long input connection traces:
• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since
the device features just one GND pin which may be referenced to the power ground, this may interfere with
the differential voltage between Input pins and GND and trigger an unintended change of output state.
Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage
• 1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is
highly recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate driver device package and transferring it into the external resistor itself.
Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable
pins, caution must be used in the following applications:
• Input or Enable pins are switching to amplitude > 15 V
• Input or Enable pins are switched at dV/dt > 2 V/ns
If both of these conditions occur, it is advised to add a series 150-Ω resistor for the pin(s) being switched to limit
the current through the input structure.
8.3.3 Enable Function
The Enable (EN) pin of the UCC27531-Q1 has an internal pullup resistor to an internal reference voltage so
leaving Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can
also be driven by low-voltage logic to enable and disable the driver.
8.3.4 Output Stage
The output stage of the UCC27531-Q1 device is illustrated in Figure 23. The UCC27531-Q1 device features a
unique architecture on the output stage which delivers the highest peak source current when it is most needed
during the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector
voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel
arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a
narrow instant when the output changes state from low to high, the gate driver device is able to deliver a brief
boost in the peak sourcing current enabling fast turn on.
VDD
ROH
RNMOS ,Pull Up
Input Signal
Anti ShootThrough
Circuitry
OUTH
OUTL
Narrow Pulse at
each Turn On
ROL
Figure 23. UCC27531-Q1 Gate Driver Output Stage
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Feature Description (continued)
Split output depicted in Figure 23. For devices with single OUT pin, OUTH and OUTL are connected internally
and then connected to OUT.
The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the onresistance of the P-Channel device only, because the N-Channel device is turned-on only during output change
of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is
represented by ROH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The ROL
parameter (see Electrical Characteristics), which is also a DC measurement, is representative of true impedance
of the pulldown stage in the device. In UCC27531-Q1, the effective resistance of the hybrid pullup structure is
approximately 3 x ROL.
The UCC27531-Q1 is capable of delivering 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink
capability results in a very low pulldown impedance in the driver output stage which boosts immunity against the
parasitic Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and FET power switches .
An example of a situation where Miller turn on is a concern is synchronous rectification (SR). In SR application,
the dV/dt occurs on MOSFET drain when the MOSFET is already held in Off state by the gate driver. The current
charging the CGD Miller capacitance during this high dV/dt is shunted by the pulldown stage of the driver. If the
pulldown impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can
result in spurious turn on. This phenomenon is illustrated in Figure 24.
VDS
VIN
Miller Turn -On Spike in V GS
C GD
Gate Driver
RG
COSS
ISNK
CGS
ROL
VTH
VGS of
MOSFET
ON OFF
VIN
VDS of
MOSFET
Figure 24. Low Pulldown Impedance in UCC27531-Q1
(Output Stage Mitigates Miller Turn-on Effect)
The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS
output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low
impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode
clamps may be eliminated.
14
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8.4 Device Functional Modes
The UCC227531-Q1 device operates in normal mode and UVLO mode (see VDD UVLO section for information
on UVLO operation). In normal mode, the output state is dependent on the states of the device, and the input
pins.
The UCC27531-Q1 features a single, non-inverting input, but also contains enable and disable functionality
through the EN pin. Setting the EN pin to logic HIGH will enable the non-inverting input to output on the IN pin.
The device uses a split output (OUTH, and OUTL) to allow for separate sourcing and sinking pins, which can
help reduce ground de-bouncing.
Table 2. UCC27531QDBVRQ1 Input/Output Logic Truth Table (For Single Output Driver)
EN PIN
OUTH PIN
OUTL PIN
OUT
(OUTH and OUTL pins
tied together)
L
L
High-impedance
L
L
L
H
High-impedance
L
L
H
L
High-impedance
L
L
H
H
H
High-impedance
H
H
FLOAT
H
High-impedance
H
FLOAT
H
High-impedance
L
L
IN PIN
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can
be employed between the PWM output of controllers or signal isolation devices and the gates of the power
semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the
PWM controller directly drive the gates of the switching devices. The situation is encountered often because the
PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not
capable of effectively turning on a power switch. A level shifting circuitry is needed to boost the logic-level signal
to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional
buffer drive circuits based on NPN/PNP bipolar, (or p- n-channel MOSFET), transistors in totem-pole
arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting
capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive
and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses into itself.
The UCC27531-Q1 is very flexible in this role with a strong current drive capability and wide supply voltage
range up to 32 V. This allows the driver to be used in 12-V Si MOSFET applications, 20-V and –5-V (relative to
Source) SiC FET applications, 15-V and –15-V(relative to Emitter) IGBT applications and many others. As a
single-channel driver, the UCC27531-Q1 can be used as a low-side or high-side driver. To use as a low-side
driver, the switch ground is usually the system ground so it can be connected directly to the gate driver. To use
as a high-side driver with a floating return node however, signal isolation is needed from the controller as well as
an isolated bias to the UCC27531-Q1. Alternatively, in a high-side drive configuration the UCC27531-Q1 can be
tied directly to the controller signal and biased with a non-isolated supply. However, in this configuration the
outputs of the UCC27531-Q1 need to drive a pulse transformer which then drives the power-switch to work
properly with the floating source and emitter of the power switch. Further, having the ability to control turn-on and
turn-off speeds independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining
system reliability. These requirements coupled with the need for low propagation delays and availability in
compact, low-inductance packages with good thermal capability makes gate driver devices such as the
UCC27531-Q1 extremely important components in switching power combining benefits of high-performance, low
cost, component count and board space reduction and simplified system design.
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9.2 Typical Applications
9.2.1 Driving IGBT Without Negative Bias
UCC27531-Q1
EN
1
OUTH
6
IN
OUTL
+
2
5
VDD
GND
3
4
GND
Bouncing Up
to -6.5 V
18 V
+
–
ISENSE
Controller
VCE(sense)
VCC
+
–
Figure 25. Driving IGBT Without Negative Bias
9.2.1.1 Design Requirements
When selecting the proper gate driver device for an end application, some design considerations must be
evaluated first in order to make the most appropriate selection. The following design parameters should be used
when selecting the proper gate driver device for an end application: input-to-output configuration, the input
threshold type, bias supply voltage levels, peak source and sink currents, availability of independent enable and
disable functions, propagation delay, power dissipation, and package type. See the example design parameters
and requirements in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
IN-OUT configuration
Noninverting
Input threshold type
CMOS
Bias supply voltage levels
+18 V
Negative output low voltage
N/A
dVDS/dt
(1)
(1)
20 V/ns
Enable function
Yes
Disable function
N/A
Propagation delay
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