UCC28700-Q1
SLUSC61A – JANUARY 2015 – REVISEDUCC28700-Q1
DECEMBER 2020
SLUSC61A – JANUARY 2015 – REVISED DECEMBER 2020
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UCC28700-Q1 Constant-Voltage, Constant-Current Controller
With Primary-Side Regulation
1 Features
3 Description
•
•
The UCC28700-Q1 of flyback power supply
controllers provides Constant-Voltage (CV) and
Constant-Current (CC) output regulation without the
use of an optical coupler. The devices process
information from the primary power switch and an
auxiliary flyback winding for precise control of output
voltage and current. Low start-up current, dynamically
controlled operating states and a tailored modulation
profile support very low standby power without
sacrificing start-up time or output transient response.
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
– Device HBM Classification Level 2: ±2 kV
– Device CDM Classification Level C4B: 750 V
Functional Safety-Capable
– Documentation available to aid functional safety
system design
< 30-mW Standby Power Consumption
Primary-Side Regulation (PSR) Eliminates OptoCoupler
±5% Voltage and Current Regulation
130-kHz Maximum Switching Frequency
Quasi-Resonant Valley-Switching Operation for
Highest Overall Efficiency
Patent-Pending Frequency-Jitter Scheme to Ease
EMI Compliance
Wide VDD Range Allows Small Bias Capacitor
Clamped Gate-Drive Output for MOSFET
Protection Functions: Overvoltage, Low-Line, and
Overcurrent
Programmable Cable Compensation
SOT23-6 Package
Control algorithms in the UCC28700-Q1 allows
operating efficiencies to meet or exceed applicable
standards. The output drive interfaces to a MOSFET
power switch. Discontinuous Conduction Mode (DCM)
with valley switching reduces switching losses.
Modulation of switching frequency and primary current
peak amplitude (FM and AM) keeps the conversion
efficiency high across the entire load and line ranges.
The controllers have a maximum switching frequency
of 130 kHz and always maintain control of the peakprimary current in the transformer. Protection features
help keep primary and secondary component stresses
in check. The UCC28700-Q1 allows the level of cable
compensation to be programmed.
Device Information (1)
2 Applications
•
•
•
Automotive AC-to-DC Power Conversion and DCto-DC Power Conversion
Auxiliary Power Supply for Automotive Power Train
in HEV
Flyback and Buck Power Converters
PART NUMBER
UCC28700-Q1
(1)
+
2.90 mm × 1.60 mm
VREG
D1
CB2
SOT-23 (6)
BODY SIZE (NOM)
For all available packages, see the orderable addendum at
the end of the datasheet.
VBLK
CB1
PACKAGE
Ns
Np
RPL
COUT
VOUT
±
VAC
RSTR
VAUX
UCC28700-Q1
SOT23-6
D2
VDD
CDD
Na
RS1
DRV
VS
CS
RS2
CBC
RCBC
RLC
RCS
GND
Typical Application Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
5.1 Pin Functions.............................................................. 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings (1) ................................... 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................13
8 Applications and Implementation................................ 17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................29
11.1 Device Support........................................................29
11.2 Documentation Support.......................................... 32
11.3 Trademarks............................................................. 32
4 Revision History
Changes from Revision (January 2015) to Revision A (December 2020 )
Page
• Added Functional-Safety Information................................................................................................................. 1
2
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5 Pin Configuration and Functions
CBC 1
6
VS
VDD 2
5
GND
DRV 3
4
CS
Figure 5-1. UCC28700-Q1 SOT23-6 (DBV) Top View
5.1 Pin Functions
PIN
NAME
CBC
UCC28700-Q1
I/O
DESCRIPTION
NO.
1
I
Cable Compensation (CBC) is a programming pin for compensation of cable voltage
drop. Cable compensation is programmed with a resistor to GND.
CS
4
I
Current Sense (CS) input connects to a ground-referenced current-sense resistor in
series with the power switch. The resulting voltage is used to monitor and control the
peak primary current. A series resistor can be added to this pin to compensate the peak
switch current levels as the AC-mains input varies.
DRV
3
O
Drive (DRV) is an output used to drive the gate of an external high voltage MOSFET
switching transistor.
GND
5
—
The Ground (GND) pin is both the reference pin for the controller and the low-side return
for the drive output. Special care should be taken to return all AC decoupling capacitors
as close as possible to this pin and avoid any common trace length with analog signal
return paths.
VDD
2
—
VDD is the bias supply input pin to the controller. A carefully-placed bypass capacitor to
GND is required on this pin.
I
Voltage Sense (VS) is an input used to provide voltage and timing feedback to the
controller. This pin is connected to a voltage divider between an auxiliary winding and
GND. The value of the upper resistor of this divider is used to program the AC-mains run
and stop thresholds and line compensation at the CS pin.
VS
6
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
38
V
Bias supply voltage
VVDD
Continuous gate current sink
IDRV
50
Continuous gate current source
IDRV
Selflimiting
Peak VS pin current
IVS
Gate-drive voltage at DRV
Voltage range
Operating junction temperature range
−1.2
VDRV
−0.5
Selflimiting
VS
−0.75
7
CS, CBC
−0.5
5
TJ
−55
150
Lead temperature 0.6 mm from case for 10 seconds
V
°C
260
Storage temperature, Tstg
(1)
mA
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the operating ambient temperature
ranges unless otherwise noted.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Bias supply operating voltage
CVDD
VDD bypass capacitor
MIN
MAX
UNIT
9
35
V
0.047
1
µF
RCBC
Cable-compensation resistance
10
kΩ
IVS
VS pin current
−1
mA
TJ
Operating junction temperature
−40
125
°C
6.4 Thermal Information
UCC28700-Q1
THERMAL METRIC (1)
DBV
UNIT
6 PINS
Junction-to-ambient thermal resistance (2)
θJA
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
71.2
44.4
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
(1)
4
180
(3)
°C/W
5.1
43.8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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(2)
(3)
(4)
(5)
(6)
SLUSC61A – JANUARY 2015 – REVISED DECEMBER 2020
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
6.5 Electrical Characteristics
over operating free-air temperature range, VDD = 25 V, RCBC = open, –40°C ≤ TA ≤ 125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
mA
BIAS SUPPLY INPUT
IRUN
Supply current, run
IDRV = 0, run state
2.10
2.65
IWAIT
Supply current, wait
IDRV = 0, wait state
85
110
ISTART
Supply current, start
IDRV = 0, VVDD = 18 V, start state
1.0
1.5
IFAULT
Supply current, fault
IDRV = 0, fault state
2.1
2.8
µA
mA
UNDER-VOLTAGE LOCKOUT
VVDD(on)
VDD turn-on threshold
VVDD low to high
17.5
21.0
23.0
VVDD(off)
VDD turn-off threshold
VVDD high to low
7.70
8.10
8.45
V
VS INPUT
VVSR
Regulating level
Measured at no-load condition, TJ = 25°C
4.01
4.05
4.09
V
VVSNC
Negative clamp level
IVS = -300 µA, volts below ground
190
250
325
mV
IVSB
Input bias current
VVS = 4 V
–0.25
0
0.25
µA
CS INPUT
VCST(max) Max CS threshold voltage
VVS = 3.7 V(1)
715
750
775
VCST(min)
Min CS threshold voltage
VVS = 4.35 V(1)
230
250
270
KAM
AM control ratio
VCST(max) / VCST(min)
2.75
3.00
3.15
V/V
VCCR
constant-current regulating
level
CC regulation constant
310
319
329
mV
KLC
Line compensating current
ratio
IVSLS = -300 µA, IVSLS / current out of CS pin
23
25
28
A/A
TCSLEB
Leading-edge blanking time
DRV output duration, VCS = 1 V
195
235
275
ns
IDRS
DRV source current
VDRV = 8 V, VVDD = 9 V
20
25
RDRVLS
DRV low-side drive resistance IDRV = 10 mA
mV
DRV
VDRCL
DRV clamp voltage
RDRVSS
DRV pull-down in start state
6
VVDD = 35 V
mA
12
Ω
14
16
V
150
200
230
kΩ
4.52
4.60
4.68
PROTECTION
VOVP
Over-voltage threshold
At VS input, TJ = 25°C
VOCP
Over-current threshold
At CS input
1.4
1.5
1.6
IVSL(run)
VS line-sense run current
Current out of VS pin – increasing
190
220
260
IVSL(stop)
VS line-sense stop current
Current out of VS pin – decreasing
70
80
95
KVSL
VS line-sense ratio
IVSL(run) / IVSL(stop)
2.50
2.80
3.05
TJ(stop)
Thermal shut-down
temperature
Internal junction temperature
165
V
µA
A/A
°C
CABLE COMPENSATION
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over operating free-air temperature range, VDD = 25 V, RCBC = open, –40°C ≤ TA ≤ 125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCBC(max)
Cable compensation
maximum voltage
Voltage at CBC at full load
2.8
3.0
3.4
VCVS(min)
Compensation at VS
VCBC = open, change in VS regulating level at full
load
–45
–15
25
275
320
365
VCVS(max) Maximum compensation at VS VCBC = 0 V, change in VS regulating level at full load
(1)
UNITS
V
mV
These devices automatically vary the control frequency and current sense thresholds to improve EMI performance, these threshold
voltages and frequency limits represent average levels.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
6
TEST CONDITIONS
V(1)
fSW(max)
Maximum switching frequency
VVS = 3.7
fSW(min)
Minimum switching frequency
VVS = 4.35 V(1)
TZTO
Zero-crossing timeout delay
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MIN
TYP
MAX
UNIT
120
130
140
kHz
875
1000
1100
Hz
1.80
2.10
2.55
µs
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6.7 Typical Characteristics
At VDD = 25 V, unless otherwise noted.
10
10
Run State
IRUN, VDD = 25 V
1
IVDD − Bias Supply Current (mA)
IVDD − Bias Supply Current (mA)
1
Wait State
0.1
0.01
VDD Turn−Off
0.001
VDD Turn−On
IWAIT, VDD = 25 V
0.1
0.01
0.001
0.0001
ISTART, VDD = 18 V
Start State
0.00001
0
5
10
15
20
25
VDD − Bias Supply Voltage (V)
30
35
0.0001
−25
0
25
50
75
TJ − Temperature (°C)
100
G001
Figure 6-1. Bias Supply Current vs. Bias Supply
Voltage
G002
Figure 6-2. Bias Supply Current vs. Temperature
300
4.10
250
VS Line Sense Current (µA)
VVSR − VS Regulation Voltage (V)
4.08
4.06
4.04
4.02
4.00
IVSLRUN
200
150
100
IVSLSTOP
50
3.98
3.96
−25
125
0
25
50
75
TJ − Temperature (°C)
100
125
G003
Figure 6-3. VS Regulation Voltage vs. Temperature
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0
−20
5
30
55
80
TJ − Temperature (°C)
105
125
G004
Figure 6-4. Line-Sense Current vs. Temperature
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330
VCCR − Constant Current Regulating Level (mV)
VCSTMIN − Minimum CS Threshold Voltage (mV)
270
265
260
255
250
245
240
235
230
−25
0
25
50
75
TJ − Temperature (°C)
100
325
320
315
310
−25
125
0
25
50
75
TJ − Temperature (°C)
G005
100
125
G006
Figure 6-5. Minimum CS Threshold Voltage vs.
Temperature
Figure 6-6. Constant-Current Regulating Level vs.
Temperature
FSWMIN − Minimum Switching Frequency (Hz)
1100
1075
1050
1025
1000
975
950
925
900
875
−25
0
25
50
75
TJ − Temperature (°C)
100
125
G007
Figure 6-7. Minimum Switching Frequency vs.
Temperature
VDRV = 8 V, VVDD = 9 V
Figure 6-8. DRV Source Current vs. Temperature
4.68
VOVP − VS Over−Voltage Threshold (V)
4.66
4.64
4.62
4.60
4.58
4.56
4.54
4.52
−25
0
25
50
75
TJ − Temperature (°C)
100
125
G011
Figure 6-9. Overvoltage Threshold vs. Temperature
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7 Detailed Description
7.1 Overview
The UCC28700-Q1 is a flyback power supply controller which provides accurate voltage and constant current
regulation with primary-side feedback, eliminating the need for opto-coupler feedback circuits. The controller
operates in discontinuous conduction mode with valley-switching to minimize switching losses. The modulation
scheme is a combination of frequency and primary peak current modulation to provide high conversion efficiency
across the load range. The control law provides a wide-dynamic operating range of output power to achieve the
< 30-mW stand-by power requirement.
Another feature beneficial to achieve low stand-by power without excessive start-up time is a wide operating
VDD range to allow a high-value VDD start-up resistance and low-value VDD capacitance. During low-power
operating ranges the device has power management features to reduce the device operating current at
operating frequencies below 44 kHz. The UCC28700-Q1 controller includes features in the modulator to reduce
the EMI peak energy of the fundamental switching frequency and harmonics. Accurate voltage and constant
current regulation, fast dynamic response, and fault protection are achieved with primary-side control. A
complete charger solution can be realized with a straightforward design process, low cost and low component
count.
7.2 Functional Block Diagram
POWER
& FAULT
MANAGEMENT
UVLO
21V/8V
VDD
START
RUN
WAIT
FAULT
GND
4V + VCVS
+
VDD
25mA
CONTROL
LAW
E/A
VS
OC FAULT
OV FAULT
TSD/SD FAULT
LINE FAULT
SAMPLER
VSS
DRV
VCST
+
VALLEY
SWITCHING
14V
1/FSW
200K
OV FAULT
VOVP
S
Q
R
Q
CURRENT
REGULATION
VCST
LEB
IVSLS
LINE
SENSE
CS
+
SECONDARY
TIMING
DETECT
IVSLS
10k
IVSLS / KLC
+
LINE
FAULT
OC
FAULT
+
1.5V
2.1V / 0.75V
VCVS
CABLE
COMPENSATION
0V-3V
+
ICBC
28 k:
CBC
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7.3 Feature Description
7.3.1 Detailed Pin Description
7.3.1.1 VDD (Device Bias Voltage Supply)
The VDD pin is connected to a bypass capacitor to ground and a start-up resistance to the input bulk capacitor
(+) terminal. The VDD turn-on UVLO threshold is 21 V and turn-off UVLO threshold is 8.1 V, with an available
operating range up to 35 V. The USB charging specification requires the output current to operate in constantcurrent mode from 5 V to a minimum of 2 V; this is easily achieved with a nominal VDD of approximately 25 V.
The additional VDD headroom up to 35 V allows for VDD to rise due to the leakage energy delivered to the VDD
capacitor in high-load conditions. Also, the wide VDD range provides the advantage of selecting a relatively
small VDD capacitor and high-value start-up resistance to minimize no-load stand-by power loss in the start-up
resistor.
7.3.1.2 GND (Ground)
This is a single ground reference external to the device for the gate drive current and analog signal reference.
Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and CS
signal pins.
7.3.1.3 VS (Voltage-Sense)
The VS pin is connected to a resistor divider from the auxiliary winding to ground. The output-voltage feedback
information is sampled at the end of the transformer secondary current demagnetization time to provide an
accurate representation of the output voltage. Timing information to achieve valley-switching and to control the
duty cycle of the secondary transformer current is determined by the waveform on the VS pin. Avoid placing a
filter capacitor on this input which would interfere with accurate sensing of this waveform.
The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. This information is sensed during the
MOSFET on-time. For the AC-input run/stop function, the run threshold on VS is 220 µA and the stop threshold
is 80 µA. The values for the auxiliary voltage divider upper-resistor RS1 and lower-resistor RS2 can be
determined by the equations below.
R S1 =
VIN :run ; × ¾2
NPA × IVSL (run )
(1)
where
•
•
•
NPA is the transformer primary-to-auxiliary turns ratio,
VIN(run) is the AC RMS voltage to enable turn-on of the controller (run),
IVSL(run) is the run-threshold for the current pulled out of the VS pin during the MOSFET on-time. (see the
Section 6.5 table)
RS2 =
RS1 ´ VVSR
NAS ´ (VOCV + VF ) - VVSR
(2)
where
•
•
•
•
•
10
VOCV is the converter regulated output voltage,
VF is the output rectifier forward drop at near-zero current,
NAS is the transformer auxiliary to secondary turns ratio,
RS1 is the VS divider high-side resistance,
VVSR is the CV regulating level at the VS input (see the Section 6.5 table).
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7.3.1.4 DRV (Gate Drive)
The DRV pin is connected to the MOSFET gate pin, usually through a series resistor. The gate driver provides a
gate-drive signal limited to 14 V. The turn-on characteristic of the driver is a 25-mA current source which limits
the turn-on dv/dt of the MOSFET drain and reduces the leading-edge current spike, but still provides gate-drive
current to overcome the Miller plateau. The gate-drive turn-off current is determined by the low-side driver
RDS(on) and any external gate-drive resistance. The user can reduce the turn-off MOSFET drain dv/dt by adding
external gate resistance.
7.3.1.5 CS (Current Sense)
The current-sense pin is connected through a series resistor (RLC) to the current-sense resistor (RCS). The
current-sense threshold is 0.75 V for IPP(max) and 0.25 V for IPP(min). The series resistor RLC provides the function
of feed-forward line compensation to eliminate change in IPP due to change in di/dt and the propagation delay of
the internal comparator and MOSFET turn-off time. There is an internal leading-edge blanking time of 235 ns to
eliminate sensitivity to the MOSFET turn-on current spike. It should not be necessary to place a bypass
capacitor on the CS pin. The value of RCS is determined by the target output current in constant-current (CC)
regulation. The values of RCS and RLC can be determined by the equations below. The term ηXFMR is intended to
account for the energy stored in the transformer but not delivered to the secondary. This includes transformer
resistance and core loss, bias power, and primary-to-secondary leakage ratio.
Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%,
and bias power to output power ratio of 1.5%. The ηXFMR value is approximately: 1 - 0.05 - 0.035 - 0.015 = 0.9.
(3)
where
•
•
•
•
VCCR is a current regulation constant (see the Section 6.5 table),
NPS is the transformer primary-to-secondary turns ratio (a ratio of 13 to 15 is recommended for 5-V output),
IOCC is the target output current in constant-current regulation,
ηXFMR is the transformer efficiency.
RLC =
KLC ´ RS1 ´ RCS ´ TD ´ NPA
LP
(4)
where
•
•
•
•
•
•
RS1 is the VS pin high-side resistor value,
RCS is the current-sense resistor value,
TD is the current-sense delay including MOSFET turn-off delay, add ~50 ns to MOSFET delay,
NPA is the transformer primary-to-auxiliary turns ratio,
LP is the transformer primary inductance,
KLC is a current-scaling constant (see the Section 6.5 table).
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7.3.1.6 CBC (Cable Compensation)
The cable compensation pin is connected to a resistor to ground to program the amount of output voltage
compensation to offset cable resistance. The cable compensation block provides a 0-V to 3-V voltage level on
the CBC pin corresponding to 0 to IOCC output current. The resistance selected on the CBC pin programs a
current mirror that is summed into the VS feedback divider therefore increasing the output voltage as IOUT
increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum cable
compensation of a 5-V output to 400 mV when CBC is shorted to ground. The CBC resistance value can be
determined by the equation below.
RCBC =
VCBC(max) ´ 3 kW ´ (VOCV + VF )
VVSR ´ VOCBC
- 28 kW
(5)
where
•
•
•
•
•
VO is the output voltage,
VF is the diode forward voltage,
VOCBC is the target cable compensation voltage at the output terminals,
VCBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current
(see the Section 6.5 table),
VVSR is the CV regulating level at the VS input (see the Section 6.5 table).
7.3.2 Fault Protection
There is comprehensive fault protection incorporated into the UCC28700-Q1. Protection functions include:
• Output overvoltage
• Input undervoltage
• Internal overtemperature
• Primary overcurrent fault
• CS pin fault
• VS pin fault
A UVLO reset and restart sequence applies for all fault protection events.
The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on
VS exceeds 115% of the nominal VOUT, the device stops switching and keeps the internal circuitry enabled to
discharge the VDD capacitor to the UVLO turn-off threshold. After that, the device returns to the start state and a
start-up sequence ensues.
The UCC28700-Q1 always operates with cycle-by-cycle primary peak current control. The normal operating
range of the CS pin is 0.75 V to 0.25 V. There is additional protection if the CS pin reaches 1.5 V. This results in
a UVLO reset and restart sequence. There is no leading-edge blanking on the 1.5-V threshold on CS.
The line input run and stop thresholds are determined by current information at the VS pin during the MOSFET
on-time. While the VS pin is clamped close to GND during the MOSFET on-time, the current through RS1 is
monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds
allows clean start-up and shut-down of the power supply with the line voltage. The run current threshold is 220
µA and the stop current threshold is 80 µA.
The internal overtemperature protection threshold is 165°C. If the junction temperature reaches this threshold
the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.
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7.4 Device Functional Modes
7.4.1 Primary-Side Voltage Regulation
Figure 7-1 shows a simplified flyback convertor with the main voltage regulation blocks of the device shown. The
power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is
the key to primary-side control.
IS
Bulk Voltage ± VBLK
+ VF±
Timing
Primary
Secondary
COUT
VOUT
RLOAD
RS1
VS
Discriminator and
Sampler
VCL
RS2
GD
DRV
Control Law
Minimum Period
and Peak
Primary Current
CS
RCS
Zero Crossings
Figure 7-1. Simplified Flyback Convertor (with the main voltage regulation blocks)
In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer
energy to the secondary. As shown in Figure 7-2 it is clear there is a down slope representing a decreasing total
rectifier VF and resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an
accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks
the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after
the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current.
The internal reference on VS is 4.05 V; the resistor divider is selected as outlined in the VS pin description.
VS Sample
(VOUT + VF + ISRS) NA / NS
0V
- (VBLK) NA / NP
Figure 7-2. Auxiliary Winding Voltage
The UCC28700-Q1 VS signal sampler includes signal discrimination methods to ensure an accurate sample of
the output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to
ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any
subsequent leakage inductance ring. Refer to Figure 7-3 for a detailed illustration of waveform criteria to ensure
a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset
pedestal, TLK_RESET in Figure 7-3. Because this can mimic the waveform of the secondary current decay,
followed by a sharp downslope, it is important to keep the leakage reset time less than 500 ns for IPRI minimum,
and less than 1.5 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform
following TLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at
least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it
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usually occurs during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on VS is
scaled up to the auxiliary winding voltage by RS1 and RS2, and is equal to 100 mV x (RS1 + RS2) / RS2.
TLK RESET
TSMPL
VS ring p-p
TDM
Figure 7-3. Auxiliary Waveform Details
During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode
as illustrated in Figure 7-4 below. The internal operating frequency limits of the device are 130 kHz maximum
and 1 kHz minimum. The transformer primary inductance and primary peak current chosen sets the maximum
operating frequency of the converter. The output preload resistor and efficiency at low power determines the
converter minimum operating frequency. There is no stability compensation required for the UCC28700-Q1
controller.
Figure 7-4. Frequency and Amplitude Modulation Modes (during voltage regulation)
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7.4.2 Primary-Side Current Regulation
Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary
average current. The control law dictates that as power is increased in CV regulation and approaching CC
regulation the primary-peak current is at IPP(max). Referring to Figure 7-5 below, the primary-peak current, turns
ratio, secondary demagnetization time (tDM), and switching period (TSW) determine the secondary average
output current. Ignoring leakage inductance effects, the average output current is given by Equation 6. When the
average output current reaches the regulation reference in the current control block, the controller operates in
frequency modulation mode to control the output current at any output voltage at or below the voltage regulation
target as long as the auxiliary winding can keep VDD above the UVLO turn-off threshold.
IPP
IS x N S/NP
tON
tDM
T SW
Figure 7-5. Transformer Currents
(6)
Figure 7-6. Typical Target Output V-I Characteristic
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7.4.3 Valley-Switching
The UCC28700-Q1 utilizes valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI,
and to minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all
load conditions unless the VDS ringing has diminished.
Referring to Figure 7-7 below, the UCC28700-Q1 operates in a valley-skipping mode in most load conditions to
maintain an accurate voltage or current regulation point and still switch on the lowest available VDS voltage.
VDS
VDRV
Figure 7-7. Valley-Skipping Mode
7.4.4 Start-Up Operation
Upon application of input voltage to the converter, the start-up resistor connected to VDD from the bulk capacitor
voltage (VBLK) charges the VDD capacitor. During charging of the VDD capacitor the device bias supply current
is less than 1.5 µA. When VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled and the
converter starts switching. The initial three cycles are limited to IPP(min). This allows sensing any initial input or
output faults with minimal power delivery. After the initial three cycles at minimum I PP(min), the controller responds
to the condition dictated by the control law. The converter remains in discontinuous mode during charging of the
output capacitor(s), maintaining a constant output current until the output voltage is in regulation.
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8 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The UCC28700-Q1 flyback power supply controllers provides constant voltage (CV) and constant current (CC)
output regulation to help meet USB-compliant adaptors and charger requirements. These devices use the
information obtained from auxiliary winding sensing (VS) to control the output voltage and do not require
optocoupler/TL431 feedback circuitry. Not requiring optocoupler feedback reduces the component count and
makes the design more cost effective.
8.2 Typical Application
D1
VBLK
CB2
+
CB1
Ns
Np
VREG
RPL
COUT
VOUT
±
VAC
UCC28700-Q1
SOT23-6
RSTR
VAUX
D2
VDD
CDD
Na
RS1
DRV
VS
CS
RS2
CBC
RCBC
RLC
RCS
GND
Figure 8-1. Typical Application Circuit
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8.2.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
SYMBOL
NOTES AND CONDITIONS
MIN
NOM
MAX
UNIT
100
115/230
240
V
47
50/60
INPUT CHARACTERISTICS
Input Voltage
VIN
Line Frequency
fLINE
No Load Input Power
PSB_CONV
VIN = Nom, IO = 0 A
Brownout Voltage
VIN(RUN)
IO = Nom
Output Voltage
VO
VIN = Nom, IO = Nom
Output Voltage Ripple
VRIPPLE
VIN = Nom, IO = Max
Output Current
IO
VIN = Min to Max
1
Output OVP
VOVP
IOUT = Min to Max
5.75
VOΔ
(0.1 A to 0.6 A) or (0.6 A to 0.1 A)
VOΔ = 0.9 V for COUT calculation
in applications section
64
Hz
30
mW
70
V
OUTPUT CHARACTERISTICS
4.75
5
5.25
V
0.1
V
1.05
A
V
Transient Response
Load Step (VO = 4.1 V to 6 V)
4.1
5
6
V
105
kHz
SYSTEMS CHARACTERISTICS
Switching Frequency
Full Load Efficiency (115/230 V
RMS Input)
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η
IO = 1 A
74%
76%
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8.2.2 Detailed Design Procedure
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28700-Q1 controller. Please refer to the Figure 8-1 for circuit details and section Section 11.1.1 for variable
definitions used in the applications equations below.
8.2.2.1 Transformer Parameter Verification
The transformer turns ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these
should be reviewed. The UCC28700-Q1 controller requires a minimum on time of the MOSFET (TON) and
minimum D MAG time (TDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of
FMAX, LP and RCS affects the minimum TON and TDMAG.
The secondary rectifier and MOSFET voltage stress can be determined by the equations below.
VREV =
VIN(max) ´ 2
NPS
+ VOCV + VOCBC
(7)
For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.
VDSPK
VIN(max) u 2
VOCV
VF
VOCBC u NPS
VLK
(8)
The following equations are used to determine if the minimum TON target of 300 ns and minimum TDMAG target
of 1.1 µs is achieved.
(9)
(10)
8.2.2.2 Output Capacitance
The output capacitance value is typically determined by the transient response requirement from no-load. For
example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a
load-step transient of 0 mA to 500 mA . The equation below assumes that the switching frequency can be at the
UCC28700-Q1 minimum of fSW(min).
COUT
æ
ö
1
ITRAN ç
+ 150 ms ÷
ç fSW(min)
÷
è
ø
=
VOD
(11)
Another consideration of the output capacitor(s) is the ripple voltage requirement which is reviewed based on
secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation
below.
RESR =
VRIPPLE ´ 0.8
IPP(max) ´ NPS
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8.2.2.3 VDD Capacitance, CDD
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain
the voltage to the UCC28700-Q1. The total output current available to the load and to charge the output
capacitors is the constant-current regulation target. The equation below assumes the output current of the
flyback is available to charge the output capacitance until the minimum output voltage is achieved. There is an
estimated 1 mA of gate-drive current in the equation and 1 V of margin added to VDD.
(13)
8.2.2.4 VDD Start-Up Resistance, RSTR
Once the VDD capacitance is known, the start-up resistance from VBULK to achieve the turn-on time target can
be determined.
(14)
8.2.2.5 VS Resistor Divider, Line Compensation, and Cable Compensation
The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side
divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1
is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating
threshold.
VIN :run ; × ¾2
NPA × IVSL (run )
R S1 =
(15)
The low-side VS pin resistor is selected based on desired VO regulation voltage.
RS2 =
NAS
RS1 ´ VVSR
´ (VOCV + VF ) - VVSR
(16)
The UCC28700-Q1 can maintain tight constant-current regulation over input line by utilizing the line
compensation feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and
expected gate drive and MOSFET turn-off delay. Assume a 50-ns internal delay in the UCC28700-Q1.
(17)
On the UCC28700-Q1 which has adjustable cable compensation, the resistance for the desired compensation
level at the output terminals can be determined using the equation below.
RCBC =
20
VCBC(max) ´ 3 kW ´ (VOCV + VF )
VVSR ´ VOCBC
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- 28 kW
(18)
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8.2.2.6 Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum
Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target.
PIN =
VOCV ´ IOCC
h
(19)
The below equation provides an accurate solution for input capacitance based on a target minimum bulk
capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve
the target capacitance.
CBULK
æ
æ VBULK(min)
1
2PIN ´ ç 0.25 +
´ arcsin ç
ç
2p
ç
è 2 ´ VIN(min)
è
=
2VIN(min)2 - VBULK(min)2 ´ fLINE
(
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)
öö
÷÷
÷÷
øø
(20)
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8.2.2.7 Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency
at full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.
Initially determine the maximum available total duty cycle of the on time and secondary conduction time based
on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not
have an estimate from previous designs. For the transition mode operation limit, the period required from the end
of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs
assuming 500-kHz resonant frequency. DMAX can be determined using the equation below.
(21)
Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation
below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation.
It is set internally by the UCC28700-Q1 at 0.425. The total voltage on the secondary winding needs to be
determined; which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC).
For the 5-V USB charger applications, a turns ratio range of 13 to 15 is typically used.
NPS(max) =
DMAX ´ VBULK(min)
DMAGCC ´ (VOCV + VF + VOCBC )
(22)
Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following
parameters.
The UCC28700-Q1 controller constant-current regulation is achieved by maintaining a maximum DMAG duty
cycle of 0.425 at the maximum primary current setting. The transformer turns ratio and constant-current
regulating voltage determine the current sense resistor for a target constant current.
Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term
is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias
power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An
overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding
loss, and 1.5% bias power.
(23)
The primary transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency and output and transformer power losses are
included in the equation below. Initially determine transformer primary current.
Primary current is simply the maximum current sense threshold divided by the current sense resistance.
IPP(max) =
LP =
VCST(max)
RCS
(24)
2 (VOCV + VF + VOCBC ) ´ IOCC
hXFMR ´ IPP(max)2 ´ fMAX
(25)
The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target
operating output voltage in constant-current regulation and the VDD UVLO of the UCC28700-Q1. There is
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additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns
ratio to be used in many designs.
NAS =
VDD(off ) + VFA
VOCC + VF
(26)
8.2.2.8 Standby Power Estimate
Assuming no-load standby power is a critical design parameter, determine estimated no-load power based on
target converter maximum switching frequency and output power rating.
The following equation estimates the stand-by power of the converter.
PSB _ CONV =
POUT ´ fMIN
hSB ´ K AM2 ´ fMAX
(27)
For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on
25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in
the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias
power estimated at 2.5 mW.
RPL =
VOCV 2
PSB _ CONV - 2.5 mW
(28)
Typical start-up resistance values for RSTR range from 13 MΩ to 20 MΩ to achieve 1-s start-up time. The
capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement,
typically 325 VDC.
(29)
For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the start-up resistance and
converter stand-by power loss.
(30)
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8.2.3 Application Curves
24
Figure 8-2. Output at Startup at 115-V RMS (No
Load)
Figure 8-3. Output at Startup at 115-V RMS (5-Ω
Load)
Figure 8-4. Output at Startup at 230-V RMS (No
Load)
Figure 8-5. Output at Startup at 230-V RMS (5-Ω
Load)
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CH1 = IO, CH4 = VO With a 5-V Offset
CH1 = IO, CH4 = VO With a 5-V Offset
Figure 8-6. Load Transients: (0.1-A to 0.6-A Load
Step)
Figure 8-7. Load Transients: (0.6-A to 0.1-A Load
Step)
CH4 = VO, Output voltage at EVM output
CH2 = VO, Output voltage measured at the end of the 3M of cable in parallel with a 1-uF capacitor. The output voltage has less than
50 mV of output ripple at the end of the cable.
Figure 8-8. Output Ripple Voltage at Full Load
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9 Power Supply Recommendations
The UCC28700-Q1 is intended for AC/DC converters with input voltage range of 85 VAC(rms) to 265 VAC(rms)
using Flyback topology. It can be used in other applications and converter topologies with different input
voltages. Be sure that all voltages and currents are within the recommended operating conditions and absolute
maximum ratings of the device.
To maintain output current regulation over the entire input voltage range, design the converter to operate close to
fMAX when in full-load conditions.
To improve thermal performance increase the copper area connected to GND pins.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
High frequency bypass Capacitor C7 should be placed arcos Pin 2 and 5 as close as you can get it to the
pins.
Resistor R15 and C7 form a low pass filter and the connection of R15 and C7 should be as close to the VDD
pin as possible.
C9 should be put as close to CS pin and R10 as possible. This forms a low pass filter with R10.
The connection for C9 and R10 should be as close to the CS pin as possible.
Please note that C9 may not be required in all designs. However, it is wise to put a place holder for it in your
design.
The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R7 and
R9. Note the trace with between the R7, R9 and VS pin should be; as short as; possible to reduce/eliminate
possible EMI coupling.
Note the IC ground and power ground should meet at the bulk capacitor’s (C4 and C5) return. Tri to ensure
that high frequency/high current from the power stage does not go through the signal ground.
– The high frequency/high current path that you need to be cautious of on the primary is C4, C5 +, T1
(P1,P2), Q1d, Q1s, R13 to the return of C4 and C5.
Try to keep all high current loops as short as possible.
Keep all high current/high frequency traces away from or perpendicular to other traces in the design.
Traces on the voltage clamp formed by D1, R1, D4 and C4 as short as possible.
C4 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt
caused by large di/dt.
Avoid mounting semiconductors under magnetics.
Figure 10-1. 5-W USB Adapter Schematic
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D4
C1
TP4
VOUT-
R4
10.2 Layout Example
C5
C3
R2
C8
R15
R11
D3
U1
C6
R9
C7
R8
Q1
J1
R3
C9
R7
TP3
D2
R12
JMP2
VOUT+
D5
C4
R6
R13
D1
T1
Line
R5
R1
JMP3
J2
C2
TP1
L1
TP3
Nuetral
R10
Figure 10-2. Layout Example
28
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Capacitance Terms in Farads
CBULK
total input capacitance of CB1 and CB2.
CDD
minimum required capacitance on the VDD pin.
COUT
minimum output capacitance required.
11.1.1.2 Duty Cycle Terms
DMAGCC
secondary diode conduction duty cycle in CC, 0.425.
DMAX
MOSFET on-time duty cycle.
11.1.1.3 Frequency Terms in Hertz
fLINE
minimum line frequency.
fMAX
target full-load maximum switching frequency of the converter.
fMIN
minimum switching frequency of the converter, add 15% margin over the fSW(min) limit of the device.
fSW(min) minimum switching frequency (see the Section 6.5 table)
11.1.1.4 Current Terms in Amperes
IOCC
converter output constant-current target.
IPP(max)
maximum transformer primary current.
ISTART
start-up bias supply current (see the Section 6.5 table).
ITRAN
required positive load-step current.
IVSL(run)
VS pin run current (see the Section 6.5 table).
11.1.1.5 Current and Voltage Scaling Terms
KAM
maximum-to-minimum peak primary current ratio (see the Section 6.5 table).
KLC
current-scaling constant (see the Section 6.5 table).
11.1.1.6 Transformer Terms
LP
transformer primary inductance.
NAS
transformer auxiliary-to-secondary turns ratio.
NPA
transformer primary-to-auxiliary turns ratio.
NPS
transformer primary-to-secondary turns ratio.
11.1.1.7 Power Terms in Watts
PIN
converter maximum input power.
POUT
full-load output power of the converter.
PRSTR
VDD start-up resistor power dissipation.
PSB
total stand-by power.
PSB_CONV
PSB minus start-up resistor and snubber losses.
11.1.1.8 Resistance Terms in Ω
RCS
primary current programming resistance
RESR
total ESR of the output capacitor(s).
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RPL
preload resistance on the output of the converter.
RS1
high-side VS pin resistance.
RS2
low-side VS pin resistance.
RSTR
maximum start-up resistance to achieve the turn-on time target.
RSTR
VDD start-up resistance.
11.1.1.9 Timing Terms in Seconds
TD
current-sense delay including MOSFET turn-off delay; add 50 ns to MOSFET delay.
TDMAG(min)
minimum secondary rectifier conduction time.
TON(min)
minimum MOSFET on time.
TR
resonant frequency during the DCM (discontinuous conduction mode) time.
TSTR
converter start-up time requirement.
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UCC28700-Q1
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SLUSC61A – JANUARY 2015 – REVISED DECEMBER 2020
11.1.1.10 Voltage Terms in Volts
VBLK
highest bulk capacitor voltage for stand-by power measurement.
VBULK(min) minimum voltage on CB1 and CB2 at full power.
VOCBC
target cable compensation voltage at the output terminals.
VCBC(max) maximum voltage at the CBC pin at the maximum converter output current (see the Section 6.5
table).
VCCR
constant-current regulating voltage (see the Section 6.5 table).
VCST(max) CS pin maximum current-sense threshold (see the Section 6.5 table).
VCST(min) CS pin minimum current-sense threshold (see the Section 6.5 table).
VDD(off)
UVLO turn-off voltage (see the Section 6.5 table).
VDD(on)
UVLO turn-on voltage (see the Section 6.5 table).
VOΔ
output voltage drop allowed during the load-step transient.
VDSPK
peak MOSFET drain-to-source voltage at high line.
VF
secondary rectifier forward voltage drop at near-zero current.
VFA
auxiliary rectifier forward voltage drop.
VLK
estimated leakage inductance energy reset voltage.
VOCV
regulated output voltage of the converter.
VOCC
target lowest converter output voltage in constant-current regulation.
VREV
peak reverse voltage on the secondary rectifier.
VRIPPLE
output peak-to-peak ripple voltage at full-load.
VVSR
CV regulating level at the VS input (see the Section 6.5 table).
11.1.1.11 AC Voltage Terms in VRMS
VIN(max)
maximum input voltage to the converter.
VIN(min)
minimum input voltage to the converter.
VIN(run)
converter input start-up (run) voltage.
11.1.1.12 Efficiency Terms
ηSB
estimated efficiency of the converter at no-load condition, not including start-up resistance or bias
losses. For a 5-V USB charger application, 60% to 65% is a good initial estimate.
η
converter overall efficiency.
ηXFMR transformer primary-to-secondary power transfer efficiency.
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Using the UCC28700EVM-068, Evaluation Module, SLUU968
•
11.3 Trademarks
All trademarks are the property of their respective owners.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28700QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
700Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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