VFC110APG4

VFC110 SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 High-Frequency VOLTAGE-TO-FREQUENCY CONVERTER FEATURES DESCRIPTION D HIGH-FREQUENCY OPERATION: D The VFC110 voltage-to-frequency converter is a third-generation VFC offering improved features and performance. These include higher frequency operation, an onboard precision 5V reference, and a Disable function. 4MHz FS max EXCELLENT LINEARITY: ±0.02% typ at 2MHz PRECISION 5V REFERENCE DISABLE PIN D D D LOW JITTER The precision 5V reference can be used for offsetting the VFC transfer function, as well as exciting transducers or bridges. The Enable pin allows several VFCs’ outputs to be paralleled, multiplexed, or simply to shut off the VFC. The open-collector frequency output is TTL-/ CMOS-compatible. The output may be isolated by using an opto-coupler or transformer. APPLICATIONS D D D D D INTEGRATING A/D CONVERSION PROCESS CONTROL VOLTAGE ISOLATION VOLTAGE-CONTROLLED OSCILLATOR Internal input resistor, one-shot and integrator capacitors simplify applications circuits. These components are trimmed for a full-scale output frequency of 4MHz at 10V input. No additional components are required for many applications. FM TELEMETRY The VFC110 is packaged in a plastic 14-pin DIP. Industrial and military temperature range gradeouts are available. I IN VOUT Comparator +VS 1 12 11 10 VIN 2 8 fO U T 7 D igital G roun d 5 E nab le O ne− S ho t Input Common 14 VR EF 4 13 3 6 − VS Analog Ground 5V COS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. Copyright  1998−2007, Texas Instruments Incorporated
          
             
 !     !    www.ti.com "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 ABSOLUTE MAXIMUM RATINGS(1) Power Supply Voltages (+VS to −VS) . . . . . . . . . . . . . . . . . . . . . 40V fOUT Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Comparator In Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . −5V to +VS Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS to −VS Integrator Common-Mode Voltage . . . . . . . . . . . . . −1.5V to +1.5V Integrator Differential Input Voltage . . . . . . . . . . . . . +0.5V to −0.5V Integrator Out (short-circuit) . . . . . . . . . . . . . . . . . . . . . . . Indefinite VREF Out (short-circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite Operating Temperature Range P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C Storage Temperature P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +125°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE VFC110AP 14-Pin Plastic DIP N −25°C to +85°C (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATION Top View 2 P-DIP IIN 1 14 Input Common VIN 2 13 Analog Common +5VREF Out 3 12 VOUT −VS 4 11 Comparator In Enable 5 10 +VS COS 6 9 NC Digital Ground 7 8 fOUT "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS At TA = +25°C and VS = ±15V, unless otherwise noted. VFC110AP PARAMETER VOLTAGE-TO-FREQUENCY OPERATION Nonlinearity(1): fFS = 100kHz fFS = 1MHz fFS = 2MHz fFS = 4MHz Gain Error, f = 1MHz Gain Drift, f = 1MHz Relative to VREF PSRR INPUT Full-Scale Input Current IB− (Inverting Input) IB+ (Noninverting Input) VOS VOS Drift INTEGRATOR AMPLIFIER OUTPUT Output Voltage Range Output Current Drive Capacitive Load CONDITIONS COS = 2.2nF, RIN = 44kΩ COS = 150pF, RIN = 40kΩ COS = 56pF, RIN = 34kΩ COS = (Int), RIN = (Int) COS = 150pF, RIN = 40kΩ Specified Temp Range Specified Temp Range VS = ±8V to ±18V REFERENCE VOLTAGE Voltage Voltage Drift Load Regulation PSRR Current Limit ENABLE INPUT VHIGH (fOUT Enabled) VLOW (fOUT Disabled) IHIGH ILOW TYP MAX UNITS 0.01 0.05 0.1 %FS %FS %FS %FS % ppm/°C ppm/°C %/V 0.02 1 5 100 100 0.1 250 20 250 500 100 3 Specified Temp Range RL = 2kΩ 35 −0.2 5 No Oscillations COMPARATOR INPUT IB (Input Bias Current) Trigger Voltage Input Voltage Range OPEN COLLECTOR OUTPUT VO Low ILEAKAGE Fall Time Delay to Rise Settling Time MIN +VS − 4 20 10 −5 ±50 −5 +VS 0.1 25 25 To Specified Linearity for a Full-Scale Input Step IO = 0 to 10mA VS = ±8V to ±18V Short Circuit Specified Temp Range Specified Temp Range 0.4 1 µA nA nA mV µV/°C V mA nF µA mV V V µA ns ns One Pulse of New Frequency Plus 1µs 4.97 5 15 2 5 20 5.03 50 10 2 0.4 0.1 1 POWER SUPPLY Voltage, ±VS Current ±8 TEMPERATURE RANGE Specified AP Storage AP ±15 13 V ppm/°C mV mV/V mA V V µA µA ±18 16 V mA −25 +85 °C −40 +125 °C (1) Nonlinearity measured from 1V to 10V input. 3 "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 TYPICAL CHARACTERISTICS At TA = +25°C and VS = ±15V, unless otherwise noted. FULL−SCALE FREQUENCY vs EXTERNAL ONE−SHOT CAPACITOR QUIESCENT CURRENT vs TEMPERATURE 10M 18 1M RIN = 40kΩ 100k I Q+ 14 Quiescent Current (mA) Full−Scale Frequency (Hz) 16 12 10 IQ− 8 6 4 2 10k 10pF 0 100pF 1nF 10nF 100nF −25 0 25 50 75 Temperature (_ C) REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT TYPICAL FULL−SCALE GAIN DRIFT vs FULL−SCALE FREQUENCY 5.01 100 Full−Scale Frequency (ppm/_C) 4.99 4.98 Short−Circuit Current Limit 4.97 A Grade 100 4.96 10 0 2 4 6 8 10 12 14 16 18 20 22 10k 100k 1M 10M Full−Scale Frequency (Hz) Output Current (mA) FREQUENCY COUNT REPEATABILITY vs COUNTER GATE TIME JITTER vs FULL−SCALE FREQUENCY 500 0 .001 Jitter (ppm) 400 300 200 100 0 17 0.0006 0.0004 18 fFS = 100kHz 0.0002 19 fFS = 1MHz 0.0001 10k 100k 1M 10M Full−Scale Frequency (Hz) Jitter is the ratio of the 1σ value of the distribution of the period (1/fOUT, max) to the mean of the period. 1ms 10ms 100ms 1s Time This graph describes the low frequency stability of the VFC110: the ratio of the 1σ point of the distribution of 100 runs (where each mean frequency came from 1000 readings for each gate time) to the overall mean frequency. Repeatability (Bits) Frequency Repeatability (%) 0.0008 4 125 1000 5.00 VREF (V) −50 External One−Shot Capacitor "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VS = ±15V, unless otherwise noted. NONLINEARITY vs FULL−SCALE FREQUENCY NONLINEARITY vs INPUT VOLTAGE 1 0.6 0.01 0.4 fFS = 4MHz 0.2 0 0 −0.2 −0.01 −0.4 fFS = 1MHz −0.6 −0.02 −0.8 −1.0 0 1 2 3 4 5 6 Input Voltage (V) 7 8 9 10 Typical Nonlinearity (% of FSR) 0.8 0.02 4MHz FS Linearity Error (% of FSR) 1MHz FS Linearity Error (% of FSR) 1.0 0.1 0.01 0.001 104 105 106 107 Full−Scale Frequency (Hz) 5 "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 connected to logic ground. The one-shot connection (pin 6) is not short-circuit protected. Short-circuits to ground may damage the device. OPERATION Figure 1 shows the connections required for operation at a full-scale output frequency of 4MHz. Only power supply bypass capacitors and an output pull-up resistor, RPU, are required for this mode of operation. A 0V to 10V input voltage produces a 0Hz to 4MHz output frequency. The internal input resistor, one-shot and integrator capacitors set the full-scale output frequency. The input is applied to the summing junction of the integrator amplifier through the 25kΩ internal input resistor. Pin 14 (the noninverting amplifier input) should be referred directly to the negative side of VIN. The common-mode range of the integrating amplifier is limited to approximately −1V to +1V referred to analog ground. This allows the noninverting input to Kelvin-sense the common connection of VIN, easily accommodating any ground-drop errors. The input impedance loading VIN is equal to the input resistor—approximately 25kΩ. The integrator capacitor’s value does not directly affect the output frequency, but determines the magnitude of the voltage swing on the integrator’s output. Using a CINT equal to COS provides an integrator output swing from 0V to approximately 1.5V. COMPONENT SELECTION Selection of the external resistor and capacitor type is important. Temperature drift of an external input resistor and one-shot capacitor will affect temperature stability of the output frequency. NPO ceramic capacitors will normally produce the best results. Silver-mica types will result in slightly higher drift, but may be adequate in many applications. A low temperature coefficient film resistor should be used for RIN. OPERATION AT LOWER FREQUENCIES The integrator capacitor serves as a charge bucket, where charge is accumulated from the input, VIN, and that charge is drained during the one-shot period. While the size of the bucket (capacitor value) is not critical, it must not leak. Capacitor leakage or dielectric absorption can affect the linearity and offset of the transfer function. High-quality ceramic capacitors can be used for values less than 0.01µF. Use caution with higher value ceramic capacitors. High-k ceramic capacitors may have voltage nonlinearities which can degrade overall linearity. Polystyrene, polycarbonate, or mylar film capacitors are superior for high values. The VFC110 can be operated at lower frequencies simply by limiting the input voltage to less than the nominal 10V full-scale input. To maintain a 10V FS input and highest accuracy, however, external components are required (see Table 1). Small adjustments may be required in the nominal values indicated. Integrator and one-shot capacitors are added in parallel to internal capacitors. Figure 2 illustrates the connections required for 100kHz full-scale output. The one-shot capacitor, COS, should be +VS VL +15V +5V 10 RPU 680Ω NC 1 12 11 8 2 14 fOUT 0MHz to 4MHz 50pF(1) 25kΩ(1) One− Shot 0V to V +10V IN 7 Logic Ground 5 NC VREF 4 −15V −VS 13 3 6 NC NC Analog Ground NOTE: (1) Nominal values (±20%). Figure 1. 4MHz Full-Scale Operation 6 "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 Table 1. Component Selection Table FULL-SCALE FREQUENCY, fFS chosen for the pull-up resistor may depend on the full-scale frequency and capacitance on the output line. Excessive capacitance on fOUT will cause a slow, rounded rising edge at the end of an output pulse. This effect can be minimized by using a pull-up resistor which sets the output current to its maximum of 8mA. The logic power supply can be any positive voltage up to +VS. EXTERNAL COMPONENTS RIN COS CINT 4MHz ∗ ∗ ∗ 2MHz 34kΩ 56pF ∗ 1MHz 40kΩ 150pF ∗ 500kHz 58kΩ 330pF 2nF ENABLE PIN 100kHz 44kΩ 2.2nF 10nF 50kHz 88kΩ 2.2nF 0.1µF 10kHz 44kΩ 22nF 0.1µF If left unconnected, the Enable input will assume a logic High level, enabling operation. Alternatively, the Enable input may be connected directly to +VS. Since an internal pull-up current is included, the Enable input may be driven by an open-collector logic signal. * Use internal component only. The values given were determined empirically to give the optimal performance, taking into consideration tradeoffs between linearity and jitter for each given full-scale frequency of operation. The capacitors listed were chosen from standard values of NPO ceramic type capacitors while the resistor values were rounded off. Larger CINT values may improve linearity, but may also increase frequency noise. A logic Low at the Enable input causes output pulses to cease. This is accomplished by interrupting the signal path through the one-shot circuitry. While disabled, all circuitry remains active and quiescent current is unchanged. Since no reset current pulses can occur while disabled, any positive input voltage will cause the integrator op amp to ramp negatively and saturate at its most negative output swing of approximately −0.7V. PULL-UP RESISTOR When the Enable input receives a logic High (greater than +2V), a reset current cycle is initiated (causing fOUT to go Low). The integrator ramps positively and normal operation is established. The time required for the output frequency to stabilize is equal to approximately one cycle of the final output frequency plus 1µs. The VFC110 frequency output is an open-collector transistor. A pull-up resistor should be connected from fOUT to the logic supply voltage, +VL. The output transistor is On during the one-shot period, causing the output to be a logic Low. The current flowing in this resistor should be limited to 8mA to assure a 0.4V maximum logic Low. The value +VL +VS 5kΩ Gain Trim VIN 44kΩ RIN CINT 10nF 1 12 10 11 RPU 8 0V to +10V NC 2 fOUT 0kHz to 100kHz One−Shot 14 7 5 VREF 4 −VS 13 3 NC 6 C OS 2.2nF High = Enable Low = Disable Figure 2. 100kHz Full-Scale Operation 7 "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 PRINCIPLE OF OPERATION The oscillation is regulated by the balance of current (or charge) between the input current and the time-averaged reset current. The equation of current balance is: The VFC110 uses a charge-balance technique to achieve high accuracy. The heart of this technique is an analog integrator formed by the integrator op amp, feedback capacitor CINT, and input resistor RIN. The integrator’s output voltage is proportional to the charge stored in CINT. An input voltage develops an input current of VIN/RIN, which is forced to flow through CINT. This current charges CINT, causing the integrator output voltage to ramp negatively. I IN + I IREF Duty Cycle V IN + I REF f OUT T O R IN where TO is the one-shot period and fOUT is the oscillation frequency. When the output of the integrator ramps to 0V, the comparator trips, triggering the one-shot. This connects the reference current, IREF, (approximately 1mA) to the integrator input during the one-shot period, TOS. This switched current causes the integrator output to ramp positively until the one-shot period ends. Then the cycle starts again. Effect of Smaller CINT Integrator Output (Pin 12) 0V TOS 1/f OUT fOUT REFERENCE VOLTAGE Using the Enable input, several VFCs’ outputs can be connected to a single output line. All disabled VFCs will have a high output impedance; one active VFC can then transmit on the output line. Since the disabled VFCs are not oscillating, they cannot interfere or lock with the operating VFC. Locking can occur when one VFC operates at nearly the same frequency as—or a multiple of—a nearby VFC. Coupling between the two may cause them to lock to the same or exact multiple frequency. It then takes a small incremental input voltage change to unlock them. Locking cannot occur when unneeded VFCs are disabled. The VREF output is useful for offsetting the transfer function and exciting sensors. Figure 3 shows VREF used to offset the transfer function of the VFC110 to achieve a bipolar input voltage range. Sub-surface zener reference circuitry is used for low noise and excellent temperature drift. Output current is specified to 10mA and current-limited to approximately 20mA. Excessive or variable loads on VREF can decrease frequency stability due to internal heating. +15V 1 R1 12 11 +5V 10 RPU 8 VIN fOUT R2 2 NC One−Shot 14 7 5 VREF IREF (∼1mA) 4 − 15 V 13 3 6 COS 5V Figure 3. Offsetting the Frequency Output 8 NC "#$$% www.ti.com SBVS021A − OCTOBER 1988 − REVISED APRIL 2007 MEASURING THE OUTPUT FREQUENCY characteristic curve Frequency Count Repeatability vs Counter Gate Time shows the effect of noise as the counter gate time is varied. It shows the one standard deviation (1σ) count variation (as a percentage of FS counts) versus counter gate time. To complete an integrating A/D conversion, the output frequency of the VFC110 must be counted. Simple frequency counting is accomplished by counting output pulses for a reference time (usually derived from a crystal oscillator). This can be implemented with counter/timer peripheral chips available for many popular microprocessor families. Many microcontrollers have counter inputs that can be programmed for frequency measurement. FREQUENCY-TO-VOLTAGE CONVERSION The VFC110 can also be connected as a frequency-to-voltage converter (Figure 4). Input frequency pulses are applied to the comparator input. A negative-going pulse crossing 0V initiates a reference current pulse which is averaged by the integrator op amp. The values of the one-shot capacitor and feedback resistor (same as RIN) are determined with Table 1. The input frequency pulse must not remain negative for longer than the duration of the one-shot period. Figure 4 shows the required timing to assure this. If the negative-going input frequency pulses are longer in duration, the capacitive coupling circuit shown can be used. Level shift or capacitive coupling circuitry should not provide pulses which go lower than −5V or damage to the comparator input may occur. Since fOUT is an open-collector device, the negative-going edge provides the fastest logic transition. Clocking the counter on the falling edge will provide the best results in noisy environments. Frequency can also be measured by accurately timing the period of one or more cycles of the VFC output. Frequency must then be computed since it is inversely proportional to the measured period. This measurement technique can provide higher measurement resolution in short conversion times. It is the method used in most high-performance laboratory frequency counters. It is usually necessary to offset the transfer function so 0V input causes a finite frequency out. Otherwise the output period (and therefore the conversion time) approaches infinity. This frequency-to-voltage converter operates by averaging (filtering) the reference current pulses triggered on every falling edge at the frequency input. Voltage ripple with a frequency equal to the input will be present in the output voltage. The magnitude of this ripple voltage is inversely proportional to the integrator capacitor. The ripple can be made arbitrarily small with a large capacitor, but at the sacrifice of settling time. The R-C time constant of CINT and RIN determine the settling behavior. A better compromise between output ripple and settling time can be achieved by adding a low-pass filter following the voltage output. FREQUENCY NOISE Frequency noise (small random variation in the output frequency) limits the useful resolution of fast frequency measurement techniques. Long measurement time averages the effect of frequency noise and achieves the maximum useful resolution. The VFC110 is designed to minimize frequency noise and allows improved useful resolution with short measurement times. The typical L ong Pulse s O K +V S V O U T = 0 to 10V R IN 12k Ω fIN +VS CINT 1n F 2 .2k Ω 1 12 11 10 1k Ω 8 NC fIN TTL 4.7k Ω −V 1 /1 0f F S m ax NC 2 One−Shot 14 7 S 5 NC VREF 4 − VS 13 3 6 COS NC Figure 4. Frequency-to-Voltage Conversion 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) VFC110AP ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -25 to 85 VFC110AP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of