VFC110AG

® VFC110 High-Frequency VOLTAGE-TO-FREQUENCY CONVERTER FEATURES q HIGH-FREQUENCY OPERATION: 4MHz FS max q EXCELLENT LINEARITY: ±0.02% typ at 2MHz q PRECISION 5V REFERENCE q DISABLE PIN q LOW JITTER APPLICATIONS q INTEGRATING A/D CONVERSION q PROCESS CONTROL q VOLTAGE ISOLATION q VOLTAGE-CONTROLLED OSCILLATOR q FM TELEMETRY DESCRIPTION The VFC110 voltage-to-frequency converter is a thirdgeneration VFC offering improved features and performance. These include higher frequency operation, an on-board precision 5V reference and a Disable function. The precision 5V reference can be used for offsetting the VFC transfer function, as well as exciting transducers or bridges. The Enable pin allows several VFCs’ outputs to be paralleled, multiplexed, or simply to shut off the VFC. The open-collector frequency I IN 1 VOUT 12 Comparator 11 output is TTL/CMOS-compatible. The output may be isolated by using an opto-coupler or transformer. Internal input resistor, one-shot and integrator capacitors simplify applications circuits. These components are trimmed for a full-scale output frequency of 4MHz at 10V input. No additional components are required for many applications. The VFC110 is packaged in plastic and ceramic 14-pin DIPs. Industrial and military temperature range gradeouts are available. +VS 10 8 f OUT V IN 2 Input Common 14 One-Shot 7 Digital Ground 5 Enable V REF 4 –VS 13 Analog Ground 3 5V 6 C OS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1988 Burr-Brown Corporation PDS-861B Printed in U.S.A. October, 1993 SPECIFICATIONS At TA = +25°C and VS = ±15V, unless otherwise noted. VFC110BG PARAMETER VOLTAGE-TO-FREQUENCY OPERATION Nonlinearity(1): fFS = 100kHz fFS = 1MHz fFS = 2MHz fFS = 4MHz Gain Error, f = 1MHz Gain Drift, f = 1MHz Relative to VREF PSRR INPUT Full Scale Input Current IB– (Inverting Input) IB+ (Non-Inverting Input) VOS VOS Drift INTEGRATOR AMPLIFIER OUTPUT Output Voltage Range Output Current Drive Capacitive Load COMPARATOR INPUT IB (Input Bias Current) Trigger Voltage Input Voltage Range OPEN COLLECTOR OUTPUT VO Low ILEAKAGE Fall Time Delay to Rise Settling Time REFERENCE VOLTAGE Voltage Voltage Drift Load Regulation PSRR Current Limit ENABLE INPUT VHIGH (fOUT Enabled) VLOW (fOUT Disabled) IHIGH ILOW POWER SUPPLY Voltage, ±VS Current TEMPERATURE RANGE Specified AG, BG, AP SG Storage AG, BG, SG AP * Same specifications as VFC110BG. NOTE: (1) Nonlinearity measured from 1V to 10V input. CONDITIONS COS = 2.2nF, RIN = 44kΩ COS = 150pF, RIN = 40kΩ COS = 56pF, RIN = 34kΩ COS = (Int), RIN = (Int) COS = 150pF, RIN = 40kΩ Specified Temp Range Specified Temp Range VS = ±8V to ±18V MIN TYP 0.005 0.01 0.02 1 MAX 0.01 0.05 VFC110AG/SG/AP MIN TYP 0.01 * * 5 50 50 0.05 250 15 250 Specified Temp Range RL = 2kΩ No Oscillations –0.2 5 35 +VS – 4 20 10 –5 ±50 –5 +VS * * * 500 60 3 * * * 10 * * * * * * 20 * 100 0.1 * 100 3 * 100 MAX 0.05 0.1 UNITS %FS %FS %FS %FS % ppm/°C ppm/°C %/V µA nA nA mV µV/°C V mA nF µA mV V V µA ns ns To Specified Linearity for a Full-Scale Input Step 4.97 IO = 0 to 10mA VS = ±8V to ±18V Short Circuit Specified Temp Range Specified Temp Range 0.4 0.1 1 * 25 * 25 * One Pulse of New Frequency Plus 1µs 5 2 5 20 5.03 20 10 * * * * * * 50 * 15 2 V ppm/°C mV mV/V mA V V µA µA V mA * 0.4 0.1 1 * * ±18 16 * * * * * * ±8 ±15 13 –25 –55 –65 –40 +85 +125 +150 +125 * * °C °C °C °C * * * * The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® VFC110 2 PIN CONFIGURATION Top View I IN V IN +5VREF Out –VS Enable COS Digital Ground 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Input Common Analog Common VOUT Comparator In +VS NC f OUT ABSOLUTE MAXIMUM RATINGS DIP Power Supply Voltages (+VS to –VS) ................................................ 40V fOUT Sink Current ............................................................................ 50mA Comparator In Voltage .......................................................... –5V to +VS Enable Input ........................................................................... +VS to –VS Integrator Common-Mode Voltage .................................. –1.5V to +1.5V Integrator Differential Input Voltage ................................ +0.5V to –0.5V Integrator Out (short-circuit) ..................................................... Indefinite VREF Out (short-circuit) .............................................................. Indefinite Operating Temperature Range G Package ................................................................ –55°C to +125°C P Package ................................................................... –40°C to +85°C Storage Temperature G Package ................................................................ –60°C to +150°C P Package ................................................................. –40°C to +125°C Lead Temperature (soldering, 10s) ............................................. +300°C PACKAGE INFORMATION PRODUCT VFC110AG VFC110BG VFC110SG VFC110AP PACKAGE 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Plastic DIP PACKAGE DRAWING NUMBER(1) 169 169 169 010 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION PRODUCT VFC110AG VFC110BG VFC110SG VFC110AP PACKAGE Ceramic DIP Ceramic DIP Ceramic DIP Plastic DIP TEMPERATURE RANGE –25°C to +85°C –25°C to +85°C –55 °C to +125°C –25°C to +85°C ® 3 VFC110 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, unless otherwise noted. FULL-SCALE FREQUENCY vs EXTERNAL ONE-SHOT CAPACITOR 10M 18 16 QUIESCENT CURRENT vs TEMPERATURE Full Scale Frequency (Hz) Quiescent Current (mA) 14 12 10 8 6 4 2 IQ+ 1M IQ– 100k R IN = 40k Ω 10k 10pF 100pF 1nF 10nF 100nF 0 –50 –25 0 25 50 75 100 125 External One-Shot Capacitor Temperature (°C) REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT 5.01 Full Scale Frequency (ppm/°C) TYPICAL FULL SCALE GAIN DRIFT vs FULL SCALE FREQUENCY 1000 5 V REF (V) 4.99 100 A Grade, S Grade B Grade 4.98 Short Circuit Current Limit 4.97 4.96 0 2 4 6 8 10 12 14 16 18 20 22 Output Current (mA) 10 10k 100k 1M 10M Full Scale Frequency (Hz) JITTER vs FULL SCALE FREQUENCY 500 Frequency Repeatability (%) 0.001 0.0008 FREQUENCY COUNT REPEATABILITY vs COUNTER GATE TIME 17 400 Jitter (ppm) 0.0006 0.0004 300 f FS = 100kHz 18 200 0.0002 f FS = 1MHz 0.0001 1ms 19 100 0 10k 100k 1M 10M 10ms Time 100ms 1s Full Scale Frequency (Hz) Jitter is the ratio of the 1σ value of the distribution of the period (1/fOUT , max) to the mean of the period. This graph describes the low frequency stability of the VFC110: the ratio of the 1σ point of the distribution of 100 runs (where each mean frequency came from 1000 readings for each gate time) to the overall mean frequency. ® VFC110 4 Repeatability (Bits) TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. NONLINEARITY vs INPUT VOLTAGE 1 1MHz FS Linearity Error (% of FSR) NONLINEARITY vs FULL SCALE FREQUENCY 1 4MHz FS Linearity Error (% of FSR) 0.02 0.8 0.6 0.01 f FS = 4MHz 0 0.4 0.2 0 –0.2 Typical Nonlinearity (% of FSR) 0.1 –0.01 f FS = 1MHz –0.02 0 1 2 3 4 5 6 7 8 9 10 –0.4 –0.6 –0.8 –1 0.01 0.001 10 4 Input Voltage (V) 10 5 10 6 10 7 Full Scale Frequency (Hz) OPERATION Figure 1 shows the connections required for operation at a full-scale output frequency of 4MHz. Only power supply bypass capacitors and an output pull-up resistor, RPU, are required for this mode of operation. A 0V to 10V input voltage produces a 0Hz to 4MHz output frequency. The internal input resistor, one-shot and integrator capacitors set the full-scale output frequency. The input is applied to the summing junction of the integrator amplifier through the 25kΩ internal input resistor. Pin 14 (the non-inverting amplifier input) should be referred directly to the negative side of VIN. The common-mode range of the integrating amplifier is limited to approximately –1V to +1V referred to analog ground. This allows the non-inverting input to Kelvin-sense the common connection of VIN, easily accommodating any ground-drop errors. The input impedance loading VIN is equal to the input resistor—approximately 25kΩ. OPERATION AT LOWER FREQUENCIES The VFC110 can be operated at lower frequencies simply by limiting the input voltage to less than the nominal 10V fullscale input. To maintain a 10V FS input and highest accuracy, however, external components are required (see Table I). Small adjustments may be required in the nominal values indicated. Integrator and one-shot capacitors are added in parallel to internal capacitors. Figure 2 shows the connections required for 100kHz full scale output. The one-shot capacitor, COS, should be connected to logic ground. The one-shot connection (pin 6) is not short-circuit protected. Short-circuits to ground may damage the device. +VS +15V NC 1 12 11 10 8 2 14 0 to +10V VIN 25k Ω * 50pF* One-Shot VL +5V RPU 680 Ω f OUT 0 to 4MHz 7 Logic Ground 5 NC V REF 4 –15V * Nominal Values (±20%) –VS 13 3 NC 6 NC Analog Ground FIGURE 1. 4MHz Full-Scale Operation. ® 5 VFC110 The integrator capacitor’s value does not directly affect the output frequency, but determines the magnitude of the voltage swing on the integrator’s output. Using a CINT equal to COS provides an integrator output swing from 0V to approximately 1.5V. linearity and offset of the transfer function. High-quality ceramic capacitors can be used for values less than 0.01µF. Use caution with higher value ceramic capacitors. High-k ceramic capacitors may have voltage nonlinearities which can degrade overall linearity. Polystyrene, polycarbonate, or mylar film capacitors are superior for high values. PULL-UP RESISTOR The VFC110’s frequency output is an open-collector transistor. A pull-up resistor should be connected from fOUT to the logic supply voltage, +VL. The output transistor is On during the one-shot period, causing the output to be a logic Low. The current flowing in this resistor should be limited to 8mA to assure a 0.4V maximum logic Low. The value chosen for the pull-up resistor may depend on the full-scale frequency and capacitance on the output line. Excessive capacitance on fOUT will cause a slow, rounded rising edge at the end of an output pulse. This effect can be minimized by using a pullup resistor which sets the output current to its maximum of 8mA. The logic power supply can be any positive voltage up to +VS. ENABLE PIN If left unconnected, the Enable input will assume a logic High level, enabling operation. Alternatively, the Enable input may be connected directly to +VS. Since an internal pull-up current is included, the Enable input may be driven by an open-collector logic signal. A logic Low at the Enable input causes output pulses to cease. This is accomplished by interrupting the signal path through the one-shot circuitry. While disabled, all circuitry remains active and quiescent current is unchanged. Since no reset current pulses can occur while disabled, any positive input voltage will cause the integrator op amp to ramp negatively and saturate at its most negative output swing of approximately –0.7V. COMPONENT SELECTION Selection of the external resistor and capacitor type is important. Temperature drift of an external input resistor and oneshot capacitor will affect temperature stability of the output frequency. NPO ceramic capacitors will normally produce the best results. Silver-mica types will result in slightly higher drift, but may be adequate in many applications. A low temperature coefficient film resistor should be used for RIN. The integrator capacitor serves as a “charge bucket,” where charge is accumulated from the input, VIN, and that charge is drained during the one-shot period. While the size of the bucket (capacitor value) is not critical, it must not leak. Capacitor leakage or dielectric absorption can affect the FULL-SCALE FREQUENCY, fFS 4MHz 2MHz 1MHz 500kHz 100kHz 50kHz 10kHz EXTERNAL COMPONENTS RIN * 34kΩ 40kΩ 58kΩ 44kΩ 88kΩ 44kΩ COS * 56pF 150pF 330pF 2.2nF 2.2nF 22nF CINT * * * 2nF 10nF 0.1µF 0.1µF * Use internal component only. The values given were determined empirically to give the optimal performance, taking into consideration tradeoffs between linearity and jitter for each given full scale frequency of operation. The capacitors listed were chosen from standard values of NPO ceramic type capacitors while the resistor values were rounded off. Larger CINT values may improve linearity, but may also increase frequency noise. TABLE I. Component Selection Table. 5k Ω Gain Trim 44k Ω R IN CINT +VS +VL 1 10nF 12 11 10 RPU 8 f OUT 0 to 100kHz One-Shot 7 5 V REF VIN 0 to +10V NC 2 14 4 –VS 13 3 NC 6 C OS 2.2nF High = Enable Low = Disable FIGURE 2. 100kHz Full-Scale Operation. ® VFC110 6 PRINCIPLE OF OPERATION The VFC110 uses a charge-balance technique to achieve high accuracy. The heart of this technique is an analog integrator formed by the integrator op amp, feedback capacitor CINT, and input resistor RIN. The integrator’s output voltage is proportional to the charge stored in CINT. An input voltage develops an input current of VIN/RIN, which is forced to flow through CINT. This current charges CINT, causing the integrator output voltage to ramp negatively. When the output of the integrator ramps to 0V, the comparator trips, triggering the one-shot. This connects the reference current, IREF, to the integrator input during the one-shot period, TOS. This switched current causes the integrator output to ramp positively until the one-shot period ends. Then the cycle starts again. The oscillation is regulated by the balance of current (or charge) between the input current and the time-averaged When the Enable input receives a logic High (greater than +2V), a reset current cycle is initiated (causing fOUT to go Low). The integrator ramps positively and normal operation is established. The time required for the output frequency to stabilize is equal to approximately one cycle of the final output frequency plus 1µs. Using the Enable input, several VFCs’ outputs can be connected to a single output line. All disabled VFCs will have a high output impedance; one active VFC can then transmit on the output line. Since the disabled VFCs are not oscillating, they cannot interfere or “lock” with the operating VFC. Locking can occur when one VFC operates at nearly the same frequency as—or a multiple of—a nearby VFC. Coupling between the two may cause them to lock to the same or exact multiple frequency. It then takes a small incremental input voltage change to unlock them. Locking cannot occur when unneeded VFCs are disabled. Integrator Output (Pin 12) 0V TOS 1/fOUT fOUT Effect of Smaller C INT reset current. The equation of current balance is IIN = IREF • Duty Cycle VIN/RIN = IREF • fOUT • TO where TO is the one-shot period and fOUT is the oscillation frequency. REFERENCE VOLTAGE The VREF output is useful for offsetting the transfer function and exciting sensors. Figure 3 shows VREF used to offset the transfer function of the VFC110 to achieve a bipolar input voltage range. Sub-surface zener reference circuitry is used for low noise and excellent temperature drift. Output current is specified to 10mA and current-limited to approximately 20mA. Excessive or variable loads on VREF can decrease frequency stability due to internal heating. MEASURING THE OUTPUT FREQUENCY To complete an integrating A/D conversion, the output frequency of the VFC110 must be counted. Simple frequency counting is accomplished by counting output pulses for a reference time (usually derived from a crystal oscilla- +15V R1 VIN R2 2 NC 14 7 5 NC V REF One-Shot 1 12 11 10 8 +5V RPU f OUT 4 –15V 13 5V 3 6 C OS FIGURE 3. Offsetting the Frequency Output. ® 7 VFC110 tor). This can be implemented with counter/timer peripheral chips available for many popular microprocessor families. Many micro-controllers have counter inputs that can be programmed for frequency measurement. Since fOUT is an open-collector device, the negative-going edge provides the fastest logic transition. Clocking the counter on the falling edge will provide the best results in noisy environments. Frequency can also be measured by accurately timing the period of one or more cycles of the VFC’s output. Frequency must then be computed since it is inversely proportional to the measured period. This measurement technique can provide higher measurement resolution in short conversion times. It is the method used in most high-performance laboratory frequency counters. It is usually necessary to offset the transfer function so 0V input causes a finite frequency out. Otherwise the output period (and therefore the conversion time) approaches infinity. FREQUENCY NOISE Frequency noise (small random variation in the output frequency) limits the useful resolution of fast frequency measurement techniques. Long measurement time averages the effect of frequency noise and achieves the maximum useful resolution. The VFC110 is designed to minimize frequency noise and allows improved useful resolution with short measurement times. The typical curve “Frequency Count Repeatability vs Counter Gate Time” shows the effect of noise as the counter gate time is varied. It shows the one standard deviation (1σ) count variation (as a percentage of FS counts) versus counter gate time. FREQUENCY-TO-VOLTAGE CONVERSION The VFC110 can also be connected as a frequency-tovoltage converter (Figure 4). Input frequency pulses are applied to the comparator input. A negative-going pulse crossing 0V initiates a reference current pulse which is averaged by the integrator op amp. The values of the oneshot capacitor and feedback resistor (same as RIN) are determined with Table I. The input frequency pulse must not remain negative for longer than the duration of the one-shot period. Figure 4 shows the required timing to assure this. If the negative-going input frequency pulses are longer in duration, the capacitive coupling circuit shown can be used. Level shift or capacitive coupling circuitry should not provide pulses which go lower than –5V or damage to the comparator input may occur. This frequency-to-voltage converter operates by averaging (filtering) the reference current pulses triggered on every falling edge at the frequency input. Voltage ripple with a frequency equal to the input will be present in the output voltage. The magnitude of this ripple voltage is inversely proportional to the integrator capacitor. The ripple can be made arbitrarily small with a large capacitor, but at the sacrifice of settling time. The R-C time constant of CINT and RIN determine the settling behavior. A better compromise between output ripple and settling time can be achieved by adding a low-pass filter following the voltage output. Long Pulses OK +VS R IN 12k Ω VOUT = 0 to 10V fIN 1nF 2.2k Ω 1 C INT 12 11 10 +VS 1k Ω fIN TTL 1/10f FS max 4.7k Ω –VS NC 2 14 One-Shot 8 NC 7 5 NC V REF 4 –VS 13 3 NC 6 C OS FIGURE 4. Frequency-to-Voltage Conversion. ® VFC110 8