CY7C1248V18-300BZC

CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 375 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 750 MHz) @ 375 MHz • Read latency of 2.0 clock cycles • Two input clocks (K and K) for precise DDR timing • • • • • • • • • — SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high speed systems Data valid pin (QVLD) to indicate valid data on the output Synchronous internally self-timed writes Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1] HSTL inputs and variable drive HSTL output buffers Available in 165-ball FBGA package (15 x 17 x 1.4 mm) Offered in both in Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words (CY7C1246V18), 9-bit words (CY7C1257V18), 18-bit words (CY7C1248V18), or 36-bit words (CY7C1250V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, which share the same physical pins with the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from individual DDR SRAMs in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations With Read Cycle Latency of 2.0 cycles: CY7C1246V18 – 4M x 8 CY7C1257V18 – 4M x 9 CY7C1248V18 – 2M x 18 CY7C1250V18 – 1M x 36 Selection Guide 375 MHz Maximum Operating Frequency Maximum Operating Current 375 1210 333 MHz 333 1080 300 MHz 300 1000 Unit MHz mA Note 1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD. Cypress Semiconductor Corporation Document Number: 001-06348 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 15, 2007 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Logic Block Diagram (CY7C1246V18) A(20:0) 21 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 2M x 8 Array Write Reg 2M x 8 Array 8 Output Logic Control CLK Gen. R/W Read Data Reg. 16 Control Logic CQ CQ 8 Reg. 8 DQ[7:0] QVLD VREF R/W NWS[1:0] 8 8 Reg. Reg. 8 Logic Block Diagram (CY7C1257V18) A(20:0) 21 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 2M x 9 Array Write Reg 2M x 9 Array 9 Output Logic Control CLK Gen. R/W Read Data Reg. 18 Control Logic CQ CQ 9 Reg. 9 DQ[8:0] QVLD VREF R/W BWS[0] 9 9 Reg. Reg. 9 Document Number: 001-06348 Rev. *C Page 2 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Logic Block Diagram (CY7C1248V18) A(19:0) 20 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 1M x 18 Array Write Reg 1M x 18 Array 18 Output Logic Control CLK Gen. R/W Read Data Reg. 36 Control Logic 18 18 Reg. Reg. Reg. 18 18 18 CQ CQ DQ[17:0] QVLD VREF R/W BWS[1:0] Logic Block Diagram (CY7C1250V18) A(18:0) 19 Write Add. Decode LD K K DOFF Read Add. Decode Address Register Write Reg 512K x 36 Array Write Reg 512K x 36 Array 36 Output Logic Control CLK Gen. R/W Read Data Reg. 72 Control Logic 36 36 Reg. Reg. Reg. 36 36 36 CQ CQ DQ[35:0] QVLD VREF R/W BWS[3:0] Document Number: 001-06348 Rev. *C Page 3 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Pin Configurations 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1246V18 (4M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI CY7C1257V18 (4M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC DQ8 TDI Document Number: 001-06348 Rev. *C Page 4 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1248V18 (2M x 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI CY7C1250V18 (1M x 36) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 A DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI Document Number: 001-06348 Rev. *C Page 5 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Pin Definitions Pin Name DQ[x:0] IO Pin Description Input/Output- Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during Synchronous valid write operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the K and K clocks during read operations. When read access is deselected, Q[x:0] are automatically tri-stated. CY7C1246V18 − DQ[7:0] CY7C1257V18 − DQ[8:0] CY7C1248V18 − DQ[17:0] CY7C1250V18 − DQ[35:0] InputSynchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. Synchronous This definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K. Nibble Write Select 0, 1, Active LOW (CY7C1246V18 only). Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select causes the corresponding nibble of data to be ignored and not written into the device. LD NWS0, NWS1 InputSynchronous BWS0, BWS1, BWS2, BWS3 InputByte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks Synchronous during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1257V18 − BWS0 controls D[8:0] CY7C1248V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1250V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select causes the corresponding byte of data to be ignored and not written into the device. InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operaSynchronous tions. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1246V18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1257V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1248V18, and 1M x 36 (2 arrays each of 512K x 36) for CY7C1250V18. InputSynchronous Read/Write Input. When LD is LOW, this input designates the access type (read Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times around edge of K. Valid output indicator InputClock InputClock Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode. A R/W QVLD K K CQ Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on page 22. Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on page 22. CQ Document Number: 001-06348 Rev. *C Page 6 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Pin Definitions (continued) Pin Name ZQ IO Input Pin Description Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. DOFF Input TDO TCK TDI TMS NC NC/72M NC/144M NC/288M VREF VDD VSS VDDQ Output Input Input Input N/A N/A N/A N/A InputReference Power Supply Power supply inputs to the core of the device. Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Document Number: 001-06348 Rev. *C Page 7 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Functional Overview The CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the rising edge of the input clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the input clocks (K and K). All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K\K). CY7C1248V18 is described in the following sections. The same basic descriptions apply to CY7C1246V18, CY7C1257V18, and CY7C1250V18. Read Operations The CY7C1248V18 is organized internally as a single array of 2M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). Following the next two K clock rising edges, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K and K). To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). When read access is deselected, the CY7C1248V18 completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive input clock (K). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Write Address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the information presented to D[17:0] is also stored into the Write Data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When write access is deselected, the device ignores all inputs after the pending write operations are completed. Byte Write Operations Byte write operations are supported by the CY7C1248V18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write enables the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation. Double Data Rate Operation The CY7C1248V18 enables high-performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C1248V18 requires two No Operation (NOP) cycles when transitioning from a read to a write cycle. At higher frequencies, some applications may require a third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a Posted Write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15%, is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on page 22. Valid Data Indicator (QVLD) QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR-II+ Document Number: 001-06348 Rev. *C Page 8 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. Delay Lock Loop (DLL) These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, DLL Considerations in QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be reset to lock to the desired frequency. During power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. Application Example Figure 1 shows the use of two DDR-II+ in an application. Figure 1. Application Example ZQ CQ/CQ KK ZQ CQ/CQ KK DQ A SRAM#1 LD R/W R = 250ohms DQ A SRAM#2 LD R/W R = 250ohms DQ Addresses BUS Cycle Start MASTER R/W (CPU or ASIC) Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Truth Table The truth table for the CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 follows.[2, 3, 4, 5, 6, 7] Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.0 cycle Latency) Load address; wait two cycle; read data on consecutive K and K rising edges. NOP: No Operation Standby: Clock Stopped K L-H LD L R/W L DQ D(A) at K(t + 1) ↑ DQ D(A + 1) at K(t + 1) ↑ L-H L H Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 2) ↑ L-H Stopped H X X X High-Z Previous State High-Z Previous State Notes 2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge. 3. Device powers up deselected with the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges. 7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document Number: 001-06348 Rev. *C Page 9 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Write Cycle Descriptions The write cycle descriptions table for CY7C1246V18 and CY7C1248V18 follows.[2, 8] BWS0/ BWS1/ NWS0 L NWS1 L K L–H K – Comments During the data portion of a write sequence : CY7C1246V18 − both nibbles (D[7:0]) are written into the device, CY7C1248V18 − both bytes (D[17:0]) are written into the device. L L – L-H During the data portion of a write sequence : CY7C1246V18 − both nibbles (D[7:0]) are written into the device, CY7C1248V18 − both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence : CY7C1246V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1248V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L H L–H L H – L–H During the data portion of a write sequence : CY7C1246V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1248V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence : CY7C1246V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1248V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. H L L–H H L – L–H During the data portion of a write sequence : CY7C1246V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1248V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. H H H H L–H – Write Cycle Descriptions The write cycle descriptions table for CY7C1257V18 follows.[2, 8] BWS0 L L H H K L-H – L-H – K – L-H – L-H Comments During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. Note 8. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are met. Document Number: 001-06348 Rev. *C Page 10 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Write Cycle Descriptions The write cycle descriptions table for CY7C1250V18 follows.[2, 8] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L-H – L-H – L-H – L-H – L-H – L-H – K – Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remain unaltered. L-H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remain unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remain unaltered. L-H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remain unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L-H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L-H No data is written into the device during this portion of a write operation. Document Number: 001-06348 Rev. *C Page 11 of 27 [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO should be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. Test Access Port – Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see “TAP Controller State Diagram” on page 14. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. Whether the output is active depends on the current state of the TAP state machine (see “Instruction Codes” on page 17). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO pins and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in “TAP Controller Block Diagram” on page 15. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. “Boundary Scan Order” on page 18 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page 17. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Instruction Codes” on page 17. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. Document Number: 001-06348 Rev. *C Page 12 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is in a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is issued during the Update-IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required — that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-06348 Rev. *C Page 13 of 27 [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 TAP Controller State Diagram The state diagram for the TAP controller follows.[9] 1 TEST-LOGIC RESET 0 1 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 0 SHIFT-IR 1 0 1 EXIT1-IR 0 1 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06348 Rev. *C Page 14 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 Instruction Register 31 30 29 . . 2 1 0 1 0 Selection Circuitry TDO Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range[10, 11, 12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND ≤ VI ≤ VDD Test Conditions IOH = −2.0 mA IOH = −100 µA IOL = 2.0 mA IOL = 100 µA –0.3 −5 Min 1.4 1.6 0.4 0.2 0.65VDD VDD + 0.3 0.35VDD 5 Max Unit V V V V V V µA Notes 10. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20. 11. Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than tCYC/2). 12. All voltage refers to ground. Document Number: 001-06348 Rev. *C Page 15 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 TAP AC Switching Characteristics Over the Operating Range[13, 14] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min 50 20 Max Unit ns MHz ns ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions.[14] Figure 2. TAP Timing and Test Conditions 0.9V 50Ω TDO Z0 = 50Ω 0V CL = 20 pF ALL INPUT PULSES 1.8V 0.9V (a) GND tTH tTL Test Clock TCK tTMSS tTMSH tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Notes 13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 14. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-06348 Rev. *C Page 16 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Identification Register Definitions Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) Value CY7C1246V18 000 11010111100000111 00000110100 CY7C1257V18 000 11010111100001111 00000110100 CY7C1248V18 000 11010111100010111 00000110100 CY7C1250V18 000 Description Version number. 11010111100100111 Defines the type of SRAM. 00000110100 Enables unique identification of SRAM vendor. Indicates the presence of an ID register. 1 1 1 1 Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 109 Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input/output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input/output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the input/output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-06348 Rev. *C Page 17 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal Document Number: 001-06348 Rev. *C Page 18 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During power up, when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock. DLL Constraints • DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. • The DLL functions at frequencies down to 120 MHz. • If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. Power Up Sequence • Apply power with DOFF tied HIGH (all other inputs can be HIGH or LOW) — Apply VDD before VDDQ — Apply VDDQ before VREF or at the same time as VREF • Provide stable power and clock (K, K) for 2048 cycles to lock the DLL Power Up Waveforms Figure 3. Power Up Waveforms K K ~ ~ Unstable Clock > 2048 Stable Clock Start Normal Operation Clock Start (Clock Starts after VDD/VDDQ is Stable) VDD/VDDQ VDD/VDDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to VDDQ) DOFF Document Number: 001-06348 Rev. *C ~ ~ Page 19 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied . –55°C to + 125°C Supply Voltage on VDD Relative to GND....... –0.5V to + 2.9V Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD DC Applied to Outputs in High-Z..........–0.5V to VDDQ + 0.3V DC Input Voltage[11] ...............................–0.5V to VDD + 0.3V Range Com’l Ind’l Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current..................................................... >200 mA Operating Range Ambient Temperature 0°C to +70°C –40°C to +85°C VDD[15] 1.8 ± 0.1V VDDQ[15] 1.4V to VDD Electrical Characteristics Over the Operating Range [12] DC Electrical Characteristics Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Input Reference Voltage[18] VDD Operating Supply GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled Typical Value = 0.75V VDD = Max., IOUT = 0 mA, 300 MHz f = fMAX = 1/tCYC 333 MHz 375 MHz ISB1 Automatic Power Down Current Max. VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 300 MHz 333 MHz 375 MHz Note 16 Note 17 IOH = –0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min 1.7 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.15 –2 –2 0.68 0.75 Typ 1.8 1.5 Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.15 VREF – 0.1 2 2 0.95 1000 1080 1210 290 300 320 Unit V V V V V V V V µA µA V mA mA mA mA mA mA AC Input Requirements Over the Operating Range [11] Parameter VIH VIL \ Description Input HIGH Voltage Input LOW Voltage Test Conditions Min. VREF + 0.2 –0.24 Typ. – – Max. VDDQ + 0.24 VREF – 0.2 Unit V V Notes 15. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω. 17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω. 18. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger. VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller. Document Number: 001-06348 Rev. *C Page 20 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. 5 4 5 Unit pF pF pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 165 FBGA Package 16.25 2.91 Unit °C/W °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50Ω RL = 50Ω VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50Ω ALL INPUT PULSES 1.25V 0.75V [19] ZQ (a) RQ = 250Ω INCLUDING JIG AND SCOPE RQ = 250Ω (b) Note 19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms. Document Number: 001-06348 Rev. *C Page 21 of 27 [+] [+] Feedback CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 Switching Characteristics Over the Operating Range [19, 20] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tSA tSC tSCDDR tSD tHA tHC tHCDDR tHD tCO tDOH tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCLZ tQVLD tKC Var tKC lock tKC Reset tKHKH tKHKL tKLKH tKHKH tAVKH tIVKH tIVKH tDVKH tKHAX tKHIX tKHIX tKHDX tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHQZ tCHQX1 tCQHQVLD tKC Var tKC lock tKC Reset K Clock Cycle Time Input Clock (K/K) HIGH Input Clock (K/K) LOW Description VDD(Typical) to the first Access[21] 375 MHz 1 2.66 0.4 0.4 – 8.4 – – – – – – – – – – – 0.45 – 0.45 – 0.2 – – – 0.45 – 333 MHz 1 3.0 0.4 0.4 1.28 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – –0.45 – –0.45 – –0.2 1.03 1.03 – –0.45 – 8.4 – – – – – – – – – – – 0.45 – 0.45 – 0.2 – – – 0.45 – 300 MHz 1 3.3 0.4 0.4 1.40 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – –0.45 – –0.45 – –0.2 1.15 1.15 – –0.45 – 8.4 – – – – – – – – – – – 0.45 – 0.45 – 0.2 – – – 0.45 – Min Max Min Max Min Max Unit ms ns tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles ns K Clock Rise to K Clock Rise (rising edge to rising edge) 1.13 Address Setup to K Clock Rise Control Setup to K Clock Rise (LD, R/W) Double Data Rate Control Setup to Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Setup to Clock (K/K) Rise Address Hold after K Clock Rise Control Hold after K Clock Rise (LD, R/W) Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K/K) Rise K/K Clock Rise to Data Valid K/K Clock Rise to Echo Clock Valid Echo Clock Hold after K/K Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Output Clock (CQ/CQ) HIGH[22] CQ Clock Rise to CQ Clock Rise[22] (rising edge to rising edge) Clock (K/K) Rise to High-Z (Active to High-Z)[23, 24] Clock (K/K) Rise to Low-Z [23, 24] [25] Setup Times 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – – –0.45 – –0.2 0.88 0.88 – –0.45 Hold Times Output Times Data Output Hold after K/K Clock Rise (Active to Active) –0.45 Echo Clock High to QVLD Valid Clock Phase Jitter DLL Lock Time (K) K Static to DLL Reset[26] –0.20 0.20 –0.20 0.20 –0.20 0.20 – 2048 30 0.20 – – – 2048 30 0.20 – – – 2048 30 0.20 – – DLL Timing Notes 20. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being operated and will output data with the output timing of that frequency range. 21. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 22. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production. 23. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±100 mV from steady-state voltage. 24. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 25. tQVLD spec is applicable for both rising and falling edges of QVLD signal. 26. Hold to >VIH or