830S21AMI-01LF

1-TO-1 2.5V, 3.3V DIFFERENTIAL-TOLVCMOS/LVTTL TRANSLATOR General Description ICS830S21I-01 is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. ICS830S21I-01 Features • • • • • • • • • • One LVCMOS/LVTTL output Differential CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Maximum output frequency: 350MHz Part-to-part skew: 525ps (maximum) Additive phase jitter, RMS: 0.11ps (typical) Small 8 lead SOIC package saves board space Full 3.3V and 2.5V operating supply -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package ICS Block Diagram CLK Pullup/Pulldown Q nCLK Pullup/Pulldown OE Pullup Pin Assignment nc CLK nCLK OE 1 2 3 4 8 7 6 5 VDD Q nc GND ICS830S21I-01 8-Lead SOIC 3.9mm x 4.9mm x 1.375mm package body M Package Top View IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 1 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Table 1. Pin Descriptions Number 1, 6 2 3 4 5 7 8 Name nc CLK nCLK OE GND Q VDD Unused Input Input Input Power Output Power Pullup/ Pulldown Pullup/ Pulldown Pullup Type Description No connect. Non-inverting differential clock input. Inverting differential clock input. Output enable pin. See Table 3. LVCMOS / LVTTL interface levels. Power supply ground. Single-ended clock output. LVCMOS / LVTTL interface levels. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance VDD = 3.465V VDD = 2.625V Output Impedance VDD = 3.3V VDD = 2.5V Test Conditions Minimum Typical 4 51 51 10 8 10 12 Maximum Units pF kΩ kΩ pF pF ROUT Ω Ω Function Tables Table 3. OE Configuration Table Input OE 0 1 (default) Operation Output Q is in a high-impedance state. Output Q is enabled. IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 2 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 93.1°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 12 Units V mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 11 Units V mA Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol VIH Parameter Input High Voltage Test Conditions VDD = 3.3V VDD = 2.5V Input Low Voltage Input High Current Input Low Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.3V VDD = 2.5V VDD = 3.3V or 2.5V -150 2.6 1.8 0.5 Minimum 2.2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 10 Units V V V V µA µA V V V VIL IIH IIL VOH VOL NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 3 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Table 4D. Differential DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -150 0.15 GND + 0.5 1.5 VDD – 0.85 Minimum Typical Maximum 150 Units µA µA V V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. AC Electrical Characteristics Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol fMAX tPD tsk(pp) tjit tR / tF odc tEN tDIS Parameter Output Frequency Propagation Delay, NOTE 1 Part-to-Part Skew; NOTE 2, 3 Buffer Additive Phase jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 350MHz, Integration Range (12kHz – 20MHz) 20% to 80% ƒ ≤ 266MHz 85 47 0.11 500 53 8 8 0.95 Test Conditions Minimum Typical 350 1.95 525 Maximum Units MHz ns ps ps ps % ns ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol fMAX tPD tsk(pp) tjit tR / tF odc tEN tDIS Parameter Output Frequency Propagation Delay, NOTE 1 Part-to-Part Skew; NOTE 2, 3 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 350MHz, Integration Range (12kHz – 20MHz) 20% to 80% ƒ ≤ 266MHz 125 47 0.11 500 53 8 8 1 Test Conditions Minimum Typical 350 2 550 Maximum Units MHz ns ps ps ps % ns ns For NOTES, see Table 5A above. IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 4 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 350MHz 12kHz to 20MHz = 0.11ps (typical) SSB Phase Noise dBc/Hz Offset Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 5 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Parameter Measurement Information 1.65V±5% 1.25V±5% VDD SCOPE Qx VDD SCOPE Qx LVCMOS GND LVCMOS GND -1.65V±5% -1.25V±5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit VDD nCLK CLK nCLK V PP Cross Points V CMR CLK Q VDD 2 t PD GND Differential Input Level Propagation Delay V Q DD 2 80% 20% tR x 100% 80% 20% tF t PW t PERIOD Q odc = t PW t PERIOD Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 6 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Parameter Measurement Information, continued Par t 1 V Qx DD 2 Par t 2 V DD Qy 2 t sk(pp) Part-to-Part Skew Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 7 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK Zo = 50Ω Zo = 50Ω nCLK nCLK CLK 3.3V LVPECL HiPerClockS Input R1 50 R2 50 HiPerClockS Input LVHSTL IDT HiPerClockS LVHSTL Driver R1 50 R2 50 R2 50 Figure 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK Zo = 50Ω nCLK R1 100 R3 125 R4 125 3.3V 3.3V Zo = 50Ω LVPECL R1 84 R2 84 HiPerClockS Input Zo = 50Ω nCLK LVDS Receiver Figure 2C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 2.5V R3 120 Zo = 60Ω R4 120 2.5V 3.3V *R3 33 Zo = 50Ω CLK Zo = 50Ω nCLK CLK Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input SSTL R1 120 R2 120 HiPerClockS *Optional – R3 and R4 can be 0Ω Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 8 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Reliability Information Table 6. θJA vs. Air Flow Table for a 8 Lead SOIC θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 93.1°C/W 1 84.3°C/W 2.5 79.6°C/W Transistor Count The transistor count for ICS830S21I-01 is: 214 Package Outline and Package Dimensions Package Outline - M Suffix for 8 Lead SOIC Table 7. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 9 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Ordering Information Table 8. Ordering Information Part/Order Number 830S21AMI-01LF 830S21AMI-01LFT Marking S21AI01L S21AI01L Package “Lead-Free” 8 Lead SOIC “Lead-Free” 8 Lead SOIC Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR 10 ICS830S21AMI-01 REV. A OCTOBER 27, 2008 ICS830S21I-01 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA